Skip to content
Snippets Groups Projects
Commit 29465302 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[hdl] fix bug in DMA controller where the IRQ status clear signal would be stuck at '1'

parent b8d012b5
Branches
Tags
No related merge requests found
......@@ -114,6 +114,7 @@ architecture behaviour of dma_controller is
signal dma_stat_rack_wb : std_logic;
signal dma_stat_irq_wr_wb : std_logic;
signal dma_stat_irq_wr : std_logic;
signal dma_stat_wr : std_logic;
signal dma_cstart_reg : std_logic_vector(31 downto 0);
signal dma_hstartl_reg : std_logic_vector(31 downto 0);
signal dma_hstarth_reg : std_logic_vector(31 downto 0);
......@@ -215,7 +216,8 @@ begin
data_i (0) => dma_stat_irq_wr_wb,
wr_i => dma_stat_wr_wb,
ack_o => dma_stat_wack_wb,
data_o (0) => dma_stat_irq_wr
data_o (0) => dma_stat_irq_wr,
wr_o => dma_stat_wr
);
-- Sync stat
......@@ -266,7 +268,7 @@ begin
when DMA_IDLE =>
-- Clear interrupt when idle status is read.
if dma_stat_irq_wr = '1' then
if dma_stat_irq_wr = '1' and dma_stat_wr = '1' then
dma_irq_reg <= '0';
end if;
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment