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-- SPDX-FileCopyrightText: 2023 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--
--------------------------------------------------------------------------------
-- GN4124 core for PCIe FMC carrier
-- http://www.ohwr.org/projects/gn4124-core
--------------------------------------------------------------------------------
--
-- unit name: opt_rl0_pl_stg
--
-- description: entity toigenerically switch in/out a AXI_ST or avalon_st RL0 pipeline stage.
--
--
--------------------------------------------------------------------------------
--
-- This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later.
-- You may redistribute and modify this source and make products using it
-- under the terms of the CERN-OHL-W v2 or future versions (https://ohwr.org/cern_ohl_w_v2.txt).
--
-- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED
-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see
-- the CERN-OHL-W v2 for applicable conditions.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2023
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity opt_rl0_pl_stg is
generic (
g_IMPLEMENT_PL_STG : boolean := false;
g_DATA_WIDTH : positive := 1;
g_MIMIMISE_TRANSITIONS : boolean := false; -- when implementing a pl_stg controls if it is minimal logic OR "cleaner" for simulation and thus debugging
g_DAT_O_HAS_SRST : boolean := false
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
in_rdy_o : out std_logic;
in_vld_i : in std_logic;
in_dat_i : in std_logic_vector(g_DATA_WIDTH-1 downto 0);
out_rdy_i : in std_logic;
out_vld_o : out std_logic;
out_dat_o : out std_logic_vector(g_DATA_WIDTH-1 downto 0)
);
end entity opt_rl0_pl_stg;
architecture rtl of opt_rl0_pl_stg is
begin
gen_pl : if g_IMPLEMENT_PL_STG generate
signal clk_en_pl_reg : std_logic;
signal clk_en_op_reg : std_logic;
signal use_dat_from_pl_reg : std_logic;
signal pl_dat : std_logic_vector(g_DATA_WIDTH -1 downto 0);
begin
ctrl : entity work.teng_wr_nic_rl0_pl_stage_flowcontrol_srst
generic map (
g_minimal_op_transitions => g_MIMIMISE_TRANSITIONS
) port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
in_rdy_o => in_rdy_o,
in_vld_i => in_vld_i,
out_rdy_i => out_rdy_i,
out_vld_o => out_vld_o,
clk_en_pl_reg_o => clk_en_pl_reg,
clk_en_op_reg_o => clk_en_op_reg,
use_dat_from_pl_reg_o => use_dat_from_pl_reg
);
p_pl_stage : process(clk_i) begin
if rising_edge(clk_i) then
if '1' = clk_en_pl_reg then
pl_dat <= in_dat_i;
end if;
if '1' = clk_en_op_reg then
if '1' = use_dat_from_pl_reg then
out_dat_o <= pl_dat;
else
out_dat_o <= in_dat_i;
end if;
end if;
if (g_DAT_O_HAS_SRST = true) and (rst_n_i = '0') then
out_dat_o <= (others => '0');
pl_dat <= (others => '0');
end if;
end if;
end process p_pl_stage;
end generate;
gen_no_pl : if g_IMPLEMENT_PL_STG = false generate
begin
in_rdy_o <= out_rdy_i;
out_vld_o <= in_vld_i;
out_dat_o <= in_dat_i;
end generate;
end architecture rtl;