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Commit 91bbf080 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wishbone: UART now supports configurable FIFOs

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modules/wishbone/wb_uart/build_wb.sh
View file @ 91bbf080
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wb_simple_uart.html -V simple_uart_wb.vhd -p simple_uart_pkg.vhd --cstyle struct -C wb_uart.h --hstyle record --lang vhdl simple_uart_wb.wb
wbgen2 -D ./doc/wb_simple_uart.html -V simple_uart_wb.vhd -p simple_uart_pkg.vhd -K ../../../testbench/wishbone/include/wb_uart_regs.vh --cstyle defines -C wb_uart.h --hstyle record --lang vhdl simple_uart_wb.wb
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @ 91bbf080
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug 15 10:16:30 2017
-- Created : Tue Aug 25 17:17:50 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -22,78 +22,134 @@ package uart_wbgen2_pkg is
type t_uart_in_registers is record
sr_tx_busy_i : std_logic;
sr_rx_rdy_i : std_logic;
sr_rx_fifo_supported_i : std_logic;
sr_tx_fifo_supported_i : std_logic;
sr_rx_fifo_valid_i : std_logic;
sr_tx_fifo_empty_i : std_logic;
sr_tx_fifo_full_i : std_logic;
sr_rx_fifo_overflow_i : std_logic;
sr_rx_fifo_bytes_i : std_logic_vector(7 downto 0);
rdr_rx_data_i : std_logic_vector(7 downto 0);
host_tdr_rdy_i : std_logic;
host_rdr_data_i : std_logic_vector(7 downto 0);
host_rdr_rdy_i : std_logic;
host_rdr_count_i : std_logic_vector(15 downto 0);
end record;
end record;
constant c_uart_in_registers_init_value: t_uart_in_registers := (
sr_tx_busy_i => '0',
sr_rx_rdy_i => '0',
sr_rx_fifo_supported_i => '0',
sr_tx_fifo_supported_i => '0',
sr_rx_fifo_valid_i => '0',
sr_tx_fifo_empty_i => '0',
sr_tx_fifo_full_i => '0',
sr_rx_fifo_overflow_i => '0',
sr_rx_fifo_bytes_i => (others => '0'),
rdr_rx_data_i => (others => '0'),
host_tdr_rdy_i => '0',
host_rdr_data_i => (others => '0'),
host_rdr_rdy_i => '0',
host_rdr_count_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_uart_out_registers is record
bcr_o : std_logic_vector(31 downto 0);
bcr_wr_o : std_logic;
tdr_tx_data_o : std_logic_vector(7 downto 0);
tdr_tx_data_wr_o : std_logic;
host_tdr_data_o : std_logic_vector(7 downto 0);
host_tdr_data_wr_o : std_logic;
end record;
constant c_uart_out_registers_init_value: t_uart_out_registers := (
bcr_o => (others => '0'),
bcr_wr_o => '0',
tdr_tx_data_o => (others => '0'),
tdr_tx_data_wr_o => '0',
host_tdr_data_o => (others => '0'),
host_tdr_data_wr_o => '0'
);
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
);
-- Output registers (WB slave -> user design)
type t_uart_out_registers is record
sr_rx_fifo_overflow_o : std_logic;
sr_rx_fifo_overflow_load_o : std_logic;
bcr_o : std_logic_vector(31 downto 0);
bcr_wr_o : std_logic;
tdr_tx_data_o : std_logic_vector(7 downto 0);
tdr_tx_data_wr_o : std_logic;
host_tdr_data_o : std_logic_vector(7 downto 0);
host_tdr_data_wr_o : std_logic;
cr_rx_fifo_purge_o : std_logic;
cr_tx_fifo_purge_o : std_logic;
end record;
constant c_uart_out_registers_init_value: t_uart_out_registers := (
sr_rx_fifo_overflow_o => '0',
sr_rx_fifo_overflow_load_o => '0',
bcr_o => (others => '0'),
bcr_wr_o => '0',
tdr_tx_data_o => (others => '0'),
tdr_tx_data_wr_o => '0',
host_tdr_data_o => (others => '0'),
host_tdr_data_wr_o => '0',
cr_rx_fifo_purge_o => '0',
cr_tx_fifo_purge_o => '0'
);
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component simple_uart_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers
);
end component;
end package;
package body uart_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
variable tmp: t_uart_in_registers;
variable tmp: t_uart_in_registers;
begin
tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
return tmp;
tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
tmp.sr_rx_fifo_supported_i := f_x_to_zero(left.sr_rx_fifo_supported_i) or f_x_to_zero(right.sr_rx_fifo_supported_i);
tmp.sr_tx_fifo_supported_i := f_x_to_zero(left.sr_tx_fifo_supported_i) or f_x_to_zero(right.sr_tx_fifo_supported_i);
tmp.sr_rx_fifo_valid_i := f_x_to_zero(left.sr_rx_fifo_valid_i) or f_x_to_zero(right.sr_rx_fifo_valid_i);
tmp.sr_tx_fifo_empty_i := f_x_to_zero(left.sr_tx_fifo_empty_i) or f_x_to_zero(right.sr_tx_fifo_empty_i);
tmp.sr_tx_fifo_full_i := f_x_to_zero(left.sr_tx_fifo_full_i) or f_x_to_zero(right.sr_tx_fifo_full_i);
tmp.sr_rx_fifo_overflow_i := f_x_to_zero(left.sr_rx_fifo_overflow_i) or f_x_to_zero(right.sr_rx_fifo_overflow_i);
tmp.sr_rx_fifo_bytes_i := f_x_to_zero(left.sr_rx_fifo_bytes_i) or f_x_to_zero(right.sr_rx_fifo_bytes_i);
tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
return tmp;
end function;
end package body;
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @ 91bbf080
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_wb.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug 15 10:16:30 2017
-- Created : Tue Aug 25 17:17:50 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -18,298 +18,387 @@ use work.uart_wbgen2_pkg.all;
entity simple_uart_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers
);
end simple_uart_wb;
architecture syn of simple_uart_wb is
signal uart_cr_rx_fifo_purge_dly0 : std_logic ;
signal uart_cr_rx_fifo_purge_int : std_logic ;
signal uart_cr_tx_fifo_purge_dly0 : std_logic ;
signal uart_cr_tx_fifo_purge_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
regs_o.bcr_wr_o <= '0';
regs_o.tdr_tx_data_wr_o <= '0';
rdr_rack_o <= '0';
regs_o.host_tdr_data_wr_o <= '0';
host_rack_o <= '0';
elsif rising_edge(clk_sys_i) then
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
regs_o.sr_rx_fifo_overflow_load_o <= '0';
regs_o.bcr_wr_o <= '0';
regs_o.tdr_tx_data_wr_o <= '0';
rdr_rack_o <= '0';
regs_o.host_tdr_data_wr_o <= '0';
host_rack_o <= '0';
uart_cr_rx_fifo_purge_int <= '0';
uart_cr_tx_fifo_purge_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.bcr_wr_o <= '0';
regs_o.tdr_tx_data_wr_o <= '0';
rdr_rack_o <= '0';
regs_o.host_tdr_data_wr_o <= '0';
host_rack_o <= '0';
ack_in_progress <= '0';
else
regs_o.bcr_wr_o <= '0';
regs_o.tdr_tx_data_wr_o <= '0';
regs_o.host_tdr_data_wr_o <= '0';
end if;
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.sr_rx_fifo_overflow_load_o <= '0';
regs_o.bcr_wr_o <= '0';
regs_o.tdr_tx_data_wr_o <= '0';
rdr_rack_o <= '0';
regs_o.host_tdr_data_wr_o <= '0';
host_rack_o <= '0';
uart_cr_rx_fifo_purge_int <= '0';
uart_cr_tx_fifo_purge_int <= '0';
ack_in_progress <= '0';
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.sr_tx_busy_i;
rddata_reg(1) <= regs_i.sr_rx_rdy_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
regs_o.bcr_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
regs_o.tdr_tx_data_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.rdr_rx_data_i;
rdr_rack_o <= '1';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
regs_o.host_tdr_data_wr_o <= '1';
end if;
rddata_reg(8) <= regs_i.host_tdr_rdy_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.host_rdr_data_i;
host_rack_o <= '1';
rddata_reg(8) <= regs_i.host_rdr_rdy_i;
rddata_reg(24 downto 9) <= regs_i.host_rdr_count_i;
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
regs_o.sr_rx_fifo_overflow_load_o <= '0';
regs_o.bcr_wr_o <= '0';
regs_o.tdr_tx_data_wr_o <= '0';
regs_o.host_tdr_data_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
regs_o.sr_rx_fifo_overflow_load_o <= '1';
end if;
rddata_reg(0) <= regs_i.sr_tx_busy_i;
rddata_reg(1) <= regs_i.sr_rx_rdy_i;
rddata_reg(2) <= regs_i.sr_rx_fifo_supported_i;
rddata_reg(3) <= regs_i.sr_tx_fifo_supported_i;
rddata_reg(4) <= regs_i.sr_rx_fifo_valid_i;
rddata_reg(5) <= regs_i.sr_tx_fifo_empty_i;
rddata_reg(6) <= regs_i.sr_tx_fifo_full_i;
rddata_reg(7) <= regs_i.sr_rx_fifo_overflow_i;
rddata_reg(15 downto 8) <= regs_i.sr_rx_fifo_bytes_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
regs_o.bcr_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
regs_o.tdr_tx_data_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.rdr_rx_data_i;
rdr_rack_o <= '1';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
regs_o.host_tdr_data_wr_o <= '1';
end if;
rddata_reg(8) <= regs_i.host_tdr_rdy_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.host_rdr_data_i;
host_rack_o <= '1';
rddata_reg(8) <= regs_i.host_rdr_rdy_i;
rddata_reg(24 downto 9) <= regs_i.host_rdr_count_i;
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
if (wb_we_i = '1') then
uart_cr_rx_fifo_purge_int <= wrdata_reg(0);
uart_cr_tx_fifo_purge_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end process;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- TX busy
-- RX ready
-- RX FIFO supported
-- TX FIFO supported
-- RX FIFO data valid
-- TX FIFO empty
-- TX FIFO full
-- RX FIFO overflow
regs_o.sr_rx_fifo_overflow_o <= wrdata_reg(7);
-- RX FIFO data count
-- Baudrate divider setting
-- pass-through field: Baudrate divider setting in register: Baudrate control register
regs_o.bcr_o <= wrdata_reg(31 downto 0);
regs_o.bcr_o <= wrdata_reg(31 downto 0);
-- Transmit data
-- pass-through field: Transmit data in register: Transmit data regsiter
regs_o.tdr_tx_data_o <= wrdata_reg(7 downto 0);
regs_o.tdr_tx_data_o <= wrdata_reg(7 downto 0);
-- Received data
-- TX Data
-- pass-through field: TX Data in register: Host VUART Tx register
regs_o.host_tdr_data_o <= wrdata_reg(7 downto 0);
regs_o.host_tdr_data_o <= wrdata_reg(7 downto 0);
-- TX Ready
-- RX Data
-- RX Ready
-- RX FIFO Count
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- RX FIFO purge
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
uart_cr_rx_fifo_purge_dly0 <= '0';
regs_o.cr_rx_fifo_purge_o <= '0';
elsif rising_edge(clk_sys_i) then
uart_cr_rx_fifo_purge_dly0 <= uart_cr_rx_fifo_purge_int;
regs_o.cr_rx_fifo_purge_o <= uart_cr_rx_fifo_purge_int and (not uart_cr_rx_fifo_purge_dly0);
end if;
end process;
-- TX FIFO purge
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
uart_cr_tx_fifo_purge_dly0 <= '0';
regs_o.cr_tx_fifo_purge_o <= '0';
elsif rising_edge(clk_sys_i) then
uart_cr_tx_fifo_purge_dly0 <= uart_cr_tx_fifo_purge_int;
regs_o.cr_tx_fifo_purge_o <= uart_cr_tx_fifo_purge_int and (not uart_cr_tx_fifo_purge_dly0);
end if;
end process;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
wb_ack_o <= ack_sreg(0);
end syn;
modules/wishbone/wb_uart/simple_uart_wb.wb
View file @ 91bbf080
......@@ -28,9 +28,84 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO supported";
description = "1: UART supports RX FIFO";
prefix = "RX_FIFO_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO supported";
description = "1: UART supports TX FIFO";
prefix = "TX_FIFO_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO data valid";
description = "1: there's some data in the RX FIFO";
prefix = "RX_FIFO_VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO empty";
description = "1: TX FIFO is empty";
prefix = "TX_FIFO_EMPTY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO full";
description = "1: TX FIFO is full";
prefix = "TX_FIFO_FULL";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO overflow";
description = "1: RX FIFO overflow occured (latched bit, write 1 to clear)";
prefix = "RX_FIFO_OVERFLOW";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "RX FIFO data count";
description = "Number of bytes currently in the RX FIFO";
prefix = "RX_FIFO_BYTES";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Baudrate control register";
description = "Register controlling the UART baudrate";
......@@ -122,4 +197,28 @@ peripheral {
access_bus=READ_ONLY;
};
};
};
\ No newline at end of file
reg {
name = "UART General Control Register";
prefix = "CR";
field {
name = "RX FIFO purge";
description = "write 1: clears RX FIFO";
prefix = "RX_FIFO_PURGE";
type = MONOSTABLE;
};
field {
name = "TX FIFO purge";
description = "write 1: clears TX FIFO";
prefix = "TX_FIFO_PURGE";
type = MONOSTABLE;
};
};
};
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 91bbf080
......@@ -40,12 +40,16 @@ use work.UART_wbgen2_pkg.all;
entity wb_simple_uart is
generic(
g_WITH_VIRTUAL_UART : boolean;
g_WITH_PHYSICAL_UART : boolean;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0
g_WITH_VIRTUAL_UART : boolean;
g_WITH_PHYSICAL_UART : boolean;
g_WITH_PHYSICAL_UART_FIFO : boolean := false;
g_TX_FIFO_SIZE : integer := 0;
g_RX_FIFO_SIZE : integer := 0;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0
);
port (
......@@ -62,7 +66,7 @@ entity wb_simple_uart is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
int_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
......@@ -73,11 +77,11 @@ architecture arch of wb_simple_uart is
constant c_BAUD_ACC_WIDTH : integer := 16;
signal rx_ready_reg : std_logic;
signal rx_ready : std_logic;
signal uart_bcr : std_logic_vector(31 downto 0);
signal rx_ready_reg : std_logic;
signal rx_ready : std_logic;
signal uart_bcr : std_logic_vector(31 downto 0);
signal rdr_rack : std_logic;
signal rdr_rack : std_logic;
signal host_rack : std_logic;
signal baud_tick : std_logic;
......@@ -91,23 +95,41 @@ architecture arch of wb_simple_uart is
signal regs_in : t_UART_in_registers;
signal regs_out : t_UART_out_registers;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_rd : std_logic;
signal fifo_wr : std_logic;
signal fifo_count : std_logic_vector(f_log2_size(g_VUART_FIFO_SIZE)-1 downto 0);
signal phys_rx_ready, phys_tx_busy : std_logic;
signal phys_rx_data : std_logic_vector(7 downto 0);
signal vuart_fifo_empty : std_logic;
signal vuart_fifo_full : std_logic;
signal vuart_fifo_rd : std_logic;
signal vuart_fifo_wr : std_logic;
signal vuart_fifo_count : std_logic_vector(f_log2_size(g_VUART_FIFO_SIZE)-1 downto 0);
signal tx_fifo_empty : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_rd : std_logic;
signal tx_fifo_wr : std_logic;
signal tx_fifo_count : std_logic_vector(f_log2_size(g_TX_FIFO_SIZE)-1 downto 0);
signal tx_fifo_reset_n : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_overflow : std_logic;
signal rx_fifo_rd : std_logic;
signal rx_fifo_wr : std_logic;
signal rx_fifo_count : std_logic_vector(f_log2_size(g_RX_FIFO_SIZE)-1 downto 0);
signal rx_fifo_reset_n : std_logic;
signal phys_rx_ready, phys_tx_busy, phys_tx_start : std_logic;
signal phys_rx_data, phys_tx_data : std_logic_vector(7 downto 0);
type t_tx_fifo_state is (IDLE, TRANSMIT_PENDING);
signal tx_fifo_state : t_tx_fifo_state;
begin -- arch
gen_check_generics : if (not g_WITH_PHYSICAL_UART and not g_WITH_VIRTUAL_UART) generate
assert FALSE report
assert false report
"wb_simple_uart: dummy configuration (use virtual, physical or both uarts)"
severity FAILURE;
severity failure;
end generate gen_check_generics;
resized_addr(4 downto 0) <= wb_adr_i;
......@@ -115,10 +137,10 @@ begin -- arch
U_Adapter : wb_slave_adapter
generic map (
g_MASTER_USE_STRUCT => TRUE,
g_MASTER_USE_STRUCT => true,
g_MASTER_MODE => CLASSIC,
g_MASTER_GRANULARITY => WORD,
g_SLAVE_USE_STRUCT => FALSE,
g_SLAVE_USE_STRUCT => false,
g_SLAVE_MODE => g_INTERFACE_MODE,
g_SLAVE_GRANULARITY => g_ADDRESS_GRANULARITY)
port map (
......@@ -187,8 +209,8 @@ begin -- arch
rst_n_i => rst_n_i,
baud_tick_i => baud_tick,
txd_o => uart_txd_o,
tx_start_p_i => regs_out.tdr_tx_data_wr_o,
tx_data_i => regs_out.tdr_tx_data_o,
tx_start_p_i => phys_tx_start,
tx_data_i => phys_tx_data,
tx_busy_o => phys_tx_busy);
U_RX : entity work.uart_async_rx
......@@ -202,37 +224,169 @@ begin -- arch
rx_data_o => phys_rx_data);
end generate gen_phys_uart;
gen_phys_fifos : if g_WITH_PHYSICAL_UART_FIFO generate
rx_fifo_wr <= not rx_fifo_full and phys_rx_ready;
tx_fifo_wr <= not tx_fifo_full and regs_out.tdr_tx_data_wr_o;
tx_fifo_reset_n <= rst_n_i and not regs_out.cr_tx_fifo_purge_o;
rx_fifo_reset_n <= rst_n_i and not regs_out.cr_rx_fifo_purge_o;
rx_fifo_rd <= not rx_fifo_empty and rdr_rack;
U_UART_RX_FIFO : generic_sync_fifo
generic map (
g_DATA_WIDTH => 8,
g_SIZE => g_RX_FIFO_SIZE,
g_WITH_COUNT => true,
g_SHOW_AHEAD => true
)
port map (
rst_n_i => rx_fifo_reset_n,
clk_i => clk_sys_i,
d_i => phys_rx_data,
we_i => rx_fifo_wr,
q_o => regs_in.rdr_rx_data_i,
rd_i => rdr_rack,
empty_o => rx_fifo_empty,
full_o => rx_fifo_full,
count_o => rx_fifo_count);
U_UART_TX_FIFO : generic_sync_fifo
generic map (
g_DATA_WIDTH => 8,
g_SIZE => g_TX_FIFO_SIZE,
g_WITH_COUNT => false,
g_SHOW_AHEAD => true
)
port map (
rst_n_i => tx_fifo_reset_n,
clk_i => clk_sys_i,
d_i => regs_out.tdr_tx_data_o,
we_i => tx_fifo_wr,
q_o => phys_tx_data,
rd_i => phys_tx_start,
empty_o => tx_fifo_empty,
full_o => tx_fifo_full);
regs_in.sr_rx_fifo_supported_i <= '1';
regs_in.sr_tx_fifo_supported_i <= '1';
regs_in.sr_rx_fifo_valid_i <= not rx_fifo_empty;
regs_in.sr_rx_rdy_i <= not rx_fifo_empty;
regs_in.sr_rx_fifo_overflow_i <= rx_fifo_overflow;
regs_in.sr_tx_fifo_full_i <= tx_fifo_full;
regs_in.sr_tx_fifo_empty_i <= tx_fifo_empty;
phys_tx_start <= '1' when tx_fifo_state = IDLE and tx_fifo_empty = '0' else '0';
p_rx_fifo_overflow : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rx_fifo_reset_n = '0' then
rx_fifo_overflow <= '0';
else
end if;
end if;
end process;
p_tx_fifo_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if tx_fifo_reset_n = '0' then
tx_fifo_state <= IDLE;
tx_fifo_rd <= '0';
else
case tx_fifo_state is
when IDLE =>
if tx_fifo_empty = '0' then
tx_fifo_rd <= '1';
tx_fifo_state <= TRANSMIT_PENDING;
end if;
when TRANSMIT_PENDING =>
tx_fifo_rd <= '0';
if phys_tx_busy = '0' then
tx_fifo_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
regs_in.sr_tx_busy_i <= tx_fifo_full;
end generate gen_phys_fifos;
gen_phys_nofifos : if not g_WITH_PHYSICAL_UART_FIFO generate
phys_tx_data <= regs_out.tdr_tx_data_o;
phys_tx_start <= regs_out.tdr_tx_data_wr_o and not phys_tx_busy;
regs_in.sr_tx_busy_i <= phys_tx_busy when (g_WITH_PHYSICAL_UART) else '0';
p_drive_rx_ready : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_in.sr_rx_rdy_i <= '0';
int_o <= '0';
regs_in.rdr_rx_data_i <= (others => '0');
else
if rdr_rack = '1' and phys_rx_ready = '0' then
regs_in.sr_rx_rdy_i <= '0';
int_o <= '0';
elsif phys_rx_ready = '1' and g_WITH_PHYSICAL_UART then
regs_in.sr_rx_rdy_i <= '1';
int_o <= '1';
regs_in.rdr_rx_data_i <= phys_rx_data;
elsif regs_out.host_tdr_data_wr_o = '1' and g_WITH_VIRTUAL_UART then
regs_in.sr_rx_rdy_i <= '1';
int_o <= '1';
regs_in.rdr_rx_data_i <= regs_out.host_tdr_data_o;
end if;
end if;
end if;
end process p_drive_rx_ready;
end generate gen_phys_nofifos;
gen_vuart : if (g_WITH_VIRTUAL_UART) generate
fifo_wr <= not fifo_full and regs_out.tdr_tx_data_wr_o;
fifo_rd <= not fifo_empty and not regs_in.host_rdr_rdy_i;
vuart_fifo_wr <= not vuart_fifo_full and regs_out.tdr_tx_data_wr_o;
vuart_fifo_rd <= not vuart_fifo_empty and not regs_in.host_rdr_rdy_i;
U_VUART_FIFO : generic_sync_fifo
generic map (
g_DATA_WIDTH => 8,
g_SIZE => g_VUART_FIFO_SIZE,
g_WITH_COUNT => TRUE)
g_WITH_COUNT => true,
g_SHOW_AHEAD => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
d_i => regs_out.tdr_tx_data_o,
we_i => fifo_wr,
we_i => vuart_fifo_wr,
q_o => regs_in.host_rdr_data_i,
rd_i => fifo_rd,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => fifo_count);
rd_i => vuart_fifo_rd,
empty_o => vuart_fifo_empty,
full_o => vuart_fifo_full,
count_o => vuart_fifo_count);
regs_in.host_rdr_count_i(fifo_count'LEFT downto 0) <= fifo_count;
regs_in.host_rdr_count_i(15 downto fifo_count'length) <= (others => '0');
regs_in.host_rdr_count_i(vuart_fifo_count'left downto 0) <= vuart_fifo_count;
regs_in.host_rdr_count_i(15 downto vuart_fifo_count'length) <= (others => '0');
p_vuart_rx_ready : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_in.host_rdr_rdy_i <= '0';
elsif fifo_rd = '1' then
elsif vuart_fifo_rd = '1' then
regs_in.host_rdr_rdy_i <= '1';
elsif host_rack = '1' then
regs_in.host_rdr_rdy_i <= '0';
......@@ -248,31 +402,6 @@ begin -- arch
regs_in.host_rdr_rdy_i <= '0';
end generate gen_no_vuart;
p_drive_rx_ready : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_in.sr_rx_rdy_i <= '0';
int_o <= '0';
regs_in.rdr_rx_data_i <= (others => '0');
else
if rdr_rack = '1' and phys_rx_ready = '0' and regs_out.host_tdr_data_wr_o = '0' then
regs_in.sr_rx_rdy_i <= '0';
int_o <= '0';
elsif phys_rx_ready = '1' and g_WITH_PHYSICAL_UART then
regs_in.sr_rx_rdy_i <= '1';
int_o <= '1';
regs_in.rdr_rx_data_i <= phys_rx_data;
elsif regs_out.host_tdr_data_wr_o = '1' and g_WITH_VIRTUAL_UART then
regs_in.sr_rx_rdy_i <= '1';
int_o <= '1';
regs_in.rdr_rx_data_i <= regs_out.host_tdr_data_o;
end if;
end if;
end if;
end process p_drive_rx_ready;
regs_in.sr_tx_busy_i <= phys_tx_busy when (g_WITH_PHYSICAL_UART) else '0';
regs_in.host_tdr_rdy_i <= not regs_in.sr_rx_rdy_i;
end arch;
modules/wishbone/wb_uart/xwb_simple_uart.vhd
View file @ 91bbf080
......@@ -39,11 +39,14 @@ entity xwb_simple_uart is
generic(
g_WITH_VIRTUAL_UART : boolean := TRUE;
g_WITH_PHYSICAL_UART : boolean := TRUE;
g_WITH_PHYSICAL_UART_FIFO : boolean := false;
g_TX_FIFO_SIZE : integer := 0;
g_RX_FIFO_SIZE : integer := 0;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0
);
);
port(
clk_sys_i : in std_logic;
......@@ -73,6 +76,9 @@ begin -- arch
g_INTERFACE_MODE => g_INTERFACE_MODE,
g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY,
g_VUART_FIFO_SIZE => g_VUART_FIFO_SIZE,
g_WITH_PHYSICAL_UART_FIFO => g_WITH_PHYSICAL_UART_FIFO,
g_TX_FIFO_SIZE => g_TX_FIFO_SIZE,
g_RX_FIFO_SIZE => g_RX_FIFO_SIZE,
g_PRESET_BCR => g_PRESET_BCR)
port map (
clk_sys_i => clk_sys_i,
......
modules/wishbone/wishbone_pkg.vhd
View file @ 91bbf080
......@@ -944,13 +944,19 @@ package wishbone_pkg is
uart_txd_o : out std_logic);
end component;
component xwb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024);
g_WITH_VIRTUAL_UART : boolean := TRUE;
g_WITH_PHYSICAL_UART : boolean := TRUE;
g_WITH_PHYSICAL_UART_FIFO : boolean := false;
g_TX_FIFO_SIZE : integer := 0;
g_RX_FIFO_SIZE : integer := 0;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0 );
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......
testbench/wishbone/wb_uart/Manifest.py 0 → 100644
View file @ 91bbf080
sim_tool = "modelsim"
top_module="main"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vcom_opt="-mixedsvvh l -2008"
sim_top="main"
syn_device="xc7k70t"
include_dirs=["../../../sim", "../include" ]
files = [ "main.sv" ]
modules = { "local" : [ "../../../" ] }
testbench/wishbone/wb_uart/main.sv 0 → 100644
View file @ 91bbf080
//------------------------------------------------------------------------------
// Copyright CERN 2018
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ps/1ps
`include "vhd_wishbone_master.svh"
`include "wb_uart_regs.vh"
import wishbone_pkg::*;
module dupa;
xwb_simple_uart dut();
endmodule // dupa
class IBusDevice;
CBusAccessor m_acc;
uint64_t m_base;
function new ( CBusAccessor acc, uint64_t base );
m_acc =acc;
m_base = base;
endfunction // new
virtual task write32( uint32_t addr, uint32_t val );
m_acc.write(m_base +addr, val);
endtask // write
virtual task read32( uint32_t addr, output uint32_t val );
uint64_t val64;
m_acc.read(m_base +addr, val64);
val = val64;
endtask // write
endclass // BusDevice
class WBUartDriver extends IBusDevice;
function new(CBusAccessor bus, uint64_t base);
super.new(bus, base);
endfunction // new
protected bit m_with_fifo;
protected byte m_tx_queue[$];
protected byte m_rx_queue[$];
protected bit m_tx_idle;
function automatic uint32_t calc_baudrate( uint64_t baudrate, uint64_t base_clock);
return ( ((( baudrate << 12)) + (base_clock >> 8)) / (base_clock >> 7) );
endfunction
task automatic init( uint32_t baudrate, uint32_t clock_freq, int fifo_en );
uint32_t rv;
read32( `ADDR_UART_SR, rv );
write32(`ADDR_UART_BCR, calc_baudrate( baudrate, clock_freq) );
if(!fifo_en)
m_with_fifo = 0;
else
m_with_fifo = (rv & `UART_SR_RX_FIFO_SUPPORTED) ? 1 : 0;
m_tx_idle = 0;
$display("wb_simple_uart: FIFO supported = %d", m_with_fifo);
endtask // init
task automatic send( byte value );
m_tx_queue.push_back(value);
m_tx_idle = 0;
update();
endtask // send
function automatic byte recv();
if( rx_count() == 0 )
return -1;
return m_rx_queue.pop_front();
endfunction // recv
function automatic int rx_count();
return m_rx_queue.size();
endfunction // rx_count
function automatic bit poll();
return m_rx_queue.size() > 0;
endfunction // has_data
function automatic bit tx_idle();
return m_tx_idle;
endfunction // tx_idle
function automatic bit rx_overflow();
endfunction // rx_overflow
task automatic update();
automatic uint32_t sr;
automatic time ts = $time;
read32( `ADDR_UART_SR, sr );
if( m_with_fifo ) begin
if( sr & `UART_SR_RX_RDY ) begin
automatic uint32_t d;
read32(`ADDR_UART_RDR, d);
// $display("FifoRx: %x", d);
m_rx_queue.push_back(d);
end
if( ! ( sr & `UART_SR_TX_FIFO_FULL ) && m_tx_queue.size() > 0 ) begin
byte d = m_tx_queue.pop_front();
// $display("-> FifoTX %x", d);
write32(`ADDR_UART_TDR, d);
end else if ( !m_tx_queue.size() ) begin
m_tx_idle = 1;
end
end else begin
if( ! ( sr & `UART_SR_TX_BUSY ) && m_tx_queue.size() > 0) begin
byte d = m_tx_queue.pop_front();
// $display("NoFifoTX");
write32(`ADDR_UART_TDR, d);
end else if ( !m_tx_queue.size() ) begin
m_tx_idle = 1;
end
if( sr & `UART_SR_RX_RDY ) begin
automatic uint32_t d;
read32(`ADDR_UART_RDR, d);
// $display("NoFifoRx: %x", d);
m_rx_queue.push_back(d);
end
end
endtask // update
endclass // WBUartDriver
module main;
reg rst_n = 0;
reg clk_62m5 = 0;
always #8ns clk_62m5 <= ~clk_62m5;
initial begin
repeat(20) @(posedge clk_62m5);
rst_n = 1;
end
// the Device Under Test
xwb_simple_uart
#(
.g_WITH_PHYSICAL_UART(1'b1),
.g_WITH_PHYSICAL_UART_FIFO(1'b1),
.g_TX_FIFO_SIZE(64),
.g_RX_FIFO_SIZE(64),
.g_INTERFACE_MODE(PIPELINED),
.g_ADDRESS_GRANULARITY(0)
)
DUT_FIFO
(
.rst_n_i(rst_n),
.clk_sys_i (clk_62m5),
.slave_i (Host1.out),
.slave_o (Host1.in),
.uart_txd_o(txd),
.uart_rxd_i(rxd)
);
// the Device Under Test
xwb_simple_uart
#(
.g_WITH_PHYSICAL_UART(1'b1),
.g_WITH_PHYSICAL_UART_FIFO(1'b0),
.g_INTERFACE_MODE(PIPELINED),
.g_ADDRESS_GRANULARITY(0)
)
DUT_NO_FIFO
(
.rst_n_i(rst_n),
.clk_sys_i (clk_62m5),
.slave_i (Host2.out),
.slave_o (Host2.in),
.uart_txd_o(rxd),
.uart_rxd_i(txd)
);
IVHDWishboneMaster Host1
(
.clk_i (clk_62m5),
.rst_n_i (rst_n));
IVHDWishboneMaster Host2
(
.clk_i (clk_62m5),
.rst_n_i (rst_n));
initial begin
real t;
automatic CWishboneAccessor acc1 = Host1.get_accessor();
automatic WBUartDriver drv_fifo = new( acc1, 0 );
automatic CWishboneAccessor acc2 = Host2.get_accessor();
automatic WBUartDriver drv_no_fifo = new( acc2, 0 );
automatic int i;
acc1.set_mode(PIPELINED);
acc2.set_mode(PIPELINED);
#100ns;
// $stop;
@(posedge rst_n);
@(posedge clk_62m5);
drv_fifo.init(9216000, 62500000, 0);
drv_no_fifo.init(9216000, 62500000, 0);
#1us;
for(i=0;i<100;i++)
begin
drv_no_fifo.send(i);
drv_fifo.send(i);
drv_no_fifo.update();
drv_fifo.update();
end
forever
begin
// $display("%d %d", drv_fifo.tx_idle(), drv_no_fifo.tx_idle() );
drv_fifo.update();
drv_no_fifo.update();
if( drv_fifo.tx_idle() && drv_no_fifo.tx_idle() )
break;
end
$display("TX Complete");
for(i=0;i<500;i++)
begin
drv_fifo.update();
drv_no_fifo.update();
end
$display("TX Idle!");
for(i=0;i<100;i++)
begin
automatic int rx = drv_no_fifo.recv();
if( rx != i )
$error("NoFifo err %x vs %x", i, rx );
rx = drv_fifo.recv();
if( rx != i )
$error("Fifo err %x vs %x", i, rx );
end
$display("Test complete");
$stop;
end // initial begin
endmodule // main
testbench/wishbone/wb_uart/run.do 0 → 100644
View file @ 91bbf080
#vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../include/vme64x_bfm +incdir+../../include +incdir+../include +incdir+../../sim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
vsim -L unisim -L XilinxCoreLib work.main -voptargs=+acc -t 10fs
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 10ms
\ No newline at end of file
testbench/wishbone/wb_uart/wave.do 0 → 100644
View file @ 91bbf080
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/clk_sys_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rst_n_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_adr_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_dat_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_dat_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_cyc_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_sel_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_stb_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_we_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_ack_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_stall_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/int_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/uart_rxd_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/uart_txd_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_ready_reg
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_ready
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/uart_bcr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rdr_rack
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/host_rack
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/baud_tick
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/baud_tick8
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/resized_addr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_in
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_out
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/regs_in
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/regs_out
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_empty
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_full
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_rd
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_wr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_count
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_empty
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_full
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_rd
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_wr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_count
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_reset_n
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_empty
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_full
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_overflow
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_rd
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_wr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_count
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_reset_n
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_rx_ready
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_tx_busy
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_tx_start
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_rx_data
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_tx_data
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_state
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/rst_n_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/clk_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/d_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/we_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/q_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/rd_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/empty_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/full_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/almost_empty_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/almost_full_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/count_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/clk_sys_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rst_n_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_adr_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_dat_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_dat_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_cyc_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_sel_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_stb_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_we_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_ack_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_stall_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/int_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/uart_rxd_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/uart_txd_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_ready_reg
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_ready
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/uart_bcr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rdr_rack
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/host_rack
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/baud_tick
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/baud_tick8
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/resized_addr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_in
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_out
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/regs_in
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/regs_out
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_empty
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_full
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_rd
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_wr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_count
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_empty
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_full
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_rd
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_wr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_count
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_reset_n
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_empty
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_full
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_overflow
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_rd
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_wr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_count
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_reset_n
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_rx_ready
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_tx_busy
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_tx_start
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_rx_data
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_tx_data
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_state
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {12968000000 fs} 0}
configure wave -namecolwidth 298
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {109552789280 fs}
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