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Commits
8649d40d
Commit
8649d40d
authored
Aug 23, 2021
by
Federico Vaga
Browse files
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Merge branch 'release/v1.1.3'
parents
21f2e94e
4cea3a03
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Showing
53 changed files
with
6357 additions
and
1347 deletions
+6357
-1347
CHANGELOG.rst
CHANGELOG.rst
+8
-0
axi4_pkg.vhd
modules/axi/axi4_pkg.vhd
+45
-1
Manifest.py
modules/common/Manifest.py
+1
-0
gc_arbitrated_mux.vhd
modules/common/gc_arbitrated_mux.vhd
+3
-4
gc_big_adder.vhd
modules/common/gc_big_adder.vhd
+0
-1
gc_ds182x_readout.vhd
modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd
+267
-460
gc_dyn_extend_pulse.vhd
modules/common/gc_dyn_extend_pulse.vhd
+0
-1
gc_enc_8b10b.vhd
modules/common/gc_enc_8b10b.vhd
+369
-302
gc_fsm_watchdog.vhd
modules/common/gc_fsm_watchdog.vhd
+2
-2
gc_moving_average.vhd
modules/common/gc_moving_average.vhd
+1
-2
gc_simple_spi_master.vhd
modules/common/gc_simple_spi_master.vhd
+2
-1
gc_word_packer.vhd
modules/common/gc_word_packer.vhd
+3
-3
inferred_sync_fifo.vhd
modules/genrams/common/inferred_sync_fifo.vhd
+1
-1
Manifest.py
modules/wishbone/Manifest.py
+1
-0
wb_axi4lite_bridge.vhd
modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+1
-1
xwb_axi4lite_bridge.vhd
modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+26
-32
wb_ds182x_regs.cheby
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
+9
-1
wb_ds182x_regs.vhd
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd
+114
-110
xwb_ds182x_readout.vhd
modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd
+10
-3
Manifest.py
modules/wishbone/wb_fine_pulse_gen/Manifest.py
+8
-0
fine_pulse_gen_kintex7.vhd
...les/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7.vhd
+248
-0
fine_pulse_gen_kintex7_shared.vhd
...hbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7_shared.vhd
+107
-0
fine_pulse_gen_kintexultrascale.vhd
...one/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale.vhd
+435
-0
fine_pulse_gen_kintexultrascale_shared.vhd
...fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
+271
-0
fine_pulse_gen_wb.vhd
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.vhd
+860
-0
fine_pulse_gen_wb.wb
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.wb
+671
-0
fine_pulse_gen_wbgen2_pkg.vhd
.../wishbone/wb_fine_pulse_gen/fine_pulse_gen_wbgen2_pkg.vhd
+238
-0
xwb_fine_pulse_gen.vhd
modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
+531
-0
xwb_lm32.vhd
modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
+0
-44
build_wb.sh
modules/wishbone/wb_uart/build_wb.sh
+1
-1
simple_uart_pkg.vhd
modules/wishbone/wb_uart/simple_uart_pkg.vhd
+105
-49
simple_uart_wb.vhd
modules/wishbone/wb_uart/simple_uart_wb.vhd
+350
-261
simple_uart_wb.wb
modules/wishbone/wb_uart/simple_uart_wb.wb
+100
-1
wb_simple_uart.vhd
modules/wishbone/wb_uart/wb_simple_uart.vhd
+186
-56
xwb_simple_uart.vhd
modules/wishbone/wb_uart/xwb_simple_uart.vhd
+11
-2
wishbone_pkg.vhd
modules/wishbone/wishbone_pkg.vhd
+11
-5
sim_wishbone.vhd
sim/vhdl/sim_wishbone.vhd
+59
-2
htvic.c
software/htvic/drivers/htvic.c
+3
-0
spi-ocores.c
software/spi-ocores/drivers/spi/spi-ocores.c
+6
-0
Manifest.py
testbench/common/gc_ds182x_readout/Manifest.py
+17
-0
gc_ds182x_readout_tb.vhd
testbench/common/gc_ds182x_readout/gc_ds182x_readout_tb.vhd
+210
-0
wb_fine_pulse_gen_regs.vh
testbench/wishbone/include/wb_fine_pulse_gen_regs.vh
+160
-0
Manifest.py
testbench/wishbone/wb_fine_pulse_gen/Manifest.py
+15
-0
main.sv
testbench/wishbone/wb_fine_pulse_gen/main.sv
+310
-0
run.do
testbench/wishbone/wb_fine_pulse_gen/run.do
+13
-0
Manifest.py
testbench/wishbone/wb_spi/Manifest.py
+8
-0
run.do
testbench/wishbone/wb_spi/run.do
+8
-0
tb_spi.vhd
testbench/wishbone/wb_spi/tb_spi.vhd
+74
-0
Manifest.py
testbench/wishbone/wb_uart/Manifest.py
+14
-0
main.sv
testbench/wishbone/wb_uart/main.sv
+321
-0
run.do
testbench/wishbone/wb_uart/run.do
+12
-0
wave.do
testbench/wishbone/wb_uart/wave.do
+130
-0
gen_sourceid.py
tools/gen_sourceid.py
+1
-1
No files found.
CHANGELOG.rst
View file @
8649d40d
...
...
@@ -9,6 +9,14 @@ Change Log
- Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
- Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
1.1.3 - 2021-08-23
==================
https://www.ohwr.org/project/general-cores/tags/v1.1.2
Fixed
-----
- sw: kernel crash of htvic removal on modern kernel
1.1.2 - 2021-07-29
==================
https://www.ohwr.org/project/general-cores/tags/v1.1.2
...
...
modules/axi/axi4_pkg.vhd
View file @
8649d40d
...
...
@@ -140,7 +140,7 @@ package axi4_pkg is
constant
c_AXI4_RESP_SLVERR
:
std_logic_vector
(
1
downto
0
)
:
=
"10"
;
constant
c_AXI4_RESP_DECERR
:
std_logic_vector
(
1
downto
0
)
:
=
"11"
;
function
f_axi4_full_to_lite
(
function
f_axi4_full_to_lite
(
f
:
t_axi4_full_master_out_32
)
return
t_axi4_lite_master_out_32
;
...
...
@@ -198,6 +198,50 @@ package axi4_pkg is
);
end
component
;
-- AXI4-Full interface, master output ports, 512 bits
type
t_axi4_full_master_out_512
is
record
ARVALID
:
std_logic
;
AWVALID
:
std_logic
;
BREADY
:
std_logic
;
RREADY
:
std_logic
;
WLAST
:
std_logic
;
WVALID
:
std_logic
;
ARID
:
std_logic_vector
(
11
downto
0
);
AWID
:
std_logic_vector
(
11
downto
0
);
ARBURST
:
std_logic_vector
(
1
downto
0
);
ARLOCK
:
std_logic
;
ARSIZE
:
std_logic_vector
(
2
downto
0
);
AWBURST
:
std_logic_vector
(
1
downto
0
);
AWLOCK
:
std_logic
;
AWSIZE
:
std_logic_vector
(
2
downto
0
);
ARPROT
:
std_logic_vector
(
2
downto
0
);
AWPROT
:
std_logic_vector
(
2
downto
0
);
ARADDR
:
std_logic_vector
(
31
downto
0
);
AWADDR
:
std_logic_vector
(
31
downto
0
);
WDATA
:
std_logic_vector
(
511
downto
0
);
ARCACHE
:
std_logic_vector
(
3
downto
0
);
ARLEN
:
std_logic_vector
(
7
downto
0
);
ARQOS
:
std_logic_vector
(
3
downto
0
);
AWCACHE
:
std_logic_vector
(
3
downto
0
);
AWLEN
:
std_logic_vector
(
7
downto
0
);
AWQOS
:
std_logic_vector
(
3
downto
0
);
WSTRB
:
std_logic_vector
(
31
downto
0
);
end
record
;
-- AXI4-Full interface, master input ports, 512 bits
type
t_axi4_full_master_in_512
is
record
ARREADY
:
std_logic
;
AWREADY
:
std_logic
;
BVALID
:
std_logic
;
RLAST
:
std_logic
;
RVALID
:
std_logic
;
WREADY
:
std_logic
;
BID
:
std_logic_vector
(
11
downto
0
);
RID
:
std_logic_vector
(
11
downto
0
);
BRESP
:
std_logic_vector
(
1
downto
0
);
RRESP
:
std_logic_vector
(
1
downto
0
);
RDATA
:
std_logic_vector
(
511
downto
0
);
end
record
;
end
package
;
package
body
axi4_pkg
is
...
...
modules/common/Manifest.py
View file @
8649d40d
...
...
@@ -42,4 +42,5 @@ files = [
"gc_async_counter_diff.vhd"
,
"gc_sync_word_wr.vhd"
,
"gc_sync_word_rd.vhd"
,
"gc_simple_spi_master.vhd"
];
modules/common/gc_arbitrated_mux.vhd
View file @
8649d40d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 20
19-09-09
-- Last update: 20
20-09-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -38,7 +38,6 @@ use ieee.std_logic_1164.all;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
genram_pkg
.
all
;
entity
gc_arbitrated_mux
is
...
...
@@ -67,7 +66,7 @@ entity gc_arbitrated_mux is
q_valid_o
:
out
std_logic
;
-- Index of the input, to which came the currently outputted data word.
q_input_id_o
:
out
std_logic_vector
(
f_log2_
size
(
g_num_inputs
)
-1
downto
0
)
q_input_id_o
:
out
std_logic_vector
(
f_log2_
ceil
(
g_num_inputs
)
-1
downto
0
)
);
end
gc_arbitrated_mux
;
...
...
@@ -130,7 +129,7 @@ begin -- rtl
if
(
unsigned
(
grant
)
/=
0
)
then
q_o
<=
dregs
(
f_onehot_decode
(
grant
));
q_input_id_o
<=
std_logic_vector
(
to_unsigned
(
f_onehot_decode
(
grant
),
f_log2_
size
(
g_num_inputs
)));
q_input_id_o
<=
std_logic_vector
(
to_unsigned
(
f_onehot_decode
(
grant
),
f_log2_
ceil
(
g_num_inputs
)));
q_valid_o
<=
'1'
;
else
q_o
<=
(
others
=>
'X'
);
...
...
modules/common/gc_big_adder.vhd
View file @
8649d40d
...
...
@@ -31,7 +31,6 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
-- Expects registers for inputs. Async outputs.
...
...
modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd
View file @
8649d40d
...
...
@@ -45,7 +45,8 @@ entity gc_ds182x_readout is
onewire_b
:
inout
std_logic
;
-- IO to be connected to the chip(DS1820/DS1822)
id_o
:
out
std_logic_vector
(
63
downto
0
);
-- id_o value
temper_o
:
out
std_logic_vector
(
15
downto
0
);
-- temperature value (refreshed every second)
id_read_o
:
out
std_logic
;
-- id_o value is valid_o
temp_ok_o
:
out
std_logic
;
-- temperature was read and is correct.
id_read_o
:
out
std_logic
;
-- id_o value is valid
id_ok_o
:
out
std_logic
);
-- Same as id_read_o, but not reset with rst_n_i
end
gc_ds182x_readout
;
...
...
@@ -55,18 +56,29 @@ end gc_ds182x_readout;
--=================================================================================================
architecture
arch
of
gc_ds182x_readout
is
constant
SLOT_1US
:
natural
:
=
g_CLOCK_FREQ_KHZ
/
1000
;
-- time slot constants according to specs https://www.maximintegrated.com/en/app-notes/index.mvp/id/162
constant
SLOT_CNT_START
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
0
*
g_CLOCK_FREQ_KHZ
/
40000
,
16
);
constant
SLOT_CNT_START_PLUSONE
:
unsigned
(
15
downto
0
)
:
=
SLOT_CNT_START
+
1
;
constant
SLOT_CNT_SET
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
60
*
g_CLOCK_FREQ_KHZ
/
40000
,
16
);
constant
SLOT_CNT_RD
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
600
*
g_CLOCK_FREQ_KHZ
/
40000
,
16
);
-- 15us
constant
SLOT_CNT_STOP
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
3600
*
g_CLOCK_FREQ_KHZ
/
40000
,
16
);
-- 90us
constant
SLOT_CNT_PRESTOP
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
((
3600-60
)
*
g_CLOCK_FREQ_KHZ
/
40000
,
16
);
constant
SLOT_CNT_START
:
natural
:
=
0
;
-- When the bit is written
constant
SLOT_CNT_SET
:
natural
:
=
2
*
SLOT_1US
;
-- When the bit is read
constant
SLOT_CNT_RD
:
natural
:
=
12
*
SLOT_1US
;
-- When the onewire is not driven anymore.
constant
SLOT_CNT_STOP
:
natural
:
=
60
*
SLOT_1US
;
-- End of the cycle
constant
SLOT_CNT_END
:
natural
:
=
62
*
SLOT_1US
;
-- Number of cycles for a reset (until reaching 0)
constant
SLOT_CNT_RESET
:
natural
:
=
500
*
SLOT_1US
;
constant
READ_ID_HEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"33"
;
constant
CONVERT_HEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"44"
;
constant
READ_TEMPER_HEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"BE"
;
constant
SKIPHEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"CC"
;
constant
SKIP
_
HEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"CC"
;
constant
ID_LEFT
:
integer
:
=
71
;
constant
ID_RIGHT
:
integer
:
=
8
;
...
...
@@ -74,40 +86,49 @@ architecture arch of gc_ds182x_readout is
constant
TEMPER_RIGHT
:
integer
:
=
0
;
constant
TEMPER_DONE_BIT
:
std_logic
:
=
'0'
;
-- The serial line is asserted to this value by the
-- DS1820/DS1822 when the temperature conversion is ready
constant
TEMPER_LGTH
:
unsigned
(
7
downto
0
)
:
=
to_unsigned
(
72
,
8
);
constant
ID_LGTH
:
unsigned
(
7
downto
0
)
:
=
to_unsigned
(
64
,
8
);
type
op_fsm_t
is
(
READ_ID_OP
,
SKIP_ROM_OP1
,
CONV_OP1
,
CONV_OP2
,
SKIP_ROM_OP2
,
READ_TEMP_OP
);
type
cm_fsm_t
is
(
RST_CM
,
PREP_WR_CM
,
WR_CM
,
PREP_RD_CM
,
RD_CM
,
IDLE_CM
);
signal
bit_top
,
bit_cnt
:
unsigned
(
7
downto
0
);
signal
slot_cnt
:
unsigned
(
15
downto
0
);
signal
start_p
,
end_p
,
set_value
,
read_value
,
init_pulse
:
std_logic
;
signal
state_op
,
nxt_state_op
:
op_fsm_t
;
signal
state_cm
,
nxt_state_cm
:
cm_fsm_t
;
signal
crc_vec
,
header
:
std_logic_vector
(
7
downto
0
);
signal
crc_ok
,
init
,
pre_read_p
,
i_id_read
:
std_logic
;
signal
load_temper
,
load_id
,
cm_only
,
pps_p_d
:
std_logic
;
signal
serial_id_out
,
nx_serial_id_out
,
nx_serial_id_oe
:
std_logic
;
signal
i_serial_id_oe
,
serial_idr
:
std_logic
;
signal
end_wr_cm
,
end_rd_cm
,
inc_bit_cnt
,
rst_bit_cnt
:
std_logic
;
signal
shift_header
,
id_cm_reg
:
std_logic
;
signal
cm_reg
:
std_logic_vector
(
71
downto
0
);
signal
shifted_header
:
std_logic_vector
(
7
downto
0
);
signal
pre_init_p
:
std_logic
;
constant
TEMPER_LGTH
:
natural
:
=
72
;
constant
ID_LGTH
:
natural
:
=
64
;
type
op_fsm_t
is
(
READ_ID_OP
,
CONV_OP1
,
SKIP_ROM_OP1
,
READ_TEMP_OP
,
WAIT_PPS
,
SKIP_ROM_OP2
);
type
cm_fsm_t
is
(
RESET_PULSE
,
PRESENCE_PULSE
,
WR_CM
,
RD_CM
,
IDLE_CM
);
signal
bit_cnt
,
bit_top
:
natural
range
0
to
127
;
signal
slot_cnt
:
natural
range
0
to
SLOT_CNT_RESET
;
signal
start_slot
:
std_logic
;
signal
end_p
:
std_logic
;
signal
state_op
:
op_fsm_t
;
signal
state_cm
:
cm_fsm_t
;
-- Set for RESET/PRESENCE slots that lasts > 480uS
signal
long_slot
:
std_logic
;
signal
crc_vec
,
header
:
std_logic_vector
(
7
downto
0
);
signal
cm_only
:
std_logic
;
signal
onewire_oe
,
onewire_in
:
std_logic
;
signal
shift_header
:
std_logic
;
signal
cm_reg
:
std_logic_vector
(
71
downto
0
);
signal
shifted_header
:
std_logic_vector
(
7
downto
0
);
signal
cmd_done
,
cmd_init
,
cmd_start
:
std_logic
;
signal
pps_counter
:
unsigned
(
31
downto
0
);
signal
pps
:
std_logic
;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
gen_external_pps
:
if
not
g_USE_INTERNAL_PPS
generate
pps
<=
pps_p_i
;
-- Delay to ease routing.
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
pps
<=
pps_p_i
;
end
if
;
end
process
;
end
generate
gen_external_pps
;
gen_internal_pps
:
if
g_USE_INTERNAL_PPS
generate
...
...
@@ -131,479 +152,265 @@ begin
end
generate
gen_internal_pps
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Serial data line in tri-state, when not writing data out
onewire_b
<=
serial_id_out
when
i_serial_id_oe
=
'1'
else
'Z'
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps_p_i 1 clock tick delay
pps_p_iDelay
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
pps_p_d
<=
pps
;
end
if
;
end
process
;
---------------------------------------------------------------------------------------------------
-- operations FSM --
---------------------------------------------------------------------------------------------------
op_fsm_transitions
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
cmd_start
<=
'0'
;
cmd_init
<=
'0'
;
if
rst_n_i
=
'0'
then
state_op
<=
READ_ID_OP
;
state_op
<=
READ_ID_OP
;
id_o
<=
(
others
=>
'0'
);
temper_o
<=
(
others
=>
'0'
);
id_read_o
<=
'0'
;
temp_ok_o
<=
'0'
;
cmd_init
<=
'1'
;
else
state_op
<=
nxt_state_op
;
case
state_op
is
when
READ_ID_OP
=>
-- Read the ROM (unique ID). This is done once after reset.
header
<=
READ_ID_HEADER
;
bit_top
<=
ID_LGTH
;
cm_only
<=
'0'
;
if
cmd_done
=
'1'
then
if
crc_vec
=
x"00"
then
-- ID is ok, keep it.
state_op
<=
CONV_OP1
;
id_o
<=
cm_reg
(
ID_LEFT
downto
ID_RIGHT
);
id_read_o
<=
'1'
;
id_ok_o
<=
'1'
;
-- Start conversion.
header
<=
CONVERT_HEADER
;
cm_only
<=
'1'
;
cmd_start
<=
'1'
;
cmd_init
<=
'0'
;
else
-- Try again.
null
;
end
if
;
end
if
;
when
CONV_OP1
=>
if
cmd_done
=
'1'
then
-- Conversion can take at most 750ms
state_op
<=
WAIT_PPS
;
end
if
;
when
WAIT_PPS
=>
if
pps
=
'1'
then
-- Skip rom to directly reads the registers.
header
<=
SKIP_HEADER
;
cm_only
<=
'1'
;
cmd_init
<=
'1'
;
state_op
<=
SKIP_ROM_OP1
;
end
if
;
when
SKIP_ROM_OP1
=>
if
cmd_done
=
'1'
then
-- Read registers
header
<=
READ_TEMPER_HEADER
;
bit_top
<=
TEMPER_LGTH
;
cm_only
<=
'0'
;
cmd_start
<=
'1'
;
state_op
<=
READ_TEMP_OP
;
end
if
;
when
READ_TEMP_OP
=>
if
cmd_done
=
'1'
then
temper_o
<=
cm_reg
(
TEMPER_LEFT
downto
TEMPER_RIGHT
);
if
crc_vec
=
x"00"
then
temp_ok_o
<=
'1'
;
else
temp_ok_o
<=
'0'
;
end
if
;
-- Skip rom to directly reads the registers.
header
<=
SKIP_HEADER
;
cm_only
<=
'1'
;
cmd_init
<=
'1'
;
state_op
<=
SKIP_ROM_OP2
;
end
if
;
when
SKIP_ROM_OP2
=>
if
cmd_done
=
'1'
then
-- Start conversion.
header
<=
CONVERT_HEADER
;
cm_only
<=
'1'
;
cmd_start
<=
'1'
;
state_op
<=
CONV_OP1
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
op_fsm_states
:
process
(
state_op
,
pps
,
crc_ok
)
begin
nxt_state_op
<=
READ_ID_OP
;
case
state_op
is
when
READ_ID_OP
=>
if
pps
=
'1'
and
crc_ok
=
'1'
then
nxt_state_op
<=
CONV_OP1
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
CONV_OP1
=>
if
pps
=
'1'
then
nxt_state_op
<=
SKIP_ROM_OP1
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
SKIP_ROM_OP1
=>
if
pps
=
'1'
then
nxt_state_op
<=
READ_TEMP_OP
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
READ_TEMP_OP
=>
if
pps
=
'1'
then
nxt_state_op
<=
SKIP_ROM_OP2
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
SKIP_ROM_OP2
=>
if
pps
=
'1'
then
nxt_state_op
<=
CONV_OP2
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
CONV_OP2
=>
if
pps
=
'1'
then
nxt_state_op
<=
SKIP_ROM_OP1
;
else
nxt_state_op
<=
state_op
;
end
if
;
end
case
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
op_fsm_outputs
:
process
(
state_op
,
state_cm
,
crc_ok
,
pps
,
cm_only
)
begin
header
<=
READ_ID_HEADER
;
bit_top
<=
ID_LGTH
;
load_temper
<=
'0'
;
load_id
<=
'0'
;
cm_only
<=
'0'
;
case
state_op
is
when
READ_ID_OP
=>
-- Read the ROM (unique ID). This is done once after reset.
header
<=
READ_ID_HEADER
;
bit_top
<=
ID_LGTH
;
if
state_cm
=
IDLE_CM
then
load_id
<=
crc_ok
;
end
if
;
when
CONV_OP1
=>
-- Start conversion.
header
<=
CONVERT_HEADER
;
cm_only
<=
'1'
;
when
SKIP_ROM_OP1
=>
-- Skip rom to directly reads the registers.
header
<=
SKIPHEADER
;
cm_only
<=
'1'
;
when
READ_TEMP_OP
=>
-- Read registers
header
<=
READ_TEMPER_HEADER
;
bit_top
<=
TEMPER_LGTH
;
if
state_cm
=
IDLE_CM
then
load_temper
<=
crc_ok
and
pps
;
end
if
;
when
SKIP_ROM_OP2
=>
-- Skip rom to directly reads the registers.
header
<=
SKIPHEADER
;
cm_only
<=
'1'
;
when
CONV_OP2
=>
-- Start conversion.
header
<=
CONVERT_HEADER
;
cm_only
<=
'1'
;
when
others
=>
null
;
end
case
;
end
process
;
---------------------------------------------------------------------------------------------------
-- commands FSM --
---------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- commands FSM --
-------------------------------------------------------------------------------------------
cm_fsm_transitions
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
shift_header
<=
'0'
;
onewire_oe
<=
'0'
;
long_slot
<=
'0'
;
onewire_oe
<=
'0'
;
start_slot
<=
'0'
;
cmd_done
<=
'0'
;
if
rst_n_i
=
'0'
then
state_cm
<=
RST_CM
;
state_cm
<=
IDLE_CM
;
cm_reg
<=
(
others
=>
'0'
);
else
state_cm
<=
nxt_state_cm
;
case
state_cm
is
when
IDLE_CM
=>
bit_cnt
<=
0
;
if
cmd_init
=
'1'
then
state_cm
<=
RESET_PULSE
;
start_slot
<=
'1'
;
elsif
cmd_start
=
'1'
then
state_cm
<=
WR_CM
;
shifted_header
<=
header
;
start_slot
<=
'1'
;
end
if
;
when
RESET_PULSE
=>
-- Reset pulse: set to 0
long_slot
<=
'1'
;
-- Set to 0.
onewire_oe
<=
'1'
;
crc_vec
<=
(
others
=>
'0'
);
shifted_header
<=
header
;
if
end_p
=
'1'
then
state_cm
<=
PRESENCE_PULSE
;
end
if
;
when
PRESENCE_PULSE
=>
-- Presence pulse.
long_slot
<=
'1'
;
-- Do not drive
onewire_oe
<=
'0'
;
if
end_p
=
'1'
then
state_cm
<=
WR_CM
;
end
if
;
when
WR_CM
=>
-- Shift at end of slot.
-- Low during init pulse.
if
slot_cnt
<
SLOT_CNT_SET
then
onewire_oe
<=
'1'
;
elsif
slot_cnt
>=
SLOT_CNT_STOP
then
onewire_oe
<=
'0'
;
else
onewire_oe
<=
not
shifted_header
(
0
);
end
if
;
if
end_p
=
'1'
then
-- End of slot
if
bit_cnt
=
7
then
-- End of command.
bit_cnt
<=
0
;
if
cm_only
=
'0'
then
state_cm
<=
RD_CM
;
else
state_cm
<=
IDLE_CM
;
cmd_done
<=
'1'
;
end
if
;
else
-- Next bit
shifted_header
<=
'0'
&
shifted_header
(
7
downto
1
);
bit_cnt
<=
bit_cnt
+
1
;
end
if
;
end
if
;
when
RD_CM
=>
-- Low during init pulse.
if
slot_cnt
<
SLOT_CNT_SET
then
onewire_oe
<=
'1'
;
else
onewire_oe
<=
'0'
;
if
slot_cnt
=
SLOT_CNT_RD
then
-- Sample
cm_reg
<=
onewire_in
&
cm_reg
(
cm_reg
'left
downto
1
);
-- Update CRC
crc_vec
(
0
)
<=
onewire_in
xor
crc_vec
(
7
);
crc_vec
(
3
downto
1
)
<=
crc_vec
(
2
downto
0
);
crc_vec
(
4
)
<=
(
onewire_in
xor
crc_vec
(
7
))
xor
crc_vec
(
3
);
crc_vec
(
5
)
<=
(
onewire_in
xor
crc_vec
(
7
))
xor
crc_vec
(
4
);
crc_vec
(
7
downto
6
)
<=
crc_vec
(
6
downto
5
);
bit_cnt
<=
bit_cnt
+
1
;
end
if
;
end
if
;
if
end_p
=
'1'
then
-- End of slot
if
bit_cnt
=
bit_top
then
-- End of command
state_cm
<=
IDLE_CM
;
cmd_done
<=
'1'
;
end
if
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cm_fsm_states
:
process
(
state_cm
,
start_p
,
end_wr_cm
,
end_rd_cm
,
crc_ok
,
state_op
,
cm_only
,
pps_p_d
)
begin
nxt_state_cm
<=
RST_CM
;
case
state_cm
is
when
RST_CM
=>
if
start_p
=
'1'
then
nxt_state_cm
<=
PREP_WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
PREP_WR_CM
=>
if
start_p
=
'1'
then
nxt_state_cm
<=
WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
WR_CM
=>
if
end_wr_cm
=
'1'
then
if
cm_only
=
'0'
then
nxt_state_cm
<=
PREP_RD_CM
;
else
nxt_state_cm
<=
IDLE_CM
;
end
if
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
PREP_RD_CM
=>
if
start_p
=
'1'
then
nxt_state_cm
<=
RD_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
RD_CM
=>
if
end_rd_cm
=
'1'
then
nxt_state_cm
<=
IDLE_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
IDLE_CM
=>
if
state_op
=
READ_ID_OP
then
if
crc_ok
=
'0'
then
nxt_state_cm
<=
RST_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
elsif
state_op
=
READ_TEMP_OP
then
-- At this moment I will send a Conv temper_o command
if
pps_p_d
=
'1'
then
nxt_state_cm
<=
PREP_WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
elsif
(
state_op
=
CONV_OP1
)
or
(
state_op
=
CONV_OP2
)
then
-- At this moment I will restart a temper_o read
if
pps_p_d
=
'1'
then
nxt_state_cm
<=
PREP_WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
elsif
(
state_op
=
SKIP_ROM_OP1
)
or
(
state_op
=
SKIP_ROM_OP2
)
then
-- At this moment I will restart
if
pps_p_d
=
'1'
then
nxt_state_cm
<=
RST_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
end
case
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cm_fsm_outputs
:
process
(
state_cm
,
bit_cnt
,
pre_read_p
,
crc_vec
,
start_p
,
shifted_header
,
init_pulse
,
read_value
,
pre_init_p
)
begin
inc_bit_cnt
<=
'0'
;
nx_serial_id_out
<=
'0'
;
shift_header
<=
'0'
;
id_cm_reg
<=
'0'
;
nx_serial_id_oe
<=
'0'
;
rst_bit_cnt
<=
'0'
;
init
<=
'0'
;
crc_ok
<=
'0'
;
case
state_cm
is
when
RST_CM
=>
-- Reset pulse.
rst_bit_cnt
<=
'1'
;
nx_serial_id_out
<=
'0'
;
nx_serial_id_oe
<=
'1'
;
init
<=
start_p
;
when
PREP_WR_CM
=>
-- Presence pulse.
rst_bit_cnt
<=
start_p
;
nx_serial_id_oe
<=
'0'
;
nx_serial_id_out
<=
'0'
;
when
WR_CM
=>
shift_header
<=
start_p
;
inc_bit_cnt
<=
start_p
;
rst_bit_cnt
<=
'0'
;
nx_serial_id_out
<=
shifted_header
(
0
)
and
(
not
init_pulse
);
if
bit_cnt
<
to_unsigned
(
7
,
bit_cnt
'length
)
then
nx_serial_id_oe
<=
not
pre_init_p
;
else
nx_serial_id_oe
<=
not
pre_read_p
;
end
if
;
when
PREP_RD_CM
=>
rst_bit_cnt
<=
start_p
;
nx_serial_id_oe
<=
'0'
;
nx_serial_id_out
<=
'0'
;
when
RD_CM
=>
inc_bit_cnt
<=
start_p
;
rst_bit_cnt
<=
'0'
;
nx_serial_id_out
<=
not
init_pulse
;
id_cm_reg
<=
read_value
;
nx_serial_id_oe
<=
init_pulse
;
when
IDLE_CM
=>
if
crc_vec
=
x"00"
then
crc_ok
<=
'1'
;
else
crc_ok
<=
'0'
;
end
if
;
init
<=
'1'
;
end
case
;
end
process
;
---------------------------------------------------------------------------------------------------
-- time slots --
---------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- time slots --
-------------------------------------------------------------------------------------------
-- Generates time slots
-- Reset pulse
-- Read time slot
-- Write time slots
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
slot_cnt
(
slot_cnt
'left
)
<=
'1'
;
slot_cnt
(
slot_cnt
'left
-1
downto
0
)
<=
(
others
=>
'0'
);
start_p
<=
'0'
;
end_p
<=
'0'
;
set_value
<=
'0'
;
read_value
<=
'0'
;
init_pulse
<=
'0'
;
pre_init_p
<=
'0'
;
pre_read_p
<=
'0'
;
if
rst_n_i
=
'0'
or
start_slot
=
'1'
then
slot_cnt
<=
0
;
end_p
<=
'0'
;
else
-- Slot counter
if
init
=
'1'
then
slot_cnt
(
slot_cnt
'left
)
<=
'1'
;
slot_cnt
(
slot_cnt
'left
-
1
downto
0
)
<=
(
others
=>
'0'
);
elsif
slot_cnt
=
SLOT_CNT_STOP
then
slot_cnt
<=
(
others
=>
'0'
);
else
slot_cnt
<=
slot_cnt
+
1
;
end
if
;
-- Time slot start pulse
if
slot_cnt
=
SLOT_CNT_START
then
start_p
<=
'1'
;
else
start_p
<=
'0'
;
end
if
;
if
((
slot_cnt
>
SLOT_CNT_START
)
and
(
slot_cnt
<
SLOT_CNT_SET
))
then
init_pulse
<=
'1'
;
else
init_pulse
<=
'0'
;
end
if
;
if
((
slot_cnt
>
SLOT_CNT_PRESTOP
)
and
(
slot_cnt
<
SLOT_CNT_STOP
))
then
pre_init_p
<=
'1'
;
else
pre_init_p
<=
'0'
;
end
if
;
if
(((
slot_cnt
>
SLOT_CNT_PRESTOP
)
and
(
slot_cnt
<=
SLOT_CNT_STOP
))
or
(
slot_cnt
<=
SLOT_CNT_START_PLUSONE
))
then
pre_read_p
<=
'1'
;
else
pre_read_p
<=
'0'
;
end
if
;
-- End of time slot pulse
if
slot_cnt
=
SLOT_CNT_START
then
if
end_p
=
'1'
then
slot_cnt
<=
0
;
end_p
<=
'0'
;
elsif
(
long_slot
=
'1'
and
slot_cnt
=
SLOT_CNT_RESET
)
or
(
long_slot
=
'0'
and
slot_cnt
=
SLOT_CNT_END
)
then
-- End of slot, start next one.
end_p
<=
'1'
;
else
slot_cnt
<=
slot_cnt
+
1
;
end_p
<=
'0'
;
end
if
;
-- Pulse to write value on serial link
if
slot_cnt
=
SLOT_CNT_SET
then
set_value
<=
'1'
;
else
set_value
<=
'0'
;
end
if
;
-- Pulse to read value on serial link
if
slot_cnt
=
SLOT_CNT_RD
then
read_value
<=
'1'
;
else
read_value
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
-------------------------------------------------------------------------------------------
-- serdes --
-------------------------------------------------------------------------------------------
-- Serial data line in tri-state, when not writing data out
onewire_b
<=
'0'
when
onewire_oe
=
'1'
else
'Z'
;
---------------------------------------------------------------------------------------------------
-- serdes --
---------------------------------------------------------------------------------------------------
-- Data serializer bit counter
BitCnt_p
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
bit_cnt
<=
(
others
=>
'0'
);
else
if
rst_bit_cnt
=
'1'
then
bit_cnt
<=
(
others
=>
'0'
);
elsif
inc_bit_cnt
=
'1'
then
bit_cnt
<=
bit_cnt
+
1
;
end
if
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Data serializer shift register
ShiftReg_p
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
shifted_header
<=
READ_ID_HEADER
;
cm_reg
<=
(
others
=>
'0'
);
serial_idr
<=
'0'
;
serial_id_out
<=
'0'
;
i_serial_id_oe
<=
'0'
;
id_o
<=
(
others
=>
'0'
);
i_id_read
<=
'0'
;
id_read_o
<=
'0'
;
crc_vec
<=
(
others
=>
'0'
);
temper_o
<=
(
others
=>
'0'
);
onewire_in
<=
'0'
;
else
-- Samples serial input
serial_idr
<=
onewire_b
;
-- Shifts command out
if
init
=
'1'
then
shifted_header
<=
header
;
elsif
shift_header
=
'1'
then
shifted_header
(
shifted_header
'left
-1
downto
0
)
<=
shifted_header
(
shifted_header
'left
downto
1
);
shifted_header
(
shifted_header
'left
)
<=
'0'
;
end
if
;
-- Computes CRC on read data (include the received CRC itself, if no errror crc_vec = X"00")
if
init
=
'1'
then
crc_vec
<=
(
others
=>
'0'
);
elsif
id_cm_reg
=
'1'
then
crc_vec
(
0
)
<=
serial_idr
xor
crc_vec
(
7
);
crc_vec
(
3
downto
1
)
<=
crc_vec
(
2
downto
0
);
crc_vec
(
4
)
<=
(
serial_idr
xor
crc_vec
(
7
))
xor
crc_vec
(
3
);
crc_vec
(
5
)
<=
(
serial_idr
xor
crc_vec
(
7
))
xor
crc_vec
(
4
);
crc_vec
(
7
downto
6
)
<=
crc_vec
(
6
downto
5
);
end
if
;
-- Stores incoming data
if
(
id_cm_reg
=
'1'
)
then
cm_reg
(
cm_reg
'left
-
1
downto
0
)
<=
cm_reg
(
cm_reg
'left
downto
1
);
cm_reg
(
cm_reg
'left
)
<=
serial_idr
;
end
if
;
-- Updates serial output data
serial_id_out
<=
nx_serial_id_out
;
-- Updates serial output enable
i_serial_id_oe
<=
nx_serial_id_oe
;
-- Stores id_o in register
if
(
load_id
=
'1'
)
then
i_id_read
<=
'1'
;
id_o
<=
cm_reg
(
ID_LEFT
downto
ID_RIGHT
);
end
if
;
-- Stores temperature in register
if
(
load_temper
=
'1'
)
then
temper_o
<=
cm_reg
(
TEMPER_LEFT
downto
TEMPER_RIGHT
);
end
if
;
-- Delays id_o read
id_read_o
<=
i_id_read
;
onewire_in
<=
onewire_b
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Value on id_o port is valid_o
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
state_cm
=
IDLE_CM
then
id_ok_o
<=
crc_ok
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Detects end of read or end of write command
end_wr_cm
<=
'1'
when
(
bit_cnt
=
to_unsigned
(
7
,
bit_cnt
'length
))
and
(
inc_bit_cnt
=
'1'
)
else
'0'
;
end_rd_cm
<=
'1'
when
(
bit_cnt
=
bit_top
)
else
'0'
;
end
arch
;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
modules/common/gc_dyn_extend_pulse.vhd
View file @
8649d40d
...
...
@@ -29,7 +29,6 @@ use ieee.NUMERIC_STD.all;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
genram_pkg
.
all
;
entity
gc_dyn_extend_pulse
is
generic
...
...
modules/common/gc_enc_8b10b.vhd
View file @
8649d40d
--------------------------------------------------------------------------------
-- GSI
-- General Cores Library
-- https://www.ohwr.org/projects/general-cores
--------------------------------------------------------------------------------
--! @file enc_8b10b.vhd
--! Standard library
library
ieee
;
--! Standard packages
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
-------------------------------------------------------------------------------
-- --
-- GSI Darmstadt, Dept. BEL: 8b10b Encoder--
-- --
-------------------------------------------------------------------------------
--
-- unit name:
enc_8b10b
-- unit name:
enc_8b10b
--
--! @brief 8b/10b Encoder \n
--! This module provides 8bit-to-10bit encoding. \n
--! It accepts 8-bit parallel data input and generates 10-bit encoded data \n
--! output in accordance with the 8b/10b standard. IO latency is one clock
--! cycle. \n
--
--
-- description: 8b/10b Encoder
-- This module provides 8bit-to-10bit encoding. It accepts 8-bit parallel
-- data input and generates 10-bit encoded data output in accordance with
--! @author Mathias Kreider\n
--! m.kreider@gsi.de
--
--
-- This approach uses a mix of LUTs and stacked ifs, unlike the suggested
-- approach that only used gates. This uses more logic cells, but also runs
-- about twice as fast. The reverse vector function is used because all code
-- tables are provided in literature as LSB first. This way, the sourcecode
--! @date 18.02.2009
--
--
--------------------------------------------------------------------------------
-- Copyright GSI 2009-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
--! @version 1.0
--
--! @details This approach uses a mix of LUTs and stacked ifs, unlike the \n
--! suggested approach that only used gates. This uses more logic cells, but \n
--! also runs about twice as fast. \n
--! The reverse vector function is used because all code tables are provided \n
--! in literature as LSB first. This way, the sourcecode is easier to \n
--! compare. \n
--!
--! <b>Dependencies:</b>\n
--! -
--!
--! <b>References:</b>\n
--! -
--!
--! <b>Modified by:</b>\n
--! Author: Vladimir Cherkashyn\n
--! v.cherkashyn@gsi.de
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! 23.02.2009 mk cleanup\n
--! formatting, commenting
--! 16.06.2009 vc major rewrite with FSM \n
--! fixed disparity tables, formatting
-------------------------------------------------------------------------------
--! @todo Optimize, test in real design
--
-------------------------------------------------------------------------------
--=============================================================================
--/////////////////////////////////////////////////////////////////////////////
--! Entity declaration for enc_8b10b
--=============================================================================
entity
gc_enc_8b10b
is
generic
(
(
g_
use_internal_running_disparity
:
boolean
:
=
true
);
port
(
(
clk_i
:
in
std_logic
;
-- byte clock, trigger on rising edge
rst_n_i
:
in
std_logic
;
-- reset, assert HI
ctrl_i
:
in
std_logic
;
-- control char, assert HI
in_8b_i
:
in
std_logic_vector
(
7
downto
0
);
-- 8bit input
err_o
:
out
std_logic
;
-- HI if ctrl_i is HI and input is not a valid control byte
dispar_i
:
in
std_logic
:
=
'0'
;
dispar_o
:
out
std_logic
;
-- running disparity: HI = +1, LO = 0
out_10b_o
:
out
std_logic_vector
(
9
downto
0
)
-- 10bit codeword output
clk_i
:
in
std_logic
;
--! byte clock, trigger on rising edge
rst_n_i
:
in
std_logic
;
--! reset, assert HI
ctrl_i
:
in
std_logic
;
--! control char, assert HI
in_8b_i
:
in
std_logic_vector
(
7
downto
0
);
--! 8bit input
err_o
:
out
std_logic
;
--! HI if ctrl_i is HI and input is not a valid control byte
dispar_i
:
in
std_logic
:
=
'0'
;
dispar_o
:
out
std_logic
;
--! running disparity: HI = +1, LO = 0
out_10b_o
:
out
std_logic_vector
(
9
downto
0
)
--! 10bit codeword output
);
end
gc_enc_8b10b
;
--=============================================================================
--/////////////////////////////////////////////////////////////////////////////
--! Architecture Declaration rtl of enc_8b10b - 8b10b encoding
--=============================================================================
architecture
rtl
of
gc_enc_8b10b
is
--=============================================================================
-- LOOKUP TABLES
--=============================================================================
constant
c_RD_MINUS
:
std_logic
:
=
'0'
;
constant
c_RD_PLUS
:
std_logic
:
=
'1'
;
-- type for 5b/6b Code Table
type
t_enc_5b_6b
is
array
(
integer
range
<>
)
of
std_logic_vector
(
5
downto
0
);
-- type for 5b/6b Code Table
type
t_enc_3b_4b
is
array
(
integer
range
<>
)
of
std_logic_vector
(
3
downto
0
);
-- 5b/6b Code Table
constant
c_ENC_5B_6B_TABLE
:
t_enc_5b_6b
(
0
to
31
)
:
=
(
"100111"
,
-- D00
"011101"
,
-- D01
"101101"
,
-- D02
"110001"
,
-- D03
"110101"
,
-- D04
"101001"
,
-- D05
"011001"
,
-- D06
"111000"
,
-- D07
"111001"
,
-- D08
"100101"
,
-- D09
"010101"
,
-- D10
"110100"
,
-- D11
"001101"
,
-- D12
"101100"
,
-- D13
"011100"
,
-- D14
"010111"
,
-- D15
"011011"
,
-- D16
"100011"
,
-- D17
"010011"
,
-- D18
"110010"
,
-- D19
"001011"
,
-- D20
"101010"
,
-- D21
"011010"
,
-- D22
"111010"
,
-- D23
"110011"
,
-- D24
"100110"
,
-- D25
"010110"
,
-- D26
"110110"
,
-- D27
"001110"
,
-- D28
"101110"
,
-- D29
"011110"
,
-- D30
"101011"
);
-- D31
-- 5b/6b Disparity Table
constant
c_DISPAR_6B
:
std_logic_vector
(
0
to
31
)
:
=
(
"11101000100000011000000110010111"
);
-- 3b/4b Code Table
constant
c_ENC_3B_4B_TABLE
:
t_enc_3b_4b
(
0
to
7
)
:
=
(
"1011"
,
-- Dx0
"1001"
,
-- Dx1
"0101"
,
-- Dx2
"1100"
,
-- Dx3
"1101"
,
-- Dx4
"1010"
,
-- Dx5
"0110"
,
-- Dx6
"1110"
);
-- DxP7
-- 3b/4b Disparity Table
constant
c_DISPAR_4B
:
std_logic_vector
(
0
to
7
)
:
=
(
--=============================================================================
-- FUNCTIONS
--=============================================================================
--=============================================================================
-- INTERNAL SIGNALS
--! function f_reverse_vector - bit reversal
function
f_reverse_vector
(
a
:
in
std_logic_vector
)
return
std_logic_vector
is
variable
v_result
:
std_logic_vector
(
a
'REVERSE_RANGE
);
begin
for
i
in
a
'RANGE
loop
v_result
(
i
)
:
=
a
(
i
);
end
loop
;
return
v_result
;
end
;
-- function f_reverse_vector
--=============================================================================
-- LOOKUP TABLES
--=============================================================================
constant
c_RD_MINUS
:
std_logic
:
=
'0'
;
constant
c_RD_PLUS
:
std_logic
:
=
'1'
;
--! type for 5b/6b Code Table
type
t_enc_5b_6b
is
array
(
integer
range
<>
)
of
std_logic_vector
(
5
downto
0
);
--! type for 5b/6b Code Table
type
t_enc_3b_4b
is
array
(
integer
range
<>
)
of
std_logic_vector
(
3
downto
0
);
--! 5b/6b Code Table
constant
c_enc_5b_6b_table
:
t_enc_5b_6b
(
0
to
31
)
:
=
(
"100111"
,
-- D00
"011101"
,
-- D01
"101101"
,
-- D02
"110001"
,
-- D03
"110101"
,
-- D04
"101001"
,
-- D05
"011001"
,
-- D06
"111000"
,
-- D07
"111001"
,
-- D08
"100101"
,
-- D09
"010101"
,
-- D10
"110100"
,
-- D11
"001101"
,
-- D12
"101100"
,
-- D13
"011100"
,
-- D14
"010111"
,
-- D15
"011011"
,
-- D16
"100011"
,
-- D17
"010011"
,
-- D18
"110010"
,
-- D19
"001011"
,
-- D20
"101010"
,
-- D21
"011010"
,
-- D22
"111010"
,
-- D23
"110011"
,
-- D24
"100110"
,
-- D25
"010110"
,
-- D26
"110110"
,
-- D27
"001110"
,
-- D28
"101110"
,
-- D29
"011110"
,
-- D30
"101011"
);
-- D31
--! 5b/6b Disparity Table
constant
c_disPar_6b
:
std_logic_vector
(
0
to
31
)
:
=
(
"11101000100000011000000110010111"
);
--! 3b/4b Code Table
constant
c_enc_3b_4b_table
:
t_enc_3b_4b
(
0
to
7
)
:
=
(
"1011"
,
-- Dx0
"1001"
,
-- Dx1
"0101"
,
-- Dx2
"1100"
,
-- Dx3
"1101"
,
-- Dx4
"1010"
,
-- Dx5
"0110"
,
-- Dx6
"1110"
);
-- DxP7
--! 3b/4b Disparity Table
constant
c_disPar_4b
:
std_logic_vector
(
0
to
7
)
:
=
(
"10001001"
);
--=============================================================================
-- INTERNAL SIGNALS
--=============================================================================
signal
s_ind5b
:
integer
:
=
0
;
--! LUT 5b index
signal
s_ind3b
:
integer
:
=
0
;
--! LUT 3b index
signal
s_val6bit
:
std_logic_vector
(
5
downto
0
);
--! 6bit code
signal
s_val6bit_n
:
std_logic_vector
(
5
downto
0
);
--! 6bit code inverted
signal
s_val4bit
:
std_logic_vector
(
3
downto
0
);
--! 4bit code
signal
s_val4bit_n
:
std_logic_vector
(
3
downto
0
);
--! 4bit code inverted
--! code disparity 6b code: HI = uneven number of bits, LO = even, neutral disp
signal
s_dP6bit
:
std_logic
:
=
'0'
;
--! code disparity 4b code: HI = uneven number of bits, LO = even, neutral disp
signal
s_dP4bit
:
std_logic
:
=
'0'
;
signal
s_in_8b_reg
:
std_logic_vector
(
7
downto
0
);
--! input 8b signal buffer
signal
s_out_10b
,
s_out_10b_reg
:
std_logic_vector
(
9
downto
0
)
:
=
(
others
=>
'0'
);
--! output 10b signal buffer
signal
s_err
,
s_err_reg
:
std_logic
;
--! output err signal buffer
signal
s_ctrl_reg
:
std_logic
;
--! output dispar, ctrl signal buffers
signal
s_dpTrack
:
std_logic
:
=
c_RD_MINUS
;
--! current disparity: Hi = +1, LO = 0
signal
s_RunDisp
:
std_logic
;
--! running disparity register
signal
s_RunDisp_reg
:
std_logic
;
--! running disparity register
signal
s_RunDisp_comb
:
std_logic
;
--! running disparity register
signal
s_ind5b
:
integer
:
=
0
;
-- LUT 5b index
signal
s_ind3b
:
integer
:
=
0
;
-- LUT 3b index
signal
s_val6bit
:
std_logic_vector
(
5
downto
0
);
-- 6bit code
signal
s_val6bit_n
:
std_logic_vector
(
5
downto
0
);
-- 6bit code inverted
signal
s_val4bit
:
std_logic_vector
(
3
downto
0
);
-- 4bit code
begin
-- code disparity 6b code: HI = uneven number of bits, LO = even, neutral disp
signal
s_dP6bit
:
std_logic
:
=
'0'
;
-- code disparity 4b code: HI = uneven number of bits, LO = even, neutral disp
s_RunDisp
<=
s_RunDisp_reg
when
g_use_internal_running_disparity
else
dispar_i
;
dispar_o
<=
s_RunDisp_comb
;
--=============================================================================
-- CONCURRENT COMMANDS
--=============================================================================
-- output 10b signal buffer
signal
s_out_10b
,
s_out_10b_reg
:
std_logic_vector
(
9
downto
0
)
:
=
(
others
=>
'0'
);
signal
s_in_8b_reg
:
std_logic_vector
(
7
downto
0
);
-- input
8b signal buffer
signal
s_err
,
s_err_reg
:
std_logic
;
-- output err signal buffer
-- use 3bit at 7-5 as index for 4bit code and disparity table \n
s_ind3b
<=
to_integer
(
unsigned
(
s_in_8b_reg
(
7
downto
5
)));
s_val4bit
<=
c_enc_3b_4b_table
(
s_ind3b
);
s_dP4bit
<=
c_disPar_4b
(
s_ind3b
);
s_val4bit_n
<=
not
(
s_val4bit
);
-- use 5bit at 4-0 as index for 6bit code and disparity table
s_ind5b
<=
to_integer
(
unsigned
(
s_in_8b_reg
(
4
downto
0
)));
s_val6bit
<=
c_enc_5b_6b_table
(
s_ind5b
);
s_dP6bit
<=
c_disPar_6b
(
s_ind5b
);
s_val6bit_n
<=
not
(
s_val6bit
);
signal
s_RunDisp
:
std_logic
;
-- running disparity register
signal
s_RunDisp_reg
:
std_logic
;
-- running disparity register
-- output wires
err_o
<=
s_err_reg
;
out_10b_o
<=
s_out_10b_reg
;
s_RunDisp
<=
s_RunDisp_reg
when
g_USE_INTERNAL_RUNNING_DISPARITY
else
dispar_i
;
dispar_o
<=
s_RunDisp_comb
;
--=============================================================================
-- CONCURRENT COMMANDS
--=============================================================================
-- use 3bit at 7-5 as index for 4bit code and disparity table \n
s_ind3b
<=
to_integer
(
unsigned
(
s_in_8b_reg
(
7
downto
5
)));
s_val4bit
<=
c_ENC_3B_4B_TABLE
(
s_ind3b
);
s_dP4bit
<=
c_DISPAR_4B
(
s_ind3b
);
s_val4bit_n
<=
not
(
s_val4bit
);
-- use 5bit at 4-0 as index for 6bit code and disparity table
s_ind5b
<=
to_integer
(
unsigned
(
s_in_8b_reg
(
4
downto
0
)));
s_val6bit
<=
c_ENC_5B_6B_TABLE
(
s_ind5b
);
s_dP6bit
<=
c_DISPAR_6B
(
s_ind5b
);
s_val6bit_n
<=
not
(
s_val6bit
);
-- output wires
err_o
<=
s_err_reg
;
out_10b_o
<=
s_out_10b_reg
;
--=============================================================================
-- ENCODING
--=============================================================================
-- Process encodes 8bit value to 10bit codeword depending on current disparity
p_encoding
:
process
(
s_RunDisp
,
s_ctrl_reg
,
s_dP4bit
,
s_dP6bit
,
s_in_8b_reg
,
s_val4bit
,
s_val4bit_n
,
s_val6bit
,
s_val6bit_n
)
-- buffers ctrl code during selection
variable
v_ctrl_code
:
std_logic_vector
(
9
downto
0
)
:
=
(
others
=>
'0'
);
begin
v_ctrl_code
:
=
(
others
=>
'0'
);
s_err
<=
'0'
;
--========================================================================
-- TRANSMISSION CONTROL CODES
--========================================================================
if
s_ctrl_reg
=
'1'
then
-- Control Char selected
-- control byte directly selects control code
case
s_in_8b_reg
is
when
"00011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110100"
);
when
"00111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011111001"
);
when
"01011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110101"
);
when
"01111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110011"
);
when
"10011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110010"
);
when
"10111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011111010"
);
when
"11011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110110"
);
when
"11111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011111000"
);
when
"11110111"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"1110101000"
);
when
"11111011"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"1101101000"
);
when
"11111101"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"1011101000"
);
when
"11111110"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0111101000"
);
when
others
=>
s_err
<=
'1'
;
end
case
;
-- select the right disparity and assign to output
if
(
s_RunDisp
=
c_RD_MINUS
)
then
s_out_10b
<=
v_ctrl_code
;
else
s_out_10b
<=
not
(
v_ctrl_code
);
end
if
;
else
--====================================================================
-- DATA CODES
--====================================================================
s_out_10b
<=
f_reverse_vector
(
s_val6bit
&
s_val4bit
);
if
s_RunDisp
=
c_RD_MINUS
then
if
s_dP4bit
=
s_dP6bit
then
if
s_dP6bit
=
'1'
then
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
else
if
s_dP4bit
=
'1'
then
if
((
s_val6bit
(
2
downto
0
)
=
"011"
)
and
(
s_val4bit
(
3
downto
1
)
=
"111"
))
then
s_out_10b
(
9
downto
6
)
<=
"1110"
;
end
if
;
else
if
(
s_val4bit
=
"1100"
)
then
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
end
if
;
end
if
;
else
if
s_dP6bit
=
'1'
then
s_out_10b
(
5
downto
0
)
<=
f_reverse_vector
(
s_val6bit_n
);
else
if
(
s_val6bit
=
"111000"
)
then
s_out_10b
(
5
downto
0
)
<=
f_reverse_vector
(
s_val6bit_n
);
end
if
;
if
s_dP4bit
=
'1'
then
if
((
s_val6bit
(
2
downto
0
)
=
"100"
)
and
(
s_val4bit
(
3
downto
1
)
=
"111"
))
then
s_out_10b
(
9
downto
6
)
<=
"0001"
;
else
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
else
if
(
s_val4bit
=
"1100"
)
then
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
end
if
;
end
if
;
end
if
;
end
process
p_encoding
;
p_disp_fsm_next
:
process
(
s_RunDisp
,
s_ctrl_reg
,
s_dP4bit
,
s_dP6bit
,
s_in_8b_reg
)
begin
s_RunDisp_comb
<=
s_RunDisp
;
if
s_RunDisp
=
c_RD_MINUS
then
if
(
s_ctrl_reg
xor
s_dP6bit
xor
s_dP4bit
)
/=
'0'
then
s_RunDisp_comb
<=
c_RD_PLUS
;
end
if
;
else
-- RD_PLUS
if
(
s_ctrl_reg
xor
s_dP6bit
xor
s_dP4bit
)
/=
'0'
then
s_RunDisp_comb
<=
c_RD_MINUS
;
end
if
;
--=============================================================================
-- ENCODING
--=============================================================================
if
(
s_in_8b_reg
(
1
downto
0
)
/=
"00"
and
s_ctrl_reg
=
'1'
)
then
--=============================================================================
-- Begin of p_encoding
--! Process encodes 8bit value to 10bit codeword depending on current disparity
--=============================================================================
--! read: clk_i, reset_i, all signals
--! write: err_o,dispar_o,out_10b_o, s_dpTrack
p_encoding
:
PROCESS
(
s_RunDisp
,
s_in_8b_reg
,
s_dP4bit
,
s_dP6bit
,
s_val4bit
,
s_val4bit_n
,
s_val6bit
,
s_val6bit_n
,
s_ctrl_reg
)
--! buffers ctrl code during selection
variable
v_ctrl_code
:
std_logic_vector
(
9
downto
0
)
:
=
(
others
=>
'0'
);
begin
v_ctrl_code
:
=
(
others
=>
'0'
);
s_err
<=
'0'
;
--========================================================================
-- TRANSMISSION CONTROL CODES
--========================================================================
if
s_ctrl_reg
=
'1'
then
-- Control Char selected
--! control byte directly selects control code
case
s_in_8b_reg
is
when
"00011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110100"
);
when
"00111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011111001"
);
when
"01011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110101"
);
when
"01111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110011"
);
when
"10011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110010"
);
when
"10111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011111010"
);
when
"11011100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011110110"
);
when
"11111100"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0011111000"
);
when
"11110111"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"1110101000"
);
when
"11111011"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"1101101000"
);
when
"11111101"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"1011101000"
);
when
"11111110"
=>
v_ctrl_code
:
=
f_reverse_vector
(
"0111101000"
);
when
others
=>
s_err
<=
'1'
;
end
case
;
--! select the right disparity and assign to output
if
(
s_RunDisp
=
c_RD_MINUS
)
then
s_out_10b
<=
v_ctrl_code
;
else
s_out_10b
<=
not
(
v_ctrl_code
);
end
if
;
else
--====================================================================
-- DATA CODES
--====================================================================
--s_out_10b(5 downto 0) <= f_reverse_vector(s_val6bit);
--s_out_10b(9 downto 6) <= f_reverse_vector(s_val4bit);
s_out_10b
<=
f_reverse_vector
(
s_val6bit
&
s_val4bit
);
if
s_RunDisp
=
c_RD_MINUS
then
if
s_dP4bit
=
s_dP6bit
then
if
s_dP6bit
=
'1'
then
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
else
if
s_dP4bit
=
'1'
then
if
(
(
s_val6bit
(
2
downto
0
)
=
"011"
)
and
(
s_val4bit
(
3
downto
1
)
=
"111"
)
)
then
s_out_10b
(
9
downto
6
)
<=
"1110"
;
end
if
;
else
if
(
s_val4bit
=
"1100"
)
then
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
end
if
;
end
if
;
else
if
s_dP6bit
=
'1'
then
s_out_10b
(
5
downto
0
)
<=
f_reverse_vector
(
s_val6bit_n
);
else
if
(
s_val6bit
=
"111000"
)
then
s_out_10b
(
5
downto
0
)
<=
f_reverse_vector
(
s_val6bit_n
);
end
if
;
if
s_dP4bit
=
'1'
then
if
(
(
s_val6bit
(
2
downto
0
)
=
"100"
)
and
(
s_val4bit
(
3
downto
1
)
=
"111"
)
)
then
s_out_10b
(
9
downto
6
)
<=
"0001"
;
else
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
else
if
(
s_val4bit
=
"1100"
)
then
s_out_10b
(
9
downto
6
)
<=
f_reverse_vector
(
s_val4bit_n
);
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
p_disp_fsm_next
;
p_disp_fsm_seq
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
s_RunDisp_reg
<=
c_RD_MINUS
;
else
s_RunDisp_reg
<=
s_RunDisp_comb
;
end
PROCESS
p_encoding
;
disp_FSM_next
:
process
(
s_RunDisp
,
s_in_8b_reg
,
s_ctrl_reg
,
s_dP6bit
,
s_dP4bit
,
s_in_8b_reg
)
begin
s_RunDisp_comb
<=
s_RunDisp
;
if
s_RunDisp
=
c_RD_MINUS
then
if
(
s_ctrl_reg
xor
s_dP6bit
xor
s_dP4bit
)
/=
'0'
then
s_RunDisp_comb
<=
c_RD_PLUS
;
end
if
;
end
if
;
end
process
p_disp_fsm_seq
;
s_ctrl_reg
<=
ctrl_i
;
s_in_8b_reg
<=
in_8b_i
;
p_inout_buffers
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
s_err_reg
<=
'0'
;
s_out_10b_reg
<=
B"0000_000000"
;
else
s_err_reg
<=
s_err
;
s_out_10b_reg
<=
s_out_10b
;
else
-- RD_PLUS
if
(
s_ctrl_reg
xor
s_dP6bit
xor
s_dP4bit
)
/=
'0'
then
s_RunDisp_comb
<=
c_RD_MINUS
;
end
if
;
end
if
;
end
if
;
if
(
s_in_8b_reg
(
1
downto
0
)
/=
"00"
and
s_ctrl_reg
=
'1'
)
then
s_RunDisp_comb
<=
s_RunDisp
;
end
if
;
end
process
;
disp_fsm_seq
:
process
(
clk_i
,
rst_n_i
)
begin
if
rising_edge
(
clk_i
)
then
--======================================================================
-- SYNC RESET
--======================================================================
--! reset encoder
if
(
rst_n_i
=
'0'
)
then
s_RunDisp_reg
<=
c_RD_MINUS
;
else
s_RunDisp_reg
<=
s_RunDisp_comb
;
end
if
;
end
if
;
end
process
;
s_ctrl_reg
<=
ctrl_i
;
s_in_8b_reg
<=
in_8b_i
;
inout_buffers
:
process
(
clk_i
,
rst_n_i
)
begin
if
rising_edge
(
clk_i
)
then
--======================================================================
-- SYNC RESET
--======================================================================
--! reset encoder
if
(
rst_n_i
=
'0'
)
then
-- s_ctrl_reg <= '0';
-- s_in_8b_reg <= B"000_00000";
s_err_reg
<=
'0'
;
s_out_10b_reg
<=
B"0000_000000"
;
else
s_err_reg
<=
s_err
;
s_out_10b_reg
<=
s_out_10b
;
end
if
;
end
if
;
end
process
;
end
rtl
;
modules/common/gc_fsm_watchdog.vhd
View file @
8649d40d
...
...
@@ -38,7 +38,7 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gen
ram
_pkg
.
all
;
use
work
.
gen
cores
_pkg
.
all
;
entity
gc_fsm_watchdog
is
generic
...
...
@@ -66,7 +66,7 @@ architecture behav of gc_fsm_watchdog is
--============================================================================
-- Signal declarations
--============================================================================
signal
wdt
:
unsigned
(
f_log2_
size
(
g_wdt_max
)
-1
downto
0
);
signal
wdt
:
unsigned
(
f_log2_
ceil
(
g_wdt_max
)
-1
downto
0
);
--==============================================================================
-- architecture begin
...
...
modules/common/gc_moving_average.vhd
View file @
8649d40d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2009-09-01
-- Last update: 20
17-10-11
-- Last update: 20
20-04-07
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
...
...
@@ -46,7 +46,6 @@ use ieee.NUMERIC_STD.all;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
genram_pkg
.
all
;
entity
gc_moving_average
is
...
...
modules/common/gc_simple_spi_master.vhd
View file @
8649d40d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 20
13-01-2
5
-- Last update: 20
20-05-0
5
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -129,6 +129,7 @@ begin -- rtl
-- Waits for start of transfer command
when
IDLE
=>
sclk
<=
'0'
;
spi_mosi_o
<=
'0'
;
counter
<=
(
others
=>
'0'
);
if
(
start_i
=
'1'
)
then
sreg
<=
data_i
;
...
...
modules/common/gc_word_packer.vhd
View file @
8649d40d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2012-09-13
-- Last update: 20
12-09-13
-- Last update: 20
20-09-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -39,7 +39,7 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gen
ram
_pkg
.
all
;
use
work
.
gen
cores
_pkg
.
all
;
entity
gc_word_packer
is
...
...
@@ -101,7 +101,7 @@ architecture rtl of gc_word_packer is
constant
c_sreg_entries
:
integer
:
=
c_sreg_size
/
f_min
(
g_input_width
,
g_output_width
);
signal
sreg
:
std_logic_vector
(
c_sreg_size
-1
downto
0
);
signal
count
:
unsigned
(
f_log2_
size
(
c_sreg_entries
+
1
)
-
1
downto
0
);
signal
count
:
unsigned
(
f_log2_
ceil
(
c_sreg_entries
+
1
)
-
1
downto
0
);
signal
empty
:
std_logic
;
signal
q_valid_comb
,
q_valid_reg
,
q_req_d0
:
std_logic
;
...
...
modules/genrams/common/inferred_sync_fifo.vhd
View file @
8649d40d
...
...
@@ -91,7 +91,7 @@ architecture syn of inferred_sync_fifo is
begin
-- syn
legacy_mode_check
:
assert
g_show_ahead
=
false
or
g_show_ahead_legacy_mode
=
false
report
legacy_mode_check
'instance_name
&
"
: show-ahead enabled for sync FIFO in "
&
report
"inferred_sync_fifo
: show-ahead enabled for sync FIFO in "
&
"legacy mode. In this mode, the full flag is asserted at g_SIZE-1. if you want the "
&
"full flag to be asserted at g_SIZE, then disable g_SHOW_AHEAD_LEGACY_MODE."
severity
NOTE
;
...
...
modules/wishbone/Manifest.py
View file @
8649d40d
...
...
@@ -27,6 +27,7 @@ modules = { "local" : [
"wb_split"
,
"wb16_to_wb32"
,
"wb_indirect"
,
"wb_fine_pulse_gen"
,
"wbgen2"
,
"wbgenplus"
,
"wb_xc7_fw_update"
,
...
...
modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
View file @
8649d40d
...
...
@@ -38,7 +38,7 @@ entity wb_axi4lite_bridge is
AWVALID
:
in
std_logic
;
BREADY
:
in
std_logic
;
RREADY
:
in
std_logic
;
WLAST
:
in
std_logic
;
WLAST
:
in
std_logic
:
=
'1'
;
WVALID
:
in
std_logic
;
ARADDR
:
in
std_logic_vector
(
31
downto
0
);
AWADDR
:
in
std_logic_vector
(
31
downto
0
);
...
...
modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
View file @
8649d40d
...
...
@@ -54,7 +54,7 @@ architecture rtl of xwb_axi4lite_bridge is
signal
state
:
t_state
;
signal
count
:
unsigned
(
10
downto
0
);
begin
process
(
clk_sys_i
)
...
...
@@ -77,8 +77,8 @@ begin
axi4_slave_o
.
RRESP
<=
(
others
=>
'X'
);
axi4_slave_o
.
RVALID
<=
'0'
;
axi4_slave_o
.
RLAST
<=
'0'
;
if
(
axi4_slave_i
.
AWVALID
=
'1'
)
then
if
(
axi4_slave_i
.
AWVALID
=
'1'
)
then
state
<=
ISSUE_WRITE
;
wb_master_o
.
adr
<=
axi4_slave_i
.
AWADDR
;
elsif
(
axi4_slave_i
.
ARVALID
=
'1'
)
then
...
...
@@ -87,12 +87,10 @@ begin
end
if
;
when
ISSUE_WRITE
=>
axi4_slave_o
.
WREADY
<=
'1'
;
wb_master_o
.
cyc
<=
'1'
;
wb_master_o
.
we
<=
'1'
;
if
(
axi4_slave_i
.
WVALID
=
'1'
)
then
axi4_slave_o
.
WREADY
<=
'1'
;
if
(
axi4_slave_i
.
WVALID
=
'1'
)
then
wb_master_o
.
stb
<=
'1'
;
wb_master_o
.
sel
<=
axi4_slave_i
.
WSTRB
;
wb_master_o
.
dat
<=
axi4_slave_i
.
WDATA
;
...
...
@@ -100,7 +98,6 @@ begin
end
if
;
when
ISSUE_READ
=>
wb_master_o
.
cyc
<=
'1'
;
wb_master_o
.
stb
<=
'1'
;
wb_master_o
.
we
<=
'0'
;
...
...
@@ -109,11 +106,11 @@ begin
state
<=
COMPLETE_READ
;
when
COMPLETE_READ
=>
if
(
wb_master_i
.
stall
=
'0'
)
then
if
(
wb_master_i
.
stall
=
'0'
)
then
wb_master_o
.
stb
<=
'0'
;
if
(
wb_master_i
.
ack
=
'1'
)
then
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
IDLE
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_
EX
OKAY
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_OKAY
;
axi4_slave_o
.
RDATA
<=
wb_master_i
.
dat
;
axi4_slave_o
.
RVALID
<=
'1'
;
axi4_slave_o
.
RLAST
<=
'1'
;
...
...
@@ -124,13 +121,13 @@ begin
end
if
;
end
if
;
when
COMPLETE_WRITE
=>
if
(
wb_master_i
.
stall
=
'0'
)
then
if
(
wb_master_i
.
stall
=
'0'
)
then
wb_master_o
.
stb
<=
'0'
;
if
(
wb_master_i
.
ack
=
'1'
)
then
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
RESPONSE_WRITE
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_EXOKAY
;
axi4_slave_o
.
BVALID
<=
'1'
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_OKAY
;
wb_master_o
.
cyc
<=
'0'
;
else
state
<=
WAIT_ACK_WRITE
;
...
...
@@ -138,29 +135,30 @@ begin
end
if
;
end
if
;
when
WAIT_ACK_WRITE
=>
if
(
wb_master_i
.
ack
=
'1'
)
then
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
RESPONSE_WRITE
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_EXOKAY
;
axi4_slave_o
.
BVALID
<=
'1'
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_OKAY
;
wb_master_o
.
cyc
<=
'0'
;
elsif
count
=
c_timeout
then
state
<=
RESPONSE_WRITE
;
axi4_slave_o
.
BVALID
<=
'1'
;
axi4_slave_o
.
BRESP
<=
c_AXI4_RESP_SLVERR
;
wb_master_o
.
cyc
<=
'0'
;
end
if
;
count
<=
count
+
1
;
when
WAIT_ACK_READ
=>
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
IDLE
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_
EX
OKAY
;
if
(
wb_master_i
.
ack
=
'1'
)
then
state
<=
RESPONSE_READ
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_OKAY
;
axi4_slave_o
.
RVALID
<=
'1'
;
axi4_slave_o
.
RLAST
<=
'1'
;
axi4_slave_o
.
RDATA
<=
wb_master_i
.
dat
;
wb_master_o
.
cyc
<=
'0'
;
elsif
count
=
c_timeout
then
state
<=
IDLE
;
state
<=
RESPONSE_READ
;
axi4_slave_o
.
RRESP
<=
c_AXI4_RESP_SLVERR
;
axi4_slave_o
.
RVALID
<=
'1'
;
axi4_slave_o
.
RLAST
<=
'1'
;
...
...
@@ -169,23 +167,19 @@ begin
end
if
;
count
<=
count
+
1
;
when
RESPONSE_WRITE
=>
if
(
axi4_slave_i
.
BREADY
=
'1'
)
then
axi4_slave_o
.
BVALID
<=
'
1
'
;
axi4_slave_o
.
BVALID
<=
'
0
'
;
state
<=
IDLE
;
end
if
;
when
RESPONSE_READ
=>
null
;
when
RESPONSE_READ
=>
if
(
axi4_slave_i
.
RREADY
=
'1'
)
then
axi4_slave_o
.
RVALID
<=
'0'
;
state
<=
IDLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
end
rtl
;
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
View file @
8649d40d
...
...
@@ -19,8 +19,12 @@ memory-map:
children:
- field:
name: data
description: temperature
description: temperature
value
range: 15-0
- field:
name: error
description: temperature is not valid
range: 31
- reg:
name: status
description: status
...
...
@@ -35,3 +39,7 @@ memory-map:
name: id_ok
description: Set when unique id was read, persist after reset
range: 1
- field:
name: temp_ok
description: Set when the temperature register is correctly read
range: 2
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd
View file @
8649d40d
-- Do not edit. Generated on Wed Sep 30 11:24:49 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl wb_ds182x_regs.vhd -i wb_ds182x_regs.cheby
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
@@ -14,49 +19,64 @@ entity wb_ds182x_regs is
id_i
:
in
std_logic_vector
(
63
downto
0
);
-- temperature
-- temperature value
temperature_data_i
:
in
std_logic_vector
(
15
downto
0
);
-- temperature is not valid
temperature_error_i
:
in
std_logic
;
-- status
-- Set when unique id was read
status_id_read_i
:
in
std_logic
;
-- Set when unique id was read, persist after reset
status_id_ok_i
:
in
std_logic
status_id_ok_i
:
in
std_logic
;
-- Set when the temperature register is correctly read
status_temp_ok_i
:
in
std_logic
);
end
wb_ds182x_regs
;
architecture
syn
of
wb_ds182x_regs
is
signal
rd_int
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
adr_int
:
std_logic_vector
(
3
downto
2
);
signal
rd_req_int
:
std_logic
;
signal
wr_req_int
:
std_logic
;
signal
rd_ack_int
:
std_logic
;
signal
wr_ack_int
:
std_logic
;
signal
wb_en
:
std_logic
;
signal
ack_int
:
std_logic
;
signal
wb_rip
:
std_logic
;
signal
wb_wip
:
std_logic
;
signal
reg_rdat_int
:
std_logic_vector
(
31
downto
0
);
signal
rd_ack1_int
:
std_logic
;
signal
rd_ack_d0
:
std_logic
;
signal
rd_dat_d0
:
std_logic_vector
(
31
downto
0
);
signal
wr_req_d0
:
std_logic
;
signal
wr_adr_d0
:
std_logic_vector
(
3
downto
2
);
signal
wr_dat_d0
:
std_logic_vector
(
31
downto
0
);
signal
wr_sel_d0
:
std_logic_vector
(
3
downto
0
);
begin
-- WB decode signals
adr_int
<=
wb_i
.
adr
(
3
downto
2
);
wb_en
<=
wb_i
.
cyc
and
wb_i
.
stb
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
wb_rip
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
wb_rip
<=
(
wb_rip
or
(
wb_en
and
not
wb_i
.
we
))
and
not
rd_ack_int
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_rip
<=
'0'
;
else
wb_rip
<=
(
wb_rip
or
(
wb_en
and
not
wb_i
.
we
))
and
not
rd_ack_int
;
end
if
;
end
if
;
end
process
;
rd_int
<=
(
wb_en
and
not
wb_i
.
we
)
and
not
wb_rip
;
rd_
req_
int
<=
(
wb_en
and
not
wb_i
.
we
)
and
not
wb_rip
;
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
wb_wip
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
wb_wip
<=
(
wb_wip
or
(
wb_en
and
wb_i
.
we
))
and
not
wr_ack_int
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_wip
<=
'0'
;
else
wb_wip
<=
(
wb_wip
or
(
wb_en
and
wb_i
.
we
))
and
not
wr_ack_int
;
end
if
;
end
if
;
end
process
;
wr_int
<=
(
wb_en
and
wb_i
.
we
)
and
not
wb_wip
;
wr_
req_
int
<=
(
wb_en
and
wb_i
.
we
)
and
not
wb_wip
;
ack_int
<=
rd_ack_int
or
wr_ack_int
;
wb_o
.
ack
<=
ack_int
;
...
...
@@ -64,113 +84,97 @@ begin
wb_o
.
rty
<=
'0'
;
wb_o
.
err
<=
'0'
;
-- Assign outputs
-- pipelining for wr-in+rd-out
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
rd_ack_int
<=
'0'
;
wr_req_d0
<=
'0'
;
else
rd_ack_int
<=
rd_ack_d0
;
wb_o
.
dat
<=
rd_dat_d0
;
wr_req_d0
<=
wr_req_int
;
wr_adr_d0
<=
adr_int
;
wr_dat_d0
<=
wb_i
.
dat
;
wr_sel_d0
<=
wb_i
.
sel
;
end
if
;
end
if
;
end
process
;
-- Register id
-- Register temperature
-- Register status
-- Process for write requests.
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
wr_ack_int
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
wr_ack_int
<=
'0'
;
case
wb_i
.
adr
(
3
downto
3
)
is
when
"0"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- Register id
when
"1"
=>
-- Register id
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
when
"1"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- Register temperature
when
"1"
=>
-- Register status
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
process
(
wr_adr_d0
,
wr_req_d0
)
begin
case
wr_adr_d0
(
3
downto
3
)
is
when
"0"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg id
wr_ack_int
<=
wr_req_d0
;
when
"1"
=>
-- Reg id
wr_ack_int
<=
wr_req_d0
;
when
others
=>
wr_ack_int
<=
wr_
int
;
wr_ack_int
<=
wr_
req_d0
;
end
case
;
end
if
;
end
process
;
-- Process for registers read.
process
(
clk_i
,
rst_n_i
)
begin
if
rst_n_i
=
'0'
then
rd_ack1_int
<=
'0'
;
reg_rdat_int
<=
(
others
=>
'X'
);
elsif
rising_edge
(
clk_i
)
then
reg_rdat_int
<=
(
others
=>
'0'
);
case
wb_i
.
adr
(
3
downto
3
)
is
when
"0"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- id
reg_rdat_int
<=
id_i
(
63
downto
32
);
rd_ack1_int
<=
rd_int
;
when
"1"
=>
-- id
reg_rdat_int
<=
id_i
(
31
downto
0
);
rd_ack1_int
<=
rd_int
;
when
others
=>
rd_ack1_int
<=
rd_int
;
end
case
;
when
"1"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- temperature
reg_rdat_int
(
15
downto
0
)
<=
temperature_data_i
;
rd_ack1_int
<=
rd_int
;
when
"1"
=>
-- status
reg_rdat_int
(
0
)
<=
status_id_read_i
;
reg_rdat_int
(
1
)
<=
status_id_ok_i
;
rd_ack1_int
<=
rd_int
;
when
others
=>
rd_ack1_int
<=
rd_int
;
end
case
;
when
"1"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg temperature
wr_ack_int
<=
wr_req_d0
;
when
"1"
=>
-- Reg status
wr_ack_int
<=
wr_req_d0
;
when
others
=>
rd_ack1_int
<=
rd_int
;
wr_ack_int
<=
wr_req_d0
;
end
case
;
end
if
;
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
end
process
;
-- Process for read requests.
process
(
wb_i
.
adr
,
reg_rdat_int
,
rd_ack1_int
,
rd_int
)
begin
process
(
adr_int
,
rd_req_int
,
id_i
,
temperature_data_i
,
temperature_error_i
,
status_id_read_i
,
status_id_ok_i
,
status_temp_ok_i
)
begin
-- By default ack read requests
wb_o
.
dat
<=
(
others
=>
'0
'
);
case
wb_i
.
adr
(
3
downto
3
)
is
when
"0"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- id
wb_o
.
dat
<=
reg_rdat
_int
;
rd_
ack_int
<=
rd_ack1_int
;
when
"1"
=>
-- id
wb_o
.
dat
<=
reg_rdat
_int
;
rd_
ack_int
<=
rd_ack1_int
;
rd_dat_d0
<=
(
others
=>
'X
'
);
case
adr_int
(
3
downto
3
)
is
when
"0"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
--
Reg
id
rd_ack_d0
<=
rd_req
_int
;
rd_
dat_d0
<=
id_i
(
63
downto
32
)
;
when
"1"
=>
--
Reg
id
rd_ack_d0
<=
rd_req
_int
;
rd_
dat_d0
<=
id_i
(
31
downto
0
)
;
when
others
=>
rd_ack_
int
<=
rd
_int
;
rd_ack_
d0
<=
rd_req
_int
;
end
case
;
when
"1"
=>
case
wb_i
.
adr
(
2
downto
2
)
is
when
"0"
=>
-- temperature
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1"
=>
-- status
wb_o
.
dat
<=
reg_rdat_int
;
rd_ack_int
<=
rd_ack1_int
;
when
"1"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg temperature
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
15
downto
0
)
<=
temperature_data_i
;
rd_dat_d0
(
30
downto
16
)
<=
(
others
=>
'0'
);
rd_dat_d0
(
31
)
<=
temperature_error_i
;
when
"1"
=>
-- Reg status
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
0
)
<=
status_id_read_i
;
rd_dat_d0
(
1
)
<=
status_id_ok_i
;
rd_dat_d0
(
2
)
<=
status_temp_ok_i
;
rd_dat_d0
(
31
downto
3
)
<=
(
others
=>
'0'
);
when
others
=>
rd_ack_
int
<=
rd
_int
;
rd_ack_
d0
<=
rd_req
_int
;
end
case
;
when
others
=>
rd_ack_
int
<=
rd
_int
;
rd_ack_
d0
<=
rd_req
_int
;
end
case
;
end
process
;
end
syn
;
modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd
View file @
8649d40d
...
...
@@ -48,6 +48,8 @@ architecture arch of xwb_ds182x_readout is
signal
temper
:
std_logic_vector
(
15
downto
0
);
-- temperature value (refreshed every second)
signal
id_read
:
std_logic
;
-- id_o value is valid_o
signal
id_ok
:
std_logic
;
-- Same as id_read_o, but not reset with rst_n_i
signal
temp_ok
:
std_logic
;
signal
temp_err
:
std_logic
;
begin
i_readout
:
entity
work
.
gc_ds182x_readout
generic
map
(
...
...
@@ -60,19 +62,24 @@ begin
onewire_b
=>
onewire_b
,
id_o
=>
id
,
temper_o
=>
temper
,
temp_ok_o
=>
temp_ok
,
id_read_o
=>
id_read
,
id_ok_o
=>
id_ok
);
temp_err
<=
not
temp_ok
;
i_regs
:
entity
work
.
wb_ds182x_regs
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_i
,
wb_i
=>
wb_i
,
wb_o
=>
wb_o
,
id_i
=>
id
,
temperature_data_i
=>
temper
,
temperature_error_i
=>
temp_err
,
status_id_read_i
=>
id_read
,
status_id_ok_i
=>
id_ok
status_id_ok_i
=>
id_ok
,
status_temp_ok_i
=>
temp_ok
);
end
arch
;
modules/wishbone/wb_fine_pulse_gen/Manifest.py
0 → 100644
View file @
8649d40d
files
=
[
"fine_pulse_gen_kintex7_shared.vhd"
,
"fine_pulse_gen_kintexultrascale_shared.vhd"
,
"fine_pulse_gen_kintex7.vhd"
,
"fine_pulse_gen_kintexultrascale.vhd"
,
"fine_pulse_gen_wbgen2_pkg.vhd"
,
"fine_pulse_gen_wb.vhd"
,
"xwb_fine_pulse_gen.vhd"
]
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7.vhd
0 → 100644
View file @
8649d40d
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
library
unisim
;
use
unisim
.
VCOMPONENTS
.
all
;
entity
fine_pulse_gen_kintex7
is
generic
(
g_sim_delay_tap_ps
:
integer
:
=
30
;
g_ref_clk_freq
:
real
:
=
125
.
0
;
g_use_odelay
:
boolean
:
=
false
);
port
(
clk_par_i
:
in
std_logic
;
clk_serdes_i
:
in
std_logic
;
rst_serdes_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
cont_i
:
in
std_logic
;
pol_i
:
in
std_logic
;
coarse_i
:
in
std_logic_vector
(
7
downto
0
);
trig_p_i
:
in
std_logic
;
pulse_o
:
out
std_logic
;
dly_load_i
:
in
std_logic
;
dly_fine_i
:
in
std_logic_vector
(
4
downto
0
)
);
end
fine_pulse_gen_kintex7
;
architecture
rtl
of
fine_pulse_gen_kintex7
is
signal
par_data
:
std_logic_vector
(
7
downto
0
);
signal
dout_predelay
,
dout_prebuf
,
dout_nodelay
:
std_logic
;
signal
odelay_load
:
std_logic
;
signal
rst
:
std_logic
;
signal
odelay_ntaps
:
std_logic_vector
(
4
downto
0
);
signal
trig_d
:
std_logic
;
-- function f_gen_bitmask (coarse : std_logic_vector; pol : std_logic; cont : std_logic) return std_logic_vector is
-- variable rv : std_logic_vector(15 downto 0);
-- begin
-- end f_gen_bitmask;
signal
mask
:
std_logic_vector
(
15
downto
0
);
signal
flip
:
std_logic
;
signal
dly_load_d
:
std_logic
;
begin
rst
<=
not
rst_sys_n_i
;
process
(
clk_par_i
)
variable
rv
:
std_logic_vector
(
15
downto
0
);
begin
if
rising_edge
(
clk_par_i
)
then
dly_load_d
<=
dly_load_i
;
if
dly_load_i
=
'1'
then
odelay_ntaps
<=
dly_fine_i
;
if
cont_i
=
'1'
then
case
coarse_i
is
when
x"00"
=>
rv
:
=
"1111000011110000"
;
when
x"01"
=>
rv
:
=
"0111100001111000"
;
when
x"02"
=>
rv
:
=
"0011110000111100"
;
when
x"03"
=>
rv
:
=
"0001111000011110"
;
when
x"04"
=>
rv
:
=
"0000111100001111"
;
when
x"05"
=>
rv
:
=
"1000011110000111"
;
when
x"06"
=>
rv
:
=
"1100001111000011"
;
when
x"07"
=>
rv
:
=
"1110000111100001"
;
when
others
=>
rv
:
=
(
others
=>
'0'
);
end
case
;
else
case
coarse_i
is
when
x"00"
=>
rv
:
=
"1111000000000000"
;
when
x"01"
=>
rv
:
=
"0111100000000000"
;
when
x"02"
=>
rv
:
=
"0011110000000000"
;
when
x"03"
=>
rv
:
=
"0001111000000000"
;
when
x"04"
=>
rv
:
=
"0000111100000000"
;
when
x"05"
=>
rv
:
=
"0000011110000000"
;
when
x"06"
=>
rv
:
=
"0000001111000000"
;
when
x"07"
=>
rv
:
=
"0000000111100000"
;
when
others
=>
rv
:
=
(
others
=>
'0'
);
end
case
;
end
if
;
if
pol_i
=
'0'
then
mask
<=
rv
;
else
mask
<=
not
rv
;
end
if
;
end
if
;
odelay_load
<=
dly_load_i
or
dly_load_d
;
trig_d
<=
trig_p_i
;
if
trig_p_i
=
'1'
then
par_data
<=
mask
(
15
downto
8
);
flip
<=
'0'
;
elsif
trig_d
=
'1'
then
par_data
<=
mask
(
7
downto
0
);
else
if
cont_i
=
'1'
then
if
flip
=
'1'
then
par_data
<=
mask
(
7
downto
0
);
else
par_data
<=
mask
(
15
downto
8
);
end
if
;
else
if
pol_i
=
'1'
then
par_data
<=
(
others
=>
'1'
);
else
par_data
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
U_Serdes
:
OSERDESE2
generic
map
(
DATA_RATE_OQ
=>
"SDR"
,
DATA_RATE_TQ
=>
"SDR"
,
DATA_WIDTH
=>
8
,
TRISTATE_WIDTH
=>
1
,
SERDES_MODE
=>
"MASTER"
)
port
map
(
D1
=>
par_data
(
7
),
D2
=>
par_data
(
6
),
D3
=>
par_data
(
5
),
D4
=>
par_data
(
4
),
D5
=>
par_data
(
3
),
D6
=>
par_data
(
2
),
D7
=>
par_data
(
1
),
D8
=>
par_data
(
0
),
T1
=>
'0'
,
T2
=>
'0'
,
T3
=>
'0'
,
T4
=>
'0'
,
SHIFTIN1
=>
'0'
,
SHIFTIN2
=>
'0'
,
OCE
=>
'1'
,
CLK
=>
clk_serdes_i
,
CLKDIV
=>
clk_par_i
,
OFB
=>
dout_predelay
,
OQ
=>
dout_nodelay
,
TBYTEIN
=>
'0'
,
TCE
=>
'0'
,
RST
=>
rst_serdes_i
);
gen_with_odelay
:
if
g_use_odelay
generate
U_Delay
:
ODELAYE2
generic
map
(
CINVCTRL_SEL
=>
"FALSE"
,
DELAY_SRC
=>
"ODATAIN"
,
HIGH_PERFORMANCE_MODE
=>
"TRUE"
,
ODELAY_TYPE
=>
"VAR_LOAD"
,
ODELAY_VALUE
=>
0
,
REFCLK_FREQUENCY
=>
g_ref_clk_freq
,
PIPE_SEL
=>
"FALSE"
,
SIGNAL_PATTERN
=>
"DATA"
)
port
map
(
DATAOUT
=>
dout_prebuf
,
CLKIN
=>
'0'
,
C
=>
clk_par_i
,
CE
=>
'0'
,
INC
=>
'0'
,
ODATAIN
=>
dout_predelay
,
LD
=>
odelay_load
,
REGRST
=>
rst_serdes_i
,
LDPIPEEN
=>
'0'
,
CNTVALUEIN
=>
odelay_ntaps
,
CINVCTRL
=>
'0'
);
end
generate
gen_with_odelay
;
gen_without_odelay
:
if
not
g_use_odelay
generate
dout_prebuf
<=
dout_nodelay
;
end
generate
gen_without_odelay
;
pulse_o
<=
dout_prebuf
;
-- gen_output_diff : if g_use_diff_output generate
-- U_OBuf : OBUFDS
-- generic map(
-- IOSTANDARD => "LVDS_25",
-- SLEW => "FAST")
-- port map(
-- O => pulse_p_o,
-- OB => pulse_n_o,
-- I => dout_prebuf);
-- end generate gen_output_diff;
end
rtl
;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7_shared.vhd
0 → 100644
View file @
8649d40d
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
unisim
;
use
unisim
.
VCOMPONENTS
.
all
;
entity
fine_pulse_gen_kintex7_shared
is
generic
(
g_global_use_odelay
:
boolean
;
g_use_external_serdes_clock
:
boolean
);
port
(
-- PLL async reset
pll_rst_i
:
in
std_logic
;
clk_ser_ext_i
:
in
std_logic
;
-- 62.5 MHz reference
clk_ref_i
:
in
std_logic
;
-- serdes parallel clock
clk_par_o
:
out
std_logic
;
-- serdes serial clock
clk_ser_o
:
out
std_logic
;
clk_odelay_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
);
end
fine_pulse_gen_kintex7_shared
;
architecture
rtl
of
fine_pulse_gen_kintex7_shared
is
signal
pll_locked
:
std_logic
;
signal
clk_fb_pll
,
clk_fb_pll_bufg
,
clk_iodelay
,
clk_iodelay_bufg
:
std_logic
;
begin
pll_iodelay_map
:
PLLE2_ADV
generic
map
(
BANDWIDTH
=>
(
"HIGH"
),
COMPENSATION
=>
(
"ZHOLD"
),
STARTUP_WAIT
=>
(
"FALSE"
),
DIVCLK_DIVIDE
=>
(
1
),
CLKFBOUT_MULT
=>
(
16
),
CLKFBOUT_PHASE
=>
(
0
.
000
),
CLKOUT0_DIVIDE
=>
(
5
),
-- 200 MHz
CLKOUT0_PHASE
=>
(
0
.
000
),
CLKOUT0_DUTY_CYCLE
=>
(
0
.
500
),
CLKOUT1_DIVIDE
=>
(
2
),
-- 500 MHz
CLKOUT1_PHASE
=>
(
0
.
000
),
CLKOUT1_DUTY_CYCLE
=>
(
0
.
500
),
CLKIN1_PERIOD
=>
(
16
.
000
))
port
map
(
CLKFBOUT
=>
clk_fb_pll
,
CLKOUT0
=>
clk_iodelay
,
CLKOUT1
=>
clk_ser_o
,
-- Input clock control
CLKFBIN
=>
clk_fb_pll_bufg
,
CLKIN1
=>
clk_ref_i
,
CLKIN2
=>
'0'
,
CLKINSEL
=>
'1'
,
DADDR
=>
(
others
=>
'0'
),
DCLK
=>
'0'
,
DEN
=>
'0'
,
DI
=>
(
others
=>
'0'
),
DWE
=>
'0'
,
PWRDWN
=>
'0'
,
RST
=>
pll_rst_i
,
LOCKED
=>
pll_locked_o
);
clk_par_o
<=
clk_ref_i
;
int_bufg
:
BUFG
port
map
(
O
=>
clk_fb_pll_bufg
,
I
=>
clk_fb_pll
);
gen_with_iodelay
:
if
g_global_use_odelay
generate
int_bufg_clkiodelay
:
BUFG
port
map
(
O
=>
clk_iodelay_bufg
,
I
=>
clk_iodelay
);
IDELAYCTRL_inst
:
IDELAYCTRL
port
map
(
RDY
=>
open
,
-- 1-bit output: Ready output
REFCLK
=>
clk_iodelay_bufg
,
-- 1-bit input: Reference clock input
RST
=>
'0'
-- 1-bit input: Active high reset input
);
clk_odelay_o
<=
clk_iodelay_bufg
;
end
generate
gen_with_iodelay
;
end
rtl
;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale.vhd
0 → 100644
View file @
8649d40d
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
library
unisim
;
use
unisim
.
VCOMPONENTS
.
all
;
entity
fine_pulse_gen_kintexultrascale
is
generic
(
g_sim_delay_tap_ps
:
integer
:
=
30
;
g_idelayctrl_ref_clk_freq
:
real
:
=
250
.
0
;
g_use_odelay
:
boolean
:
=
false
);
port
(
clk_sys_i
:
in
std_logic
;
-- system clock
clk_ref_i
:
in
std_logic
;
-- 62.5 MHz (WR)
clk_par_i
:
in
std_logic
;
-- 125 MHz
clk_serdes_i
:
in
std_logic
;
-- 500 MHz (DDR)
rst_serdes_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
cont_i
:
in
std_logic
;
pol_i
:
in
std_logic
;
coarse_i
:
in
std_logic_vector
(
7
downto
0
);
trig_p_i
:
in
std_logic
;
pulse_o
:
out
std_logic
;
dly_load_i
:
in
std_logic
;
dly_fine_i
:
in
std_logic_vector
(
8
downto
0
);
odelay_cal_latch_i
:
in
std_logic
;
odelay_value_out_o
:
out
std_logic_vector
(
8
downto
0
);
odelay_value_in_i
:
in
std_logic_vector
(
8
downto
0
);
odelay_en_vtc_i
:
in
std_logic
;
odelay_load_i
:
in
std_logic
;
odelay_rst_i
:
in
std_logic
);
end
fine_pulse_gen_kintexultrascale
;
architecture
rtl
of
fine_pulse_gen_kintexultrascale
is
constant
c_DELAY_VALUE
:
integer
:
=
1000
;
-- in ps
component
OSERDESE3
is
generic
(
DATA_WIDTH
:
integer
:
=
8
;
INIT
:
bit
:
=
'0'
;
IS_CLKDIV_INVERTED
:
bit
:
=
'0'
;
IS_CLK_INVERTED
:
bit
:
=
'0'
;
IS_RST_INVERTED
:
bit
:
=
'0'
;
ODDR_MODE
:
string
:
=
"FALSE"
;
OSERDES_D_BYPASS
:
string
:
=
"FALSE"
;
OSERDES_T_BYPASS
:
string
:
=
"FALSE"
;
SIM_DEVICE
:
string
:
=
"ULTRASCALE"
;
SIM_VERSION
:
real
:
=
2
.
0
);
port
(
OQ
:
out
std_ulogic
;
T_OUT
:
out
std_ulogic
;
CLK
:
in
std_ulogic
;
CLKDIV
:
in
std_ulogic
;
D
:
in
std_logic_vector
(
7
downto
0
);
RST
:
in
std_ulogic
;
T
:
in
std_ulogic
);
end
component
OSERDESE3
;
component
ODELAYE3
generic
(
CASCADE
:
string
:
=
"NONE"
;
DELAY_FORMAT
:
string
:
=
"TIME"
;
DELAY_TYPE
:
string
:
=
"FIXED"
;
DELAY_VALUE
:
integer
:
=
0
;
IS_CLK_INVERTED
:
bit
:
=
'0'
;
IS_RST_INVERTED
:
bit
:
=
'0'
;
REFCLK_FREQUENCY
:
real
:
=
300
.
0
;
SIM_DEVICE
:
string
:
=
"ULTRASCALE"
;
SIM_VERSION
:
real
:
=
2
.
0
;
UPDATE_MODE
:
string
:
=
"ASYNC"
);
port
(
CASC_OUT
:
out
std_ulogic
;
CNTVALUEOUT
:
out
std_logic_vector
(
8
downto
0
);
DATAOUT
:
out
std_ulogic
;
CASC_IN
:
in
std_ulogic
;
CASC_RETURN
:
in
std_ulogic
;
CE
:
in
std_ulogic
;
CLK
:
in
std_ulogic
;
CNTVALUEIN
:
in
std_logic_vector
(
8
downto
0
);
EN_VTC
:
in
std_ulogic
;
INC
:
in
std_ulogic
;
LOAD
:
in
std_ulogic
;
ODATAIN
:
in
std_ulogic
;
RST
:
in
std_ulogic
);
end
component
;
signal
par_data
:
std_logic_vector
(
15
downto
0
);
signal
par_data_125
:
std_logic_vector
(
7
downto
0
);
signal
par_data_rev
:
std_logic_vector
(
15
downto
0
);
signal
odelay_load
:
std_logic
;
signal
rst
:
std_logic
;
signal
pulse_predelay
:
std_logic
;
signal
trig_d
:
std_logic
;
-- function f_gen_bitmask (coarse : std_logic_vector; pol : std_logic; cont : std_logic) return std_logic_vector is
-- variable rv : std_logic_vector(15 downto 0);
-- begin
-- end f_gen_bitmask;
signal
mask
:
std_logic_vector
(
31
downto
0
);
signal
flip
:
std_logic
;
signal
dly_load_d
:
std_logic
;
signal
clk_ref_div2
:
std_logic
:
=
'0'
;
signal
clk_ref_div2_d0
,
clk_ref_div2_d1
,
gb_sync_p
:
std_logic
;
signal
odelay_value_out
,
odelay_value_in
,
odelay_value_in_pulse
:
std_logic_vector
(
8
downto
0
);
signal
odelay_load_clk_ref
,
odelay_load_pulse
:
std_logic
;
signal
odelay_load_clk_par
:
std_logic
;
attribute
mark_debug
:
string
;
attribute
mark_debug
of
odelay_en_vtc_i
:
signal
is
"true"
;
attribute
mark_debug
of
odelay_cal_latch_i
:
signal
is
"true"
;
attribute
mark_debug
of
odelay_value_out
:
signal
is
"true"
;
begin
rst
<=
not
rst_sys_n_i
;
process
(
clk_ref_i
)
variable
rv
:
std_logic_vector
(
31
downto
0
);
begin
if
rising_edge
(
clk_ref_i
)
then
dly_load_d
<=
dly_load_i
;
if
dly_load_i
=
'1'
then
if
cont_i
=
'1'
then
case
coarse_i
is
when
x"00"
=>
rv
:
=
"11111111000000001111111100000000"
;
when
x"01"
=>
rv
:
=
"01111111100000000111111110000000"
;
when
x"02"
=>
rv
:
=
"00111111110000000011111111000000"
;
when
x"03"
=>
rv
:
=
"00011111111000000001111111100000"
;
when
x"04"
=>
rv
:
=
"00001111111100000000111111110000"
;
when
x"05"
=>
rv
:
=
"00000111111110000000011111111000"
;
when
x"06"
=>
rv
:
=
"00000011111111000000001111111100"
;
when
x"07"
=>
rv
:
=
"00000001111111100000000111111110"
;
when
x"08"
=>
rv
:
=
"00000000111111110000000011111111"
;
when
x"09"
=>
rv
:
=
"00000000011111111000000001111111"
;
when
x"0a"
=>
rv
:
=
"00000000001111111100000000111111"
;
when
x"0b"
=>
rv
:
=
"00000000000111111110000000011111"
;
when
x"0c"
=>
rv
:
=
"00000000000011111111000000001111"
;
when
x"0d"
=>
rv
:
=
"00000000000001111111100000000111"
;
when
x"0e"
=>
rv
:
=
"00000000000000111111110000000011"
;
when
x"0f"
=>
rv
:
=
"00000000000000011111111000000001"
;
when
others
=>
rv
:
=
(
others
=>
'0'
);
end
case
;
else
case
coarse_i
is
when
x"00"
=>
rv
:
=
"11111111000000000000000000000000"
;
when
x"01"
=>
rv
:
=
"01111111100000000000000000000000"
;
when
x"02"
=>
rv
:
=
"00111111110000000000000000000000"
;
when
x"03"
=>
rv
:
=
"00011111111000000000000000000000"
;
when
x"04"
=>
rv
:
=
"00001111111100000000000000000000"
;
when
x"05"
=>
rv
:
=
"00000111111110000000000000000000"
;
when
x"06"
=>
rv
:
=
"00000011111111000000000000000000"
;
when
x"07"
=>
rv
:
=
"00000001111111100000000000000000"
;
when
x"08"
=>
rv
:
=
"00000000111111110000000000000000"
;
when
x"09"
=>
rv
:
=
"00000000011111111000000000000000"
;
when
x"0a"
=>
rv
:
=
"00000000001111111100000000000000"
;
when
x"0b"
=>
rv
:
=
"00000000000111111110000000000000"
;
when
x"0c"
=>
rv
:
=
"00000000000011111111000000000000"
;
when
x"0d"
=>
rv
:
=
"00000000000001111111100000000000"
;
when
x"0e"
=>
rv
:
=
"00000000000000111111110000000000"
;
when
x"0f"
=>
rv
:
=
"00000000000000011111111000000000"
;
when
others
=>
rv
:
=
(
others
=>
'0'
);
end
case
;
end
if
;
if
pol_i
=
'0'
then
mask
<=
rv
;
else
mask
<=
not
rv
;
end
if
;
end
if
;
odelay_load_pulse
<=
dly_load_i
or
dly_load_d
;
odelay_value_in_pulse
<=
dly_fine_i
;
trig_d
<=
trig_p_i
;
if
trig_p_i
=
'1'
then
par_data
<=
mask
(
31
downto
16
);
flip
<=
'0'
;
elsif
trig_d
=
'1'
then
par_data
<=
mask
(
15
downto
0
);
else
if
cont_i
=
'1'
then
if
flip
=
'1'
then
par_data
<=
mask
(
15
downto
0
);
else
par_data
<=
mask
(
31
downto
16
);
end
if
;
else
if
pol_i
=
'1'
then
par_data
<=
(
others
=>
'1'
);
else
par_data
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
p_div_clk
:
process
(
clk_ref_i
,
rst_serdes_i
)
begin
if
rst_serdes_i
=
'1'
then
clk_ref_div2
<=
'0'
;
elsif
rising_edge
(
clk_ref_i
)
then
clk_ref_div2
<=
not
clk_ref_div2
;
odelay_load_clk_ref
<=
odelay_load_pulse
or
odelay_load_i
;
if
odelay_load_pulse
=
'1'
then
odelay_value_in
<=
odelay_value_in_pulse
;
-- pulse gen FSM takes priority
elsif
odelay_load_i
=
'1'
then
-- ODELAY calibration FSM is 2nd in priority
odelay_value_in
<=
odelay_value_in_i
;
end
if
;
end
if
;
end
process
;
U_Sync_ODELAY_LOAD
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_ref_i
,
clk_out_i
=>
clk_par_i
,
rst_n_i
=>
rst_sys_n_i
,
d_ready_o
=>
open
,
d_p_i
=>
odelay_load_clk_ref
,
q_p_o
=>
odelay_load_clk_par
);
p_gearbox
:
process
(
clk_par_i
)
begin
if
rising_edge
(
clk_par_i
)
then
clk_ref_div2_d0
<=
clk_ref_div2
;
clk_ref_div2_d1
<=
clk_ref_div2_d0
;
gb_sync_p
<=
clk_ref_div2_d0
xor
clk_ref_div2_d1
;
if
gb_sync_p
=
'1'
then
par_data_125
<=
par_data
(
15
downto
8
);
else
par_data_125
<=
par_data
(
7
downto
0
);
end
if
;
end
if
;
end
process
;
U_Serdes
:
OSERDESE3
generic
map
(
DATA_WIDTH
=>
8
,
INIT
=>
'0'
,
IS_CLKDIV_INVERTED
=>
'0'
,
IS_CLK_INVERTED
=>
'0'
,
IS_RST_INVERTED
=>
'0'
,
ODDR_MODE
=>
"FALSE"
,
OSERDES_D_BYPASS
=>
"FALSE"
,
OSERDES_T_BYPASS
=>
"FALSE"
,
SIM_DEVICE
=>
"ULTRASCALE"
)
port
map
(
OQ
=>
pulse_predelay
,
CLK
=>
clk_serdes_i
,
CLKDIV
=>
clk_par_i
,
D
(
0
)
=>
par_data_125
(
7
),
D
(
1
)
=>
par_data_125
(
6
),
D
(
2
)
=>
par_data_125
(
5
),
D
(
3
)
=>
par_data_125
(
4
),
D
(
4
)
=>
par_data_125
(
3
),
D
(
5
)
=>
par_data_125
(
2
),
D
(
6
)
=>
par_data_125
(
1
),
D
(
7
)
=>
par_data_125
(
0
),
RST
=>
rst_serdes_i
,
T
=>
'0'
);
gen_with_odelay
:
if
g_use_odelay
generate
b_odelay
:
block
attribute
IODELAY_GROUP
:
string
;
attribute
IODELAY_GROUP
of
U_ODELAYE3_Fine_Pulse_Gen
:
label
is
"IODELAY_FPGen"
;
signal
odelay_rst_clk_par
:
std_logic
;
signal
odelay_en_vtc_clk_par
:
std_logic
;
begin
U_Sync_Reset
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_par_i
,
rst_n_i
=>
'1'
,
data_i
=>
odelay_rst_i
,
synced_o
=>
odelay_rst_clk_par
);
U_Sync_VTC
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_par_i
,
rst_n_i
=>
'1'
,
data_i
=>
odelay_en_vtc_i
,
synced_o
=>
odelay_en_vtc_clk_par
);
-- If a OSERDESE3 block (or its simplified version ODDRE) is instantiated,
-- the ODELAYE3 CLK and OSERDESE3 CLK_DIV (or ODDRE C) port must share the same clock
U_ODELAYE3_Fine_Pulse_Gen
:
ODELAYE3
generic
map
(
CASCADE
=>
"NONE"
,
-- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
DELAY_FORMAT
=>
"TIME"
,
-- (COUNT, TIME)
DELAY_TYPE
=>
"VAR_LOAD"
,
-- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
DELAY_VALUE
=>
c_DELAY_VALUE
,
-- Output delay tap setting
IS_CLK_INVERTED
=>
'0'
,
-- Optional inversion for CLK
IS_RST_INVERTED
=>
'0'
,
-- Optional inversion for RST
REFCLK_FREQUENCY
=>
g_idelayctrl_ref_clk_freq
,
-- IDELAYCTRL clock input frequency in MHz (200.0-2667.0).
SIM_DEVICE
=>
"ULTRASCALE"
,
-- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
UPDATE_MODE
=>
"ASYNC"
-- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
)
port
map
(
CASC_OUT
=>
open
,
-- 1-bit output: Cascade delay output to IDELAY input cascade
CNTVALUEOUT
=>
odelay_value_out
,
-- 9-bit output: Counter value output
DATAOUT
=>
pulse_o
,
-- 1-bit output: Delayed data from ODATAIN input port
CASC_IN
=>
'0'
,
-- 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT
CASC_RETURN
=>
'0'
,
-- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT
CE
=>
'0'
,
-- 1-bit input: Active high enable increment/decrement input
CLK
=>
clk_par_i
,
-- 1-bit input: Clock input
CNTVALUEIN
=>
odelay_value_in
,
-- 9-bit input: Counter value input
EN_VTC
=>
odelay_en_vtc_clk_par
,
-- 1-bit input: Keep delay constant over VT
INC
=>
'0'
,
-- 1-bit input: Increment/Decrement tap delay input
LOAD
=>
odelay_load_clk_par
,
-- 1-bit input: Load DELAY_VALUE input
ODATAIN
=>
pulse_predelay
,
-- 1-bit input: Data input
RST
=>
odelay_rst_clk_par
-- 1-bit input: Asynchronous Reset to the DELAY_VALUE
);
end
block
;
-- same delay applied to all pins
p_latch_delay
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
odelay_cal_latch_i
=
'1'
then
odelay_value_out_o
<=
odelay_value_out
;
end
if
;
end
if
;
end
process
;
end
generate
gen_with_odelay
;
gen_without_odelay
:
if
not
g_use_odelay
generate
pulse_o
<=
pulse_predelay
;
end
generate
gen_without_odelay
;
end
rtl
;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
0 → 100644
View file @
8649d40d
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
gencores_pkg
.
all
;
library
unisim
;
use
unisim
.
VCOMPONENTS
.
all
;
entity
fine_pulse_gen_kintexultrascale_shared
is
generic
(
g_global_use_odelay
:
boolean
;
g_use_external_serdes_clock
:
boolean
);
port
(
-- PLL async reset
pll_rst_i
:
in
std_logic
;
odelayctrl_rst_i
:
in
std_logic
;
clk_ser_ext_i
:
in
std_logic
;
-- 62.5 MHz reference
clk_ref_i
:
in
std_logic
;
-- serdes parallel clock
clk_par_o
:
out
std_logic
;
-- serdes serial clock
clk_ser_o
:
out
std_logic
;
clk_odelay_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
;
odelayctrl_rdy_o
:
out
std_logic
);
end
fine_pulse_gen_kintexultrascale_shared
;
architecture
rtl
of
fine_pulse_gen_kintexultrascale_shared
is
component
MMCME3_ADV
generic
(
BANDWIDTH
:
string
:
=
"OPTIMIZED"
;
CLKFBOUT_MULT_F
:
real
:
=
5
.
000
;
CLKFBOUT_PHASE
:
real
:
=
0
.
000
;
CLKFBOUT_USE_FINE_PS
:
string
:
=
"FALSE"
;
CLKIN1_PERIOD
:
real
:
=
0
.
000
;
CLKIN2_PERIOD
:
real
:
=
0
.
000
;
CLKOUT0_DIVIDE_F
:
real
:
=
1
.
000
;
CLKOUT0_DUTY_CYCLE
:
real
:
=
0
.
500
;
CLKOUT0_PHASE
:
real
:
=
0
.
000
;
CLKOUT0_USE_FINE_PS
:
string
:
=
"FALSE"
;
CLKOUT1_DIVIDE
:
integer
:
=
1
;
CLKOUT1_DUTY_CYCLE
:
real
:
=
0
.
500
;
CLKOUT1_PHASE
:
real
:
=
0
.
000
;
CLKOUT1_USE_FINE_PS
:
string
:
=
"FALSE"
;
CLKOUT2_DIVIDE
:
integer
:
=
1
;
CLKOUT2_DUTY_CYCLE
:
real
:
=
0
.
500
;
CLKOUT2_PHASE
:
real
:
=
0
.
000
;
CLKOUT2_USE_FINE_PS
:
string
:
=
"FALSE"
;
CLKOUT3_DIVIDE
:
integer
:
=
1
;
CLKOUT3_DUTY_CYCLE
:
real
:
=
0
.
500
;
CLKOUT3_PHASE
:
real
:
=
0
.
000
;
CLKOUT3_USE_FINE_PS
:
string
:
=
"FALSE"
;
CLKOUT4_CASCADE
:
string
:
=
"FALSE"
;
CLKOUT4_DIVIDE
:
integer
:
=
1
;
CLKOUT4_DUTY_CYCLE
:
real
:
=
0
.
500
;
CLKOUT4_PHASE
:
real
:
=
0
.
000
;
CLKOUT4_USE_FINE_PS
:
string
:
=
"FALSE"
;
CLKOUT5_DIVIDE
:
integer
:
=
1
;
CLKOUT5_DUTY_CYCLE
:
real
:
=
0
.
500
;
CLKOUT5_PHASE
:
real
:
=
0
.
000
;
CLKOUT5_USE_FINE_PS
:
string
:
=
"FALSE"
;
CLKOUT6_DIVIDE
:
integer
:
=
1
;
CLKOUT6_DUTY_CYCLE
:
real
:
=
0
.
500
;
CLKOUT6_PHASE
:
real
:
=
0
.
000
;
CLKOUT6_USE_FINE_PS
:
string
:
=
"FALSE"
;
COMPENSATION
:
string
:
=
"AUTO"
;
DIVCLK_DIVIDE
:
integer
:
=
1
;
IS_CLKFBIN_INVERTED
:
bit
:
=
'0'
;
IS_CLKIN1_INVERTED
:
bit
:
=
'0'
;
IS_CLKIN2_INVERTED
:
bit
:
=
'0'
;
IS_CLKINSEL_INVERTED
:
bit
:
=
'0'
;
IS_PSEN_INVERTED
:
bit
:
=
'0'
;
IS_PSINCDEC_INVERTED
:
bit
:
=
'0'
;
IS_PWRDWN_INVERTED
:
bit
:
=
'0'
;
IS_RST_INVERTED
:
bit
:
=
'0'
;
REF_JITTER1
:
real
:
=
0
.
010
;
REF_JITTER2
:
real
:
=
0
.
010
;
SS_EN
:
string
:
=
"FALSE"
;
SS_MODE
:
string
:
=
"CENTER_HIGH"
;
SS_MOD_PERIOD
:
integer
:
=
10000
;
STARTUP_WAIT
:
string
:
=
"FALSE"
);
port
(
CDDCDONE
:
out
std_ulogic
;
CLKFBOUT
:
out
std_ulogic
;
CLKFBOUTB
:
out
std_ulogic
;
CLKFBSTOPPED
:
out
std_ulogic
;
CLKINSTOPPED
:
out
std_ulogic
;
CLKOUT0
:
out
std_ulogic
;
CLKOUT0B
:
out
std_ulogic
;
CLKOUT1
:
out
std_ulogic
;
CLKOUT1B
:
out
std_ulogic
;
CLKOUT2
:
out
std_ulogic
;
CLKOUT2B
:
out
std_ulogic
;
CLKOUT3
:
out
std_ulogic
;
CLKOUT3B
:
out
std_ulogic
;
CLKOUT4
:
out
std_ulogic
;
CLKOUT5
:
out
std_ulogic
;
CLKOUT6
:
out
std_ulogic
;
DO
:
out
std_logic_vector
(
15
downto
0
);
DRDY
:
out
std_ulogic
;
LOCKED
:
out
std_ulogic
;
PSDONE
:
out
std_ulogic
;
CDDCREQ
:
in
std_ulogic
;
CLKFBIN
:
in
std_ulogic
;
CLKIN1
:
in
std_ulogic
;
CLKIN2
:
in
std_ulogic
;
CLKINSEL
:
in
std_ulogic
;
DADDR
:
in
std_logic_vector
(
6
downto
0
);
DCLK
:
in
std_ulogic
;
DEN
:
in
std_ulogic
;
DI
:
in
std_logic_vector
(
15
downto
0
);
DWE
:
in
std_ulogic
;
PSCLK
:
in
std_ulogic
;
PSEN
:
in
std_ulogic
;
PSINCDEC
:
in
std_ulogic
;
PWRDWN
:
in
std_ulogic
;
RST
:
in
std_ulogic
);
end
component
;
component
BUFG
is
port
(
O
:
out
std_ulogic
;
I
:
in
std_ulogic
);
end
component
BUFG
;
signal
clk_ser_prebuf
,
mmcm_clk_fb_prebuf
,
mmcm_clk_fb
:
std_logic
;
signal
clk_odelay_prebuf
,
clk_odelay
,
clk_par_prebuf
:
std_logic
;
begin
gen_use_odelay
:
if
g_global_use_odelay
generate
b_idelayctrl
:
block
attribute
IODELAY_GROUP
:
string
;
attribute
IODELAY_GROUP
of
U_IDELAYCTRL_Fine_Pulse_Gen
:
label
is
"IODELAY_FPGen"
;
signal
rst_synced
:
std_logic
;
begin
U_Sync_Reset
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_odelay
,
rst_n_i
=>
'1'
,
data_i
=>
odelayctrl_rst_i
,
synced_o
=>
rst_synced
);
U_IDELAYCTRL_Fine_Pulse_Gen
:
IDELAYCTRL
generic
map
(
SIM_DEVICE
=>
"ULTRASCALE"
-- Must be set to "ULTRASCALE"
)
port
map
(
RDY
=>
odelayctrl_rdy_o
,
REFCLK
=>
clk_odelay
,
RST
=>
odelayctrl_rst_i
);
end
block
;
end
generate
gen_use_odelay
;
gen_use_Ext_serdes_clock
:
if
g_use_external_serdes_clock
generate
-- stub for the moment
clk_ser_o
<=
clk_ser_ext_i
;
clk_par_o
<=
clk_ref_i
;
pll_locked_o
<=
'1'
;
end
generate
gen_use_Ext_serdes_clock
;
gen_use_int_serdes_clock
:
if
not
g_use_external_serdes_clock
generate
U_MMCM
:
MMCME3_ADV
generic
map
(
BANDWIDTH
=>
"OPTIMIZED"
,
-- Jitter programming (HIGH, LOW, OPTIMIZED)
COMPENSATION
=>
"AUTO"
,
-- AUTO, BUF_IN, EXTERNAL, INTERNAL, ZHOLD
STARTUP_WAIT
=>
"FALSE"
,
-- Delays DONE until MMCM is locked (FALSE, TRUE)
CLKOUT4_CASCADE
=>
"FALSE"
,
-- CLKIN_PERIOD: Input clock period in ns units, ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD
=>
16
.
0
,
CLKFBOUT_MULT_F
=>
16
.
0
,
-- Multiply value for all CLKOUT (2.000-64.000)
DIVCLK_DIVIDE
=>
1
,
-- Master division value (1-106)
CLKFBOUT_PHASE
=>
0
.
0
,
-- Phase offset in degrees of CLKFB (-360.000-360.000)
CLKFBOUT_USE_FINE_PS
=>
"FALSE"
,
CLKOUT0_DIVIDE_F
=>
2
.
0
,
-- clk_ser: 500 MHz
CLKOUT0_DUTY_CYCLE
=>
0
.
5
,
CLKOUT0_PHASE
=>
0
.
0
,
CLKOUT1_DIVIDE
=>
8
,
-- clk_par: 125 MHz
CLKOUT1_DUTY_CYCLE
=>
0
.
5
,
CLKOUT1_PHASE
=>
0
.
0
,
CLKOUT2_DIVIDE
=>
4
,
-- clk_odelay: 250 MHz
CLKOUT2_DUTY_CYCLE
=>
0
.
5
,
CLKOUT2_PHASE
=>
0
.
0
,
CLKOUT0_USE_FINE_PS
=>
"FALSE"
,
CLKOUT1_USE_FINE_PS
=>
"FALSE"
)
port
map
(
-- Clock Inputs inputs: Clock inputs
CLKIN1
=>
clk_ref_i
,
CLKIN2
=>
'0'
,
-- Clock Outputs outputs: User configurable clock outputs
CLKOUT0
=>
clk_ser_prebuf
,
CLKOUT1
=>
clk_par_prebuf
,
CLKOUT2
=>
clk_odelay_prebuf
,
-- Feedback
CLKFBOUT
=>
mmcm_clk_fb_prebuf
,
CLKFBIN
=>
mmcm_clk_fb
,
-- Status Ports outputs: MMCM status ports
LOCKED
=>
pll_locked_o
,
CDDCREQ
=>
'0'
,
-- Control Ports inputs: MMCM control ports
CLKINSEL
=>
'1'
,
PWRDWN
=>
'0'
,
RST
=>
pll_rst_i
,
-- DRP Ports inputs: Dynamic reconfiguration ports
DADDR
=>
(
others
=>
'0'
),
DCLK
=>
'0'
,
DEN
=>
'0'
,
DI
=>
(
others
=>
'0'
),
DWE
=>
'0'
,
-- Dynamic Phase Shift Ports inputs: Ports used for dynamic phase shifting of the outputs
PSCLK
=>
'0'
,
PSEN
=>
'0'
,
PSINCDEC
=>
'0'
);
u_buf_mmcm_fb
:
BUFG
port
map
(
I
=>
mmcm_clk_fb_prebuf
,
O
=>
mmcm_clk_fb
);
u_buf_mmcm_ser
:
BUFG
port
map
(
I
=>
clk_ser_prebuf
,
O
=>
clk_ser_o
);
u_buf_mmcm_par
:
BUFG
port
map
(
I
=>
clk_par_prebuf
,
O
=>
clk_par_o
);
u_buf_mmcm_odelay
:
BUFG
port
map
(
I
=>
clk_odelay_prebuf
,
O
=>
clk_odelay
);
clk_odelay_o
<=
clk_odelay
;
end
generate
gen_use_int_serdes_clock
;
end
rtl
;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.vhd
0 → 100644
View file @
8649d40d
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Generic Fine Pulse Generator Unit
---------------------------------------------------------------------------------------
-- File : fine_pulse_gen_wb.vhd
-- Author : auto-generated by wbgen2 from fine_pulse_gen_wb.wb
-- Created : Tue Jul 7 14:29:21 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_pulse_gen_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
fpg_wbgen2_pkg
.
all
;
entity
fine_pulse_gen_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
;
regs_i
:
in
t_fpg_in_registers
;
regs_o
:
out
t_fpg_out_registers
);
end
fine_pulse_gen_wb
;
architecture
syn
of
fine_pulse_gen_wb
is
signal
fpg_csr_trig0_dly0
:
std_logic
;
signal
fpg_csr_trig0_int
:
std_logic
;
signal
fpg_csr_trig1_dly0
:
std_logic
;
signal
fpg_csr_trig1_int
:
std_logic
;
signal
fpg_csr_trig2_dly0
:
std_logic
;
signal
fpg_csr_trig2_int
:
std_logic
;
signal
fpg_csr_trig3_dly0
:
std_logic
;
signal
fpg_csr_trig3_int
:
std_logic
;
signal
fpg_csr_trig4_dly0
:
std_logic
;
signal
fpg_csr_trig4_int
:
std_logic
;
signal
fpg_csr_trig5_dly0
:
std_logic
;
signal
fpg_csr_trig5_int
:
std_logic
;
signal
fpg_csr_trig6_dly0
:
std_logic
;
signal
fpg_csr_trig6_int
:
std_logic
;
signal
fpg_csr_trig7_dly0
:
std_logic
;
signal
fpg_csr_trig7_int
:
std_logic
;
signal
fpg_csr_force0_dly0
:
std_logic
;
signal
fpg_csr_force0_int
:
std_logic
;
signal
fpg_csr_force1_dly0
:
std_logic
;
signal
fpg_csr_force1_int
:
std_logic
;
signal
fpg_csr_force2_dly0
:
std_logic
;
signal
fpg_csr_force2_int
:
std_logic
;
signal
fpg_csr_force3_dly0
:
std_logic
;
signal
fpg_csr_force3_int
:
std_logic
;
signal
fpg_csr_force4_dly0
:
std_logic
;
signal
fpg_csr_force4_int
:
std_logic
;
signal
fpg_csr_force5_dly0
:
std_logic
;
signal
fpg_csr_force5_int
:
std_logic
;
signal
fpg_csr_pll_rst_int
:
std_logic
;
signal
fpg_csr_serdes_rst_int
:
std_logic
;
signal
fpg_ocr0_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr0_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr0_pol_int
:
std_logic
;
signal
fpg_ocr0_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr0_cont_int
:
std_logic
;
signal
fpg_ocr0_trig_sel_int
:
std_logic
;
signal
fpg_ocr1_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr1_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr1_pol_int
:
std_logic
;
signal
fpg_ocr1_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr1_cont_int
:
std_logic
;
signal
fpg_ocr1_trig_sel_int
:
std_logic
;
signal
fpg_ocr2_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr2_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr2_pol_int
:
std_logic
;
signal
fpg_ocr2_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr2_cont_int
:
std_logic
;
signal
fpg_ocr2_trig_sel_int
:
std_logic
;
signal
fpg_ocr3_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr3_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr3_pol_int
:
std_logic
;
signal
fpg_ocr3_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr3_cont_int
:
std_logic
;
signal
fpg_ocr3_trig_sel_int
:
std_logic
;
signal
fpg_ocr4_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr4_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr4_pol_int
:
std_logic
;
signal
fpg_ocr4_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr4_cont_int
:
std_logic
;
signal
fpg_ocr4_trig_sel_int
:
std_logic
;
signal
fpg_ocr5_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr5_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr5_pol_int
:
std_logic
;
signal
fpg_ocr5_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr5_cont_int
:
std_logic
;
signal
fpg_ocr5_trig_sel_int
:
std_logic
;
signal
fpg_ocr6_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr6_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr6_pol_int
:
std_logic
;
signal
fpg_ocr6_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr6_cont_int
:
std_logic
;
signal
fpg_ocr6_trig_sel_int
:
std_logic
;
signal
fpg_ocr7_pps_offs_int
:
std_logic_vector
(
3
downto
0
);
signal
fpg_ocr7_fine_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_ocr7_pol_int
:
std_logic
;
signal
fpg_ocr7_mask_int
:
std_logic_vector
(
7
downto
0
);
signal
fpg_ocr7_cont_int
:
std_logic
;
signal
fpg_ocr7_trig_sel_int
:
std_logic
;
signal
fpg_odelay_calib_rst_idelayctrl_int
:
std_logic
;
signal
fpg_odelay_calib_rst_odelay_int
:
std_logic
;
signal
fpg_odelay_calib_rst_oserdes_int
:
std_logic
;
signal
fpg_odelay_calib_value_int
:
std_logic_vector
(
8
downto
0
);
signal
fpg_odelay_calib_value_update_dly0
:
std_logic
;
signal
fpg_odelay_calib_value_update_int
:
std_logic
;
signal
fpg_odelay_calib_en_vtc_int
:
std_logic
;
signal
fpg_odelay_calib_cal_latch_dly0
:
std_logic
;
signal
fpg_odelay_calib_cal_latch_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
3
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
wrdata_reg
<=
slave_i
.
dat
;
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
fpg_csr_trig0_int
<=
'0'
;
fpg_csr_trig1_int
<=
'0'
;
fpg_csr_trig2_int
<=
'0'
;
fpg_csr_trig3_int
<=
'0'
;
fpg_csr_trig4_int
<=
'0'
;
fpg_csr_trig5_int
<=
'0'
;
fpg_csr_trig6_int
<=
'0'
;
fpg_csr_trig7_int
<=
'0'
;
fpg_csr_force0_int
<=
'0'
;
fpg_csr_force1_int
<=
'0'
;
fpg_csr_force2_int
<=
'0'
;
fpg_csr_force3_int
<=
'0'
;
fpg_csr_force4_int
<=
'0'
;
fpg_csr_force5_int
<=
'0'
;
fpg_csr_pll_rst_int
<=
'0'
;
fpg_csr_serdes_rst_int
<=
'0'
;
fpg_ocr0_pps_offs_int
<=
"0000"
;
fpg_ocr0_fine_int
<=
"000000000"
;
fpg_ocr0_pol_int
<=
'0'
;
fpg_ocr0_mask_int
<=
"00000000"
;
fpg_ocr0_cont_int
<=
'0'
;
fpg_ocr0_trig_sel_int
<=
'0'
;
fpg_ocr1_pps_offs_int
<=
"0000"
;
fpg_ocr1_fine_int
<=
"000000000"
;
fpg_ocr1_pol_int
<=
'0'
;
fpg_ocr1_mask_int
<=
"00000000"
;
fpg_ocr1_cont_int
<=
'0'
;
fpg_ocr1_trig_sel_int
<=
'0'
;
fpg_ocr2_pps_offs_int
<=
"0000"
;
fpg_ocr2_fine_int
<=
"000000000"
;
fpg_ocr2_pol_int
<=
'0'
;
fpg_ocr2_mask_int
<=
"00000000"
;
fpg_ocr2_cont_int
<=
'0'
;
fpg_ocr2_trig_sel_int
<=
'0'
;
fpg_ocr3_pps_offs_int
<=
"0000"
;
fpg_ocr3_fine_int
<=
"000000000"
;
fpg_ocr3_pol_int
<=
'0'
;
fpg_ocr3_mask_int
<=
"00000000"
;
fpg_ocr3_cont_int
<=
'0'
;
fpg_ocr3_trig_sel_int
<=
'0'
;
fpg_ocr4_pps_offs_int
<=
"0000"
;
fpg_ocr4_fine_int
<=
"000000000"
;
fpg_ocr4_pol_int
<=
'0'
;
fpg_ocr4_mask_int
<=
"00000000"
;
fpg_ocr4_cont_int
<=
'0'
;
fpg_ocr4_trig_sel_int
<=
'0'
;
fpg_ocr5_pps_offs_int
<=
"0000"
;
fpg_ocr5_fine_int
<=
"000000000"
;
fpg_ocr5_pol_int
<=
'0'
;
fpg_ocr5_mask_int
<=
"00000000"
;
fpg_ocr5_cont_int
<=
'0'
;
fpg_ocr5_trig_sel_int
<=
'0'
;
fpg_ocr6_pps_offs_int
<=
"0000"
;
fpg_ocr6_fine_int
<=
"000000000"
;
fpg_ocr6_pol_int
<=
'0'
;
fpg_ocr6_mask_int
<=
"00000000"
;
fpg_ocr6_cont_int
<=
'0'
;
fpg_ocr6_trig_sel_int
<=
'0'
;
fpg_ocr7_pps_offs_int
<=
"0000"
;
fpg_ocr7_fine_int
<=
"000000000"
;
fpg_ocr7_pol_int
<=
'0'
;
fpg_ocr7_mask_int
<=
"00000000"
;
fpg_ocr7_cont_int
<=
'0'
;
fpg_ocr7_trig_sel_int
<=
'0'
;
fpg_odelay_calib_rst_idelayctrl_int
<=
'0'
;
fpg_odelay_calib_rst_odelay_int
<=
'0'
;
fpg_odelay_calib_rst_oserdes_int
<=
'0'
;
fpg_odelay_calib_value_int
<=
"000000000"
;
fpg_odelay_calib_value_update_int
<=
'0'
;
fpg_odelay_calib_en_vtc_int
<=
'0'
;
fpg_odelay_calib_cal_latch_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
fpg_csr_trig0_int
<=
'0'
;
fpg_csr_trig1_int
<=
'0'
;
fpg_csr_trig2_int
<=
'0'
;
fpg_csr_trig3_int
<=
'0'
;
fpg_csr_trig4_int
<=
'0'
;
fpg_csr_trig5_int
<=
'0'
;
fpg_csr_trig6_int
<=
'0'
;
fpg_csr_trig7_int
<=
'0'
;
fpg_csr_force0_int
<=
'0'
;
fpg_csr_force1_int
<=
'0'
;
fpg_csr_force2_int
<=
'0'
;
fpg_csr_force3_int
<=
'0'
;
fpg_csr_force4_int
<=
'0'
;
fpg_csr_force5_int
<=
'0'
;
fpg_odelay_calib_value_update_int
<=
'0'
;
fpg_odelay_calib_cal_latch_int
<=
'0'
;
ack_in_progress
<=
'0'
;
else
end
if
;
else
if
((
slave_i
.
cyc
=
'1'
)
and
(
slave_i
.
stb
=
'1'
))
then
case
rwaddr_reg
(
3
downto
0
)
is
when
"0000"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_csr_trig0_int
<=
wrdata_reg
(
0
);
fpg_csr_trig1_int
<=
wrdata_reg
(
1
);
fpg_csr_trig2_int
<=
wrdata_reg
(
2
);
fpg_csr_trig3_int
<=
wrdata_reg
(
3
);
fpg_csr_trig4_int
<=
wrdata_reg
(
4
);
fpg_csr_trig5_int
<=
wrdata_reg
(
5
);
fpg_csr_trig6_int
<=
wrdata_reg
(
6
);
fpg_csr_trig7_int
<=
wrdata_reg
(
7
);
fpg_csr_force0_int
<=
wrdata_reg
(
8
);
fpg_csr_force1_int
<=
wrdata_reg
(
9
);
fpg_csr_force2_int
<=
wrdata_reg
(
10
);
fpg_csr_force3_int
<=
wrdata_reg
(
11
);
fpg_csr_force4_int
<=
wrdata_reg
(
12
);
fpg_csr_force5_int
<=
wrdata_reg
(
13
);
fpg_csr_pll_rst_int
<=
wrdata_reg
(
20
);
fpg_csr_serdes_rst_int
<=
wrdata_reg
(
21
);
end
if
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
1
)
<=
'0'
;
rddata_reg
(
2
)
<=
'0'
;
rddata_reg
(
3
)
<=
'0'
;
rddata_reg
(
4
)
<=
'0'
;
rddata_reg
(
5
)
<=
'0'
;
rddata_reg
(
6
)
<=
'0'
;
rddata_reg
(
7
)
<=
'0'
;
rddata_reg
(
8
)
<=
'0'
;
rddata_reg
(
9
)
<=
'0'
;
rddata_reg
(
10
)
<=
'0'
;
rddata_reg
(
11
)
<=
'0'
;
rddata_reg
(
12
)
<=
'0'
;
rddata_reg
(
13
)
<=
'0'
;
rddata_reg
(
19
downto
14
)
<=
regs_i
.
csr_ready_i
;
rddata_reg
(
20
)
<=
fpg_csr_pll_rst_int
;
rddata_reg
(
21
)
<=
fpg_csr_serdes_rst_int
;
rddata_reg
(
22
)
<=
regs_i
.
csr_pll_locked_i
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0001"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr0_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr0_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr0_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr0_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr0_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr0_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr0_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr0_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr0_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr0_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr0_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr0_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0010"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr1_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr1_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr1_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr1_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr1_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr1_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr1_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr1_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr1_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr1_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr1_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr1_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0011"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr2_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr2_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr2_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr2_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr2_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr2_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr2_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr2_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr2_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr2_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr2_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr2_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0100"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr3_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr3_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr3_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr3_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr3_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr3_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr3_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr3_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr3_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr3_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr3_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr3_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0101"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr4_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr4_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr4_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr4_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr4_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr4_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr4_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr4_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr4_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr4_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr4_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr4_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0110"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr5_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr5_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr5_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr5_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr5_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr5_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr5_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr5_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr5_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr5_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr5_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr5_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0111"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr6_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr6_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr6_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr6_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr6_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr6_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr6_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr6_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr6_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr6_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr6_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr6_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_ocr7_pps_offs_int
<=
wrdata_reg
(
3
downto
0
);
fpg_ocr7_fine_int
<=
wrdata_reg
(
12
downto
4
);
fpg_ocr7_pol_int
<=
wrdata_reg
(
13
);
fpg_ocr7_mask_int
<=
wrdata_reg
(
21
downto
14
);
fpg_ocr7_cont_int
<=
wrdata_reg
(
22
);
fpg_ocr7_trig_sel_int
<=
wrdata_reg
(
23
);
end
if
;
rddata_reg
(
3
downto
0
)
<=
fpg_ocr7_pps_offs_int
;
rddata_reg
(
12
downto
4
)
<=
fpg_ocr7_fine_int
;
rddata_reg
(
13
)
<=
fpg_ocr7_pol_int
;
rddata_reg
(
21
downto
14
)
<=
fpg_ocr7_mask_int
;
rddata_reg
(
22
)
<=
fpg_ocr7_cont_int
;
rddata_reg
(
23
)
<=
fpg_ocr7_trig_sel_int
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1001"
=>
if
(
slave_i
.
we
=
'1'
)
then
fpg_odelay_calib_rst_idelayctrl_int
<=
wrdata_reg
(
0
);
fpg_odelay_calib_rst_odelay_int
<=
wrdata_reg
(
1
);
fpg_odelay_calib_rst_oserdes_int
<=
wrdata_reg
(
2
);
fpg_odelay_calib_value_int
<=
wrdata_reg
(
12
downto
4
);
fpg_odelay_calib_value_update_int
<=
wrdata_reg
(
13
);
fpg_odelay_calib_en_vtc_int
<=
wrdata_reg
(
14
);
fpg_odelay_calib_cal_latch_int
<=
wrdata_reg
(
15
);
end
if
;
rddata_reg
(
0
)
<=
fpg_odelay_calib_rst_idelayctrl_int
;
rddata_reg
(
1
)
<=
fpg_odelay_calib_rst_odelay_int
;
rddata_reg
(
2
)
<=
fpg_odelay_calib_rst_oserdes_int
;
rddata_reg
(
3
)
<=
regs_i
.
odelay_calib_rdy_i
;
rddata_reg
(
12
downto
4
)
<=
fpg_odelay_calib_value_int
;
rddata_reg
(
13
)
<=
'0'
;
rddata_reg
(
14
)
<=
fpg_odelay_calib_en_vtc_int
;
rddata_reg
(
15
)
<=
'0'
;
rddata_reg
(
24
downto
16
)
<=
regs_i
.
odelay_calib_taps_i
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
slave_o
.
dat
<=
rddata_reg
;
-- Trigger Sync Pulse 0
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig0_dly0
<=
'0'
;
regs_o
.
csr_trig0_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig0_dly0
<=
fpg_csr_trig0_int
;
regs_o
.
csr_trig0_o
<=
fpg_csr_trig0_int
and
(
not
fpg_csr_trig0_dly0
);
end
if
;
end
process
;
-- Trigger Sync Pulse 1
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig1_dly0
<=
'0'
;
regs_o
.
csr_trig1_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig1_dly0
<=
fpg_csr_trig1_int
;
regs_o
.
csr_trig1_o
<=
fpg_csr_trig1_int
and
(
not
fpg_csr_trig1_dly0
);
end
if
;
end
process
;
-- Trigger Sync Pulse 2
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig2_dly0
<=
'0'
;
regs_o
.
csr_trig2_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig2_dly0
<=
fpg_csr_trig2_int
;
regs_o
.
csr_trig2_o
<=
fpg_csr_trig2_int
and
(
not
fpg_csr_trig2_dly0
);
end
if
;
end
process
;
-- Trigger Sync Pulse 3
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig3_dly0
<=
'0'
;
regs_o
.
csr_trig3_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig3_dly0
<=
fpg_csr_trig3_int
;
regs_o
.
csr_trig3_o
<=
fpg_csr_trig3_int
and
(
not
fpg_csr_trig3_dly0
);
end
if
;
end
process
;
-- Trigger Sync Pulse 4
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig4_dly0
<=
'0'
;
regs_o
.
csr_trig4_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig4_dly0
<=
fpg_csr_trig4_int
;
regs_o
.
csr_trig4_o
<=
fpg_csr_trig4_int
and
(
not
fpg_csr_trig4_dly0
);
end
if
;
end
process
;
-- Trigger Sync Pulse 5
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig5_dly0
<=
'0'
;
regs_o
.
csr_trig5_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig5_dly0
<=
fpg_csr_trig5_int
;
regs_o
.
csr_trig5_o
<=
fpg_csr_trig5_int
and
(
not
fpg_csr_trig5_dly0
);
end
if
;
end
process
;
-- Trigger Sync Pulse 6
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig6_dly0
<=
'0'
;
regs_o
.
csr_trig6_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig6_dly0
<=
fpg_csr_trig6_int
;
regs_o
.
csr_trig6_o
<=
fpg_csr_trig6_int
and
(
not
fpg_csr_trig6_dly0
);
end
if
;
end
process
;
-- Trigger Sync Pulse 7
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_trig7_dly0
<=
'0'
;
regs_o
.
csr_trig7_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_trig7_dly0
<=
fpg_csr_trig7_int
;
regs_o
.
csr_trig7_o
<=
fpg_csr_trig7_int
and
(
not
fpg_csr_trig7_dly0
);
end
if
;
end
process
;
-- Immediately Force Sync Pulse 0
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_force0_dly0
<=
'0'
;
regs_o
.
csr_force0_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_force0_dly0
<=
fpg_csr_force0_int
;
regs_o
.
csr_force0_o
<=
fpg_csr_force0_int
and
(
not
fpg_csr_force0_dly0
);
end
if
;
end
process
;
-- Immediately Force Sync Pulse 1
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_force1_dly0
<=
'0'
;
regs_o
.
csr_force1_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_force1_dly0
<=
fpg_csr_force1_int
;
regs_o
.
csr_force1_o
<=
fpg_csr_force1_int
and
(
not
fpg_csr_force1_dly0
);
end
if
;
end
process
;
-- Immediately Force Sync Pulse 2
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_force2_dly0
<=
'0'
;
regs_o
.
csr_force2_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_force2_dly0
<=
fpg_csr_force2_int
;
regs_o
.
csr_force2_o
<=
fpg_csr_force2_int
and
(
not
fpg_csr_force2_dly0
);
end
if
;
end
process
;
-- Immediately Force Sync Pulse 3
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_force3_dly0
<=
'0'
;
regs_o
.
csr_force3_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_force3_dly0
<=
fpg_csr_force3_int
;
regs_o
.
csr_force3_o
<=
fpg_csr_force3_int
and
(
not
fpg_csr_force3_dly0
);
end
if
;
end
process
;
-- Immediately Force Sync Pulse 4
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_force4_dly0
<=
'0'
;
regs_o
.
csr_force4_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_force4_dly0
<=
fpg_csr_force4_int
;
regs_o
.
csr_force4_o
<=
fpg_csr_force4_int
and
(
not
fpg_csr_force4_dly0
);
end
if
;
end
process
;
-- Immediately Force Sync Pulse 5
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_csr_force5_dly0
<=
'0'
;
regs_o
.
csr_force5_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_csr_force5_dly0
<=
fpg_csr_force5_int
;
regs_o
.
csr_force5_o
<=
fpg_csr_force5_int
and
(
not
fpg_csr_force5_dly0
);
end
if
;
end
process
;
-- Sync Pulse Ready
-- PLL Reset
regs_o
.
csr_pll_rst_o
<=
fpg_csr_pll_rst_int
;
-- Serdes Reset
regs_o
.
csr_serdes_rst_o
<=
fpg_csr_serdes_rst_int
;
-- PLL Locked
-- WR PPS offset
regs_o
.
ocr0_pps_offs_o
<=
fpg_ocr0_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr0_fine_o
<=
fpg_ocr0_fine_int
;
-- Polarity
regs_o
.
ocr0_pol_o
<=
fpg_ocr0_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr0_mask_o
<=
fpg_ocr0_mask_int
;
-- Continuous mode select
regs_o
.
ocr0_cont_o
<=
fpg_ocr0_cont_int
;
-- Trigger select
regs_o
.
ocr0_trig_sel_o
<=
fpg_ocr0_trig_sel_int
;
-- WR PPS offset
regs_o
.
ocr1_pps_offs_o
<=
fpg_ocr1_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr1_fine_o
<=
fpg_ocr1_fine_int
;
-- Polarity
regs_o
.
ocr1_pol_o
<=
fpg_ocr1_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr1_mask_o
<=
fpg_ocr1_mask_int
;
-- Continuous mode select
regs_o
.
ocr1_cont_o
<=
fpg_ocr1_cont_int
;
-- Trigger select
regs_o
.
ocr1_trig_sel_o
<=
fpg_ocr1_trig_sel_int
;
-- WR PPS offset
regs_o
.
ocr2_pps_offs_o
<=
fpg_ocr2_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr2_fine_o
<=
fpg_ocr2_fine_int
;
-- Polarity
regs_o
.
ocr2_pol_o
<=
fpg_ocr2_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr2_mask_o
<=
fpg_ocr2_mask_int
;
-- Continuous mode select
regs_o
.
ocr2_cont_o
<=
fpg_ocr2_cont_int
;
-- Trigger select
regs_o
.
ocr2_trig_sel_o
<=
fpg_ocr2_trig_sel_int
;
-- WR PPS offset
regs_o
.
ocr3_pps_offs_o
<=
fpg_ocr3_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr3_fine_o
<=
fpg_ocr3_fine_int
;
-- Polarity
regs_o
.
ocr3_pol_o
<=
fpg_ocr3_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr3_mask_o
<=
fpg_ocr3_mask_int
;
-- Continuous mode select
regs_o
.
ocr3_cont_o
<=
fpg_ocr3_cont_int
;
-- Trigger select
regs_o
.
ocr3_trig_sel_o
<=
fpg_ocr3_trig_sel_int
;
-- WR PPS offset
regs_o
.
ocr4_pps_offs_o
<=
fpg_ocr4_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr4_fine_o
<=
fpg_ocr4_fine_int
;
-- Polarity
regs_o
.
ocr4_pol_o
<=
fpg_ocr4_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr4_mask_o
<=
fpg_ocr4_mask_int
;
-- Continuous mode select
regs_o
.
ocr4_cont_o
<=
fpg_ocr4_cont_int
;
-- Trigger select
regs_o
.
ocr4_trig_sel_o
<=
fpg_ocr4_trig_sel_int
;
-- WR PPS offset
regs_o
.
ocr5_pps_offs_o
<=
fpg_ocr5_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr5_fine_o
<=
fpg_ocr5_fine_int
;
-- Polarity
regs_o
.
ocr5_pol_o
<=
fpg_ocr5_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr5_mask_o
<=
fpg_ocr5_mask_int
;
-- Continuous mode select
regs_o
.
ocr5_cont_o
<=
fpg_ocr5_cont_int
;
-- Trigger select
regs_o
.
ocr5_trig_sel_o
<=
fpg_ocr5_trig_sel_int
;
-- WR PPS offset
regs_o
.
ocr6_pps_offs_o
<=
fpg_ocr6_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr6_fine_o
<=
fpg_ocr6_fine_int
;
-- Polarity
regs_o
.
ocr6_pol_o
<=
fpg_ocr6_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr6_mask_o
<=
fpg_ocr6_mask_int
;
-- Continuous mode select
regs_o
.
ocr6_cont_o
<=
fpg_ocr6_cont_int
;
-- Trigger select
regs_o
.
ocr6_trig_sel_o
<=
fpg_ocr6_trig_sel_int
;
-- WR PPS offset
regs_o
.
ocr7_pps_offs_o
<=
fpg_ocr7_pps_offs_int
;
-- Fine delay adjust
regs_o
.
ocr7_fine_o
<=
fpg_ocr7_fine_int
;
-- Polarity
regs_o
.
ocr7_pol_o
<=
fpg_ocr7_pol_int
;
-- Serdes Bitmask
regs_o
.
ocr7_mask_o
<=
fpg_ocr7_mask_int
;
-- Continuous mode select
regs_o
.
ocr7_cont_o
<=
fpg_ocr7_cont_int
;
-- Trigger select
regs_o
.
ocr7_trig_sel_o
<=
fpg_ocr7_trig_sel_int
;
-- Reset Output IDELAYCTRL
regs_o
.
odelay_calib_rst_idelayctrl_o
<=
fpg_odelay_calib_rst_idelayctrl_int
;
-- Reset Output ODELAY
regs_o
.
odelay_calib_rst_odelay_o
<=
fpg_odelay_calib_rst_odelay_int
;
-- Reset Output OSERDES
regs_o
.
odelay_calib_rst_oserdes_o
<=
fpg_odelay_calib_rst_oserdes_int
;
-- Output Delay Ready
-- Output Delay Value
regs_o
.
odelay_calib_value_o
<=
fpg_odelay_calib_value_int
;
-- Delay value update
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_odelay_calib_value_update_dly0
<=
'0'
;
regs_o
.
odelay_calib_value_update_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_odelay_calib_value_update_dly0
<=
fpg_odelay_calib_value_update_int
;
regs_o
.
odelay_calib_value_update_o
<=
fpg_odelay_calib_value_update_int
and
(
not
fpg_odelay_calib_value_update_dly0
);
end
if
;
end
process
;
-- Enable VT compensation
regs_o
.
odelay_calib_en_vtc_o
<=
fpg_odelay_calib_en_vtc_int
;
-- Latch calibration taps
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
fpg_odelay_calib_cal_latch_dly0
<=
'0'
;
regs_o
.
odelay_calib_cal_latch_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
fpg_odelay_calib_cal_latch_dly0
<=
fpg_odelay_calib_cal_latch_int
;
regs_o
.
odelay_calib_cal_latch_o
<=
fpg_odelay_calib_cal_latch_int
and
(
not
fpg_odelay_calib_cal_latch_dly0
);
end
if
;
end
process
;
-- n Taps
rwaddr_reg
<=
slave_i
.
adr
(
5
downto
2
);
slave_o
.
stall
<=
(
not
ack_sreg
(
0
))
and
(
slave_i
.
stb
and
slave_i
.
cyc
);
slave_o
.
err
<=
'0'
;
slave_o
.
rty
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o
.
ack
<=
ack_sreg
(
0
);
end
syn
;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.wb
0 → 100644
View file @
8649d40d
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Generic Fine Pulse Generator Unit";
hdl_entity = "fine_pulse_gen_wb";
prefix = "fpg";
reg {
name = "Control/Status Register";
prefix = "CSR";
field {
name = "Trigger Sync Pulse 0";
prefix = "TRIG0";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Trigger Sync Pulse 1";
prefix = "TRIG1";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Trigger Sync Pulse 2";
prefix = "TRIG2";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Trigger Sync Pulse 3";
prefix = "TRIG3";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Trigger Sync Pulse 4";
prefix = "TRIG4";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Trigger Sync Pulse 5";
prefix = "TRIG5";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Trigger Sync Pulse 6";
prefix = "TRIG6";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Trigger Sync Pulse 7";
prefix = "TRIG7";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Immediately Force Sync Pulse 0";
prefix = "FORCE0";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Immediately Force Sync Pulse 1";
prefix = "FORCE1";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Immediately Force Sync Pulse 2";
prefix = "FORCE2";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Immediately Force Sync Pulse 3";
prefix = "FORCE3";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Immediately Force Sync Pulse 4";
prefix = "FORCE4";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Immediately Force Sync Pulse 5";
prefix = "FORCE5";
-- clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Sync Pulse Ready";
size = 6;
type = SLV;
prefix = "READY";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "PLL Reset";
prefix = "PLL_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Reset";
prefix = "SERDES_RST";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL Locked";
prefix = "PLL_LOCKED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Output 0 Control";
prefix = "OCR0";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output 1 Control";
prefix = "OCR1";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output 2 Control";
prefix = "OCR2";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output 3 Control";
prefix = "OCR3";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output 4 Control";
prefix = "OCR4";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output 5 Control";
prefix = "OCR5";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output 6 Control";
prefix = "OCR6";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output 7 Control";
prefix = "OCR7";
field {
name = "WR PPS offset";
prefix = "PPS_OFFS";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Fine delay adjust";
prefix = "FINE";
size = 9;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Polarity";
prefix = "POL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Serdes Bitmask";
prefix = "MASK";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Continuous mode select";
prefix = "CONT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Trigger select";
prefix = "TRIG_SEL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
description = "1: external trigger; 0: PPS";
};
};
reg {
name = "Output Delay Calibration (Ultrascale-specific)";
prefix = "odelay_calib";
field {
name = "Reset Output IDELAYCTRL";
type = BIT;
prefix = "rst_idelayctrl";
};
field {
name = "Reset Output ODELAY";
type = BIT;
prefix = "rst_odelay";
};
field {
name = "Reset Output OSERDES";
type = BIT;
prefix = "rst_oserdes";
};
field {
name = "Output Delay Ready";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
prefix = "rdy";
};
field {
name = "Output Delay Value";
description = "Delay value in taps";
type = SLV;
size = 9;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
prefix = "value";
};
field {
name = "Delay value update";
prefix = "value_update";
type = MONOSTABLE;
};
field {
name = "Enable VT compensation";
description = "Enable VT compensation";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
prefix = "en_vtc";
};
field {
name = "Latch calibration taps";
type = MONOSTABLE;
prefix = "cal_latch";
};
field {
name = "n Taps";
description = "Value in number of taps";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
prefix = "taps";
};
};
};
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wbgen2_pkg.vhd
0 → 100644
View file @
8649d40d
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Generic Fine Pulse Generator Unit
---------------------------------------------------------------------------------------
-- File : fine_pulse_gen_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fine_pulse_gen_wb.wb
-- Created : Tue Jul 7 14:29:21 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_pulse_gen_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
fpg_wbgen2_pkg
is
-- Input registers (user design -> WB slave)
type
t_fpg_in_registers
is
record
csr_ready_i
:
std_logic_vector
(
5
downto
0
);
csr_pll_locked_i
:
std_logic
;
odelay_calib_rdy_i
:
std_logic
;
odelay_calib_taps_i
:
std_logic_vector
(
8
downto
0
);
end
record
;
constant
c_fpg_in_registers_init_value
:
t_fpg_in_registers
:
=
(
csr_ready_i
=>
(
others
=>
'0'
),
csr_pll_locked_i
=>
'0'
,
odelay_calib_rdy_i
=>
'0'
,
odelay_calib_taps_i
=>
(
others
=>
'0'
)
);
-- Output registers (WB slave -> user design)
type
t_fpg_out_registers
is
record
csr_trig0_o
:
std_logic
;
csr_trig1_o
:
std_logic
;
csr_trig2_o
:
std_logic
;
csr_trig3_o
:
std_logic
;
csr_trig4_o
:
std_logic
;
csr_trig5_o
:
std_logic
;
csr_trig6_o
:
std_logic
;
csr_trig7_o
:
std_logic
;
csr_force0_o
:
std_logic
;
csr_force1_o
:
std_logic
;
csr_force2_o
:
std_logic
;
csr_force3_o
:
std_logic
;
csr_force4_o
:
std_logic
;
csr_force5_o
:
std_logic
;
csr_pll_rst_o
:
std_logic
;
csr_serdes_rst_o
:
std_logic
;
ocr0_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr0_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr0_pol_o
:
std_logic
;
ocr0_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr0_cont_o
:
std_logic
;
ocr0_trig_sel_o
:
std_logic
;
ocr1_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr1_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr1_pol_o
:
std_logic
;
ocr1_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr1_cont_o
:
std_logic
;
ocr1_trig_sel_o
:
std_logic
;
ocr2_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr2_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr2_pol_o
:
std_logic
;
ocr2_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr2_cont_o
:
std_logic
;
ocr2_trig_sel_o
:
std_logic
;
ocr3_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr3_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr3_pol_o
:
std_logic
;
ocr3_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr3_cont_o
:
std_logic
;
ocr3_trig_sel_o
:
std_logic
;
ocr4_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr4_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr4_pol_o
:
std_logic
;
ocr4_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr4_cont_o
:
std_logic
;
ocr4_trig_sel_o
:
std_logic
;
ocr5_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr5_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr5_pol_o
:
std_logic
;
ocr5_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr5_cont_o
:
std_logic
;
ocr5_trig_sel_o
:
std_logic
;
ocr6_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr6_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr6_pol_o
:
std_logic
;
ocr6_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr6_cont_o
:
std_logic
;
ocr6_trig_sel_o
:
std_logic
;
ocr7_pps_offs_o
:
std_logic_vector
(
3
downto
0
);
ocr7_fine_o
:
std_logic_vector
(
8
downto
0
);
ocr7_pol_o
:
std_logic
;
ocr7_mask_o
:
std_logic_vector
(
7
downto
0
);
ocr7_cont_o
:
std_logic
;
ocr7_trig_sel_o
:
std_logic
;
odelay_calib_rst_idelayctrl_o
:
std_logic
;
odelay_calib_rst_odelay_o
:
std_logic
;
odelay_calib_rst_oserdes_o
:
std_logic
;
odelay_calib_value_o
:
std_logic_vector
(
8
downto
0
);
odelay_calib_value_update_o
:
std_logic
;
odelay_calib_en_vtc_o
:
std_logic
;
odelay_calib_cal_latch_o
:
std_logic
;
end
record
;
constant
c_fpg_out_registers_init_value
:
t_fpg_out_registers
:
=
(
csr_trig0_o
=>
'0'
,
csr_trig1_o
=>
'0'
,
csr_trig2_o
=>
'0'
,
csr_trig3_o
=>
'0'
,
csr_trig4_o
=>
'0'
,
csr_trig5_o
=>
'0'
,
csr_trig6_o
=>
'0'
,
csr_trig7_o
=>
'0'
,
csr_force0_o
=>
'0'
,
csr_force1_o
=>
'0'
,
csr_force2_o
=>
'0'
,
csr_force3_o
=>
'0'
,
csr_force4_o
=>
'0'
,
csr_force5_o
=>
'0'
,
csr_pll_rst_o
=>
'0'
,
csr_serdes_rst_o
=>
'0'
,
ocr0_pps_offs_o
=>
(
others
=>
'0'
),
ocr0_fine_o
=>
(
others
=>
'0'
),
ocr0_pol_o
=>
'0'
,
ocr0_mask_o
=>
(
others
=>
'0'
),
ocr0_cont_o
=>
'0'
,
ocr0_trig_sel_o
=>
'0'
,
ocr1_pps_offs_o
=>
(
others
=>
'0'
),
ocr1_fine_o
=>
(
others
=>
'0'
),
ocr1_pol_o
=>
'0'
,
ocr1_mask_o
=>
(
others
=>
'0'
),
ocr1_cont_o
=>
'0'
,
ocr1_trig_sel_o
=>
'0'
,
ocr2_pps_offs_o
=>
(
others
=>
'0'
),
ocr2_fine_o
=>
(
others
=>
'0'
),
ocr2_pol_o
=>
'0'
,
ocr2_mask_o
=>
(
others
=>
'0'
),
ocr2_cont_o
=>
'0'
,
ocr2_trig_sel_o
=>
'0'
,
ocr3_pps_offs_o
=>
(
others
=>
'0'
),
ocr3_fine_o
=>
(
others
=>
'0'
),
ocr3_pol_o
=>
'0'
,
ocr3_mask_o
=>
(
others
=>
'0'
),
ocr3_cont_o
=>
'0'
,
ocr3_trig_sel_o
=>
'0'
,
ocr4_pps_offs_o
=>
(
others
=>
'0'
),
ocr4_fine_o
=>
(
others
=>
'0'
),
ocr4_pol_o
=>
'0'
,
ocr4_mask_o
=>
(
others
=>
'0'
),
ocr4_cont_o
=>
'0'
,
ocr4_trig_sel_o
=>
'0'
,
ocr5_pps_offs_o
=>
(
others
=>
'0'
),
ocr5_fine_o
=>
(
others
=>
'0'
),
ocr5_pol_o
=>
'0'
,
ocr5_mask_o
=>
(
others
=>
'0'
),
ocr5_cont_o
=>
'0'
,
ocr5_trig_sel_o
=>
'0'
,
ocr6_pps_offs_o
=>
(
others
=>
'0'
),
ocr6_fine_o
=>
(
others
=>
'0'
),
ocr6_pol_o
=>
'0'
,
ocr6_mask_o
=>
(
others
=>
'0'
),
ocr6_cont_o
=>
'0'
,
ocr6_trig_sel_o
=>
'0'
,
ocr7_pps_offs_o
=>
(
others
=>
'0'
),
ocr7_fine_o
=>
(
others
=>
'0'
),
ocr7_pol_o
=>
'0'
,
ocr7_mask_o
=>
(
others
=>
'0'
),
ocr7_cont_o
=>
'0'
,
ocr7_trig_sel_o
=>
'0'
,
odelay_calib_rst_idelayctrl_o
=>
'0'
,
odelay_calib_rst_odelay_o
=>
'0'
,
odelay_calib_rst_oserdes_o
=>
'0'
,
odelay_calib_value_o
=>
(
others
=>
'0'
),
odelay_calib_value_update_o
=>
'0'
,
odelay_calib_en_vtc_o
=>
'0'
,
odelay_calib_cal_latch_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_fpg_in_registers
)
return
t_fpg_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
component
fine_pulse_gen_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
;
regs_i
:
in
t_fpg_in_registers
;
regs_o
:
out
t_fpg_out_registers
);
end
component
;
end
package
;
package
body
fpg_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
tmp
(
i
):
=
'0'
;
else
tmp
(
i
):
=
x
(
i
);
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_fpg_in_registers
)
return
t_fpg_in_registers
is
variable
tmp
:
t_fpg_in_registers
;
begin
tmp
.
csr_ready_i
:
=
f_x_to_zero
(
left
.
csr_ready_i
)
or
f_x_to_zero
(
right
.
csr_ready_i
);
tmp
.
csr_pll_locked_i
:
=
f_x_to_zero
(
left
.
csr_pll_locked_i
)
or
f_x_to_zero
(
right
.
csr_pll_locked_i
);
tmp
.
odelay_calib_rdy_i
:
=
f_x_to_zero
(
left
.
odelay_calib_rdy_i
)
or
f_x_to_zero
(
right
.
odelay_calib_rdy_i
);
tmp
.
odelay_calib_taps_i
:
=
f_x_to_zero
(
left
.
odelay_calib_taps_i
)
or
f_x_to_zero
(
right
.
odelay_calib_taps_i
);
return
tmp
;
end
function
;
end
package
body
;
modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
0 → 100644
View file @
8649d40d
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
fpg_wbgen2_pkg
.
all
;
--library unisim;
--use unisim.VCOMPONENTS.all;
entity
xwb_fine_pulse_gen
is
generic
(
g_num_channels
:
integer
:
=
6
;
g_use_external_serdes_clock
:
boolean
:
=
false
;
g_target_platform
:
string
:
=
"Kintex7"
;
g_use_odelay
:
bit_vector
(
5
downto
0
)
:
=
"110000"
);
port
(
clk_sys_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
-- 62.5 MHz WR reference
rst_sys_n_i
:
in
std_logic
;
clk_ser_ext_i
:
in
std_logic
:
=
'0'
;
-- external SERDES clock, used when
-- g_use_external_serdes_clock == true
ext_trigger_p_i
:
in
std_logic
:
=
'0'
;
-- External trigger (i.e. RF receiver)
pps_p_i
:
in
std_logic
;
-- WR PPS
pulse_o
:
out
std_logic_vector
(
g_num_channels
-1
downto
0
);
clk_par_o
:
out
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
);
end
xwb_fine_pulse_gen
;
architecture
rtl
of
xwb_fine_pulse_gen
is
impure
function
f_global_use_odelay
return
boolean
is
begin
if
g_use_odelay
/=
"000000"
then
return
true
;
else
return
false
;
end
if
;
end
function
;
component
fine_pulse_gen_kintex7_shared
is
generic
(
g_global_use_odelay
:
boolean
;
g_use_external_serdes_clock
:
boolean
);
port
(
pll_rst_i
:
in
std_logic
;
clk_ser_ext_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
clk_par_o
:
out
std_logic
;
clk_ser_o
:
out
std_logic
;
clk_odelay_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
);
end
component
fine_pulse_gen_kintex7_shared
;
component
fine_pulse_gen_kintexultrascale_shared
is
generic
(
g_global_use_odelay
:
boolean
;
g_use_external_serdes_clock
:
boolean
);
port
(
pll_rst_i
:
in
std_logic
;
clk_ser_ext_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
clk_par_o
:
out
std_logic
;
clk_ser_o
:
out
std_logic
;
clk_odelay_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
);
end
component
fine_pulse_gen_kintexultrascale_shared
;
type
t_channel_state
is
(
IDLE
,
WAIT_PPS
,
WAIT_PPS_FORCED
,
WAIT_TRIGGER
);
type
t_channel
is
record
arm
:
std_logic
;
state
:
t_channel_state
;
trig_p
:
std_logic
;
trig_in
:
std_logic
;
trig_in_d
:
std_logic
;
trig_sel
:
std_logic
;
ready
:
std_logic
;
pol
:
std_logic
;
cnt
:
unsigned
(
3
downto
0
);
pps_offs
:
unsigned
(
3
downto
0
);
mask
:
std_logic_vector
(
7
downto
0
);
delay_load
:
std_logic
;
delay_fine
:
std_logic_vector
(
8
downto
0
);
cont
:
std_logic
;
force_tr
:
std_logic
;
odelay_load
:
std_logic
;
odelay_value_out
:
std_logic_vector
(
8
downto
0
);
end
record
;
type
t_channel_array
is
array
(
integer
range
<>
)
of
t_channel
;
constant
c_MAX_NUM_CHANNELS
:
integer
:
=
6
;
signal
ch
:
t_channel_array
(
0
to
c_MAX_NUM_CHANNELS
-1
);
signal
clk_par
:
std_logic
;
signal
clk_ser
:
std_logic
;
signal
clk_odelay
:
std_logic
;
signal
regs_out
:
t_fpg_out_registers
;
signal
regs_in
:
t_fpg_in_registers
;
signal
rst_n_wr
:
std_logic
;
signal
pps_p_d
:
std_logic
;
function
f_to_bool
(
x
:
bit
)
return
boolean
is
begin
if
x
=
'1'
then
return
true
;
else
return
false
;
end
if
;
end
f_to_bool
;
constant
c_pps_divider
:
integer
:
=
6250
;
signal
pps_ext
:
std_logic
;
signal
pps_cnt
:
unsigned
(
15
downto
0
);
signal
pll_locked
:
std_logic
;
signal
rst_serdes_in
,
rst_serdes
:
std_logic
;
signal
odelay_calib_rdy
:
std_logic
;
signal
pps_p1
:
std_logic
;
begin
p_extend_pps
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
rst_n_wr
=
'0'
then
pps_ext
<=
'0'
;
pps_cnt
<=
(
others
=>
'0'
);
pps_p1
<=
'0'
;
else
pps_p_d
<=
pps_p_i
;
pps_p1
<=
not
pps_p_d
and
pps_p_i
;
if
pps_p_i
=
'1'
and
pps_p_d
=
'0'
then
pps_cnt
<=
to_unsigned
(
1
,
pps_cnt
'length
);
pps_ext
<=
'0'
;
elsif
pps_cnt
=
c_pps_divider
-1
then
pps_cnt
<=
(
others
=>
'0'
);
pps_ext
<=
'1'
;
else
pps_cnt
<=
pps_cnt
+
1
;
pps_ext
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
U_Regs
:
entity
work
.
fine_pulse_gen_wb
port
map
(
rst_n_i
=>
rst_sys_n_i
,
clk_sys_i
=>
clk_sys_i
,
slave_i
=>
slave_i
,
slave_o
=>
slave_o
,
regs_i
=>
regs_in
,
regs_o
=>
regs_out
);
U_Sync_Reset
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_i
,
rst_n_i
=>
'1'
,
data_i
=>
rst_sys_n_i
,
synced_o
=>
rst_n_wr
);
U_Sync1
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_trig0_o
,
q_p_o
=>
ch
(
0
)
.
arm
);
U_Sync2
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_trig1_o
,
q_p_o
=>
ch
(
1
)
.
arm
);
U_Sync3
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_trig2_o
,
q_p_o
=>
ch
(
2
)
.
arm
);
U_Sync4
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_trig3_o
,
q_p_o
=>
ch
(
3
)
.
arm
);
U_Sync5
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_trig4_o
,
q_p_o
=>
ch
(
4
)
.
arm
);
U_Sync6
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_trig5_o
,
q_p_o
=>
ch
(
5
)
.
arm
);
U_Sync71
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_force0_o
,
q_p_o
=>
ch
(
0
)
.
force_tr
);
U_Sync72
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_force1_o
,
q_p_o
=>
ch
(
1
)
.
force_tr
);
U_Sync73
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_force2_o
,
q_p_o
=>
ch
(
2
)
.
force_tr
);
U_Sync74
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_force3_o
,
q_p_o
=>
ch
(
3
)
.
force_tr
);
U_Sync75
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_force4_o
,
q_p_o
=>
ch
(
4
)
.
force_tr
);
U_Sync76
:
entity
work
.
gc_pulse_synchronizer
port
map
(
clk_in_i
=>
clk_sys_i
,
clk_out_i
=>
clk_ref_i
,
rst_n_i
=>
rst_sys_n_i
,
d_p_i
=>
regs_out
.
csr_force5_o
,
q_p_o
=>
ch
(
5
)
.
force_tr
);
gen_ready_flags
:
for
i
in
0
to
g_num_channels
-1
generate
U_Sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
data_i
=>
ch
(
i
)
.
ready
,
synced_o
=>
regs_in
.
csr_ready_i
(
i
)
);
end
generate
gen_ready_flags
;
rst_serdes_in
<=
regs_out
.
odelay_calib_rst_oserdes_o
or
regs_out
.
csr_serdes_rst_o
;
U_Sync_Serdes_Reset
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_i
,
rst_n_i
=>
'1'
,
data_i
=>
rst_serdes_in
,
synced_o
=>
rst_serdes
);
ch
(
0
)
.
pol
<=
regs_out
.
ocr0_pol_o
;
ch
(
1
)
.
pol
<=
regs_out
.
ocr1_pol_o
;
ch
(
2
)
.
pol
<=
regs_out
.
ocr2_pol_o
;
ch
(
3
)
.
pol
<=
regs_out
.
ocr3_pol_o
;
ch
(
4
)
.
pol
<=
regs_out
.
ocr4_pol_o
;
ch
(
5
)
.
pol
<=
regs_out
.
ocr5_pol_o
;
ch
(
0
)
.
delay_fine
<=
regs_out
.
ocr0_fine_o
;
ch
(
1
)
.
delay_fine
<=
regs_out
.
ocr1_fine_o
;
ch
(
2
)
.
delay_fine
<=
regs_out
.
ocr2_fine_o
;
ch
(
3
)
.
delay_fine
<=
regs_out
.
ocr3_fine_o
;
ch
(
4
)
.
delay_fine
<=
regs_out
.
ocr4_fine_o
;
ch
(
5
)
.
delay_fine
<=
regs_out
.
ocr5_fine_o
;
ch
(
0
)
.
mask
<=
regs_out
.
ocr0_mask_o
;
ch
(
1
)
.
mask
<=
regs_out
.
ocr1_mask_o
;
ch
(
2
)
.
mask
<=
regs_out
.
ocr2_mask_o
;
ch
(
3
)
.
mask
<=
regs_out
.
ocr3_mask_o
;
ch
(
4
)
.
mask
<=
regs_out
.
ocr4_mask_o
;
ch
(
5
)
.
mask
<=
regs_out
.
ocr5_mask_o
;
ch
(
0
)
.
cont
<=
regs_out
.
ocr0_cont_o
;
ch
(
1
)
.
cont
<=
regs_out
.
ocr1_cont_o
;
ch
(
2
)
.
cont
<=
regs_out
.
ocr2_cont_o
;
ch
(
3
)
.
cont
<=
regs_out
.
ocr3_cont_o
;
ch
(
4
)
.
cont
<=
regs_out
.
ocr4_cont_o
;
ch
(
5
)
.
cont
<=
regs_out
.
ocr5_cont_o
;
ch
(
0
)
.
trig_sel
<=
regs_out
.
ocr0_trig_sel_o
;
ch
(
1
)
.
trig_sel
<=
regs_out
.
ocr1_trig_sel_o
;
ch
(
2
)
.
trig_sel
<=
regs_out
.
ocr2_trig_sel_o
;
ch
(
3
)
.
trig_sel
<=
regs_out
.
ocr3_trig_sel_o
;
ch
(
4
)
.
trig_sel
<=
regs_out
.
ocr4_trig_sel_o
;
ch
(
5
)
.
trig_sel
<=
regs_out
.
ocr5_trig_sel_o
;
ch
(
0
)
.
pps_offs
<=
unsigned
(
regs_out
.
ocr0_pps_offs_o
);
ch
(
1
)
.
pps_offs
<=
unsigned
(
regs_out
.
ocr1_pps_offs_o
);
ch
(
2
)
.
pps_offs
<=
unsigned
(
regs_out
.
ocr2_pps_offs_o
);
ch
(
3
)
.
pps_offs
<=
unsigned
(
regs_out
.
ocr3_pps_offs_o
);
ch
(
4
)
.
pps_offs
<=
unsigned
(
regs_out
.
ocr4_pps_offs_o
);
ch
(
5
)
.
pps_offs
<=
unsigned
(
regs_out
.
ocr5_pps_offs_o
);
gen_channels
:
for
i
in
0
to
g_NUM_CHANNELS
-1
generate
p_fsm
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
rst_n_wr
=
'0'
then
ch
(
i
)
.
state
<=
IDLE
;
ch
(
i
)
.
trig_p
<=
'0'
;
ch
(
i
)
.
delay_load
<=
'0'
;
else
if
ch
(
i
)
.
trig_sel
=
'1'
then
ch
(
i
)
.
trig_in
<=
ext_trigger_p_i
;
else
ch
(
i
)
.
trig_in
<=
pps_p1
;
end
if
;
ch
(
i
)
.
trig_in_d
<=
ch
(
i
)
.
trig_in
;
case
ch
(
i
)
.
state
is
when
IDLE
=>
ch
(
i
)
.
trig_p
<=
'0'
;
if
ch
(
i
)
.
force_tr
=
'1'
then
ch
(
i
)
.
ready
<=
'0'
;
ch
(
i
)
.
cnt
<=
(
others
=>
'0'
);
ch
(
i
)
.
state
<=
WAIT_PPS_FORCED
;
ch
(
i
)
.
delay_load
<=
'1'
;
elsif
ch
(
i
)
.
arm
=
'1'
then
ch
(
i
)
.
ready
<=
'0'
;
ch
(
i
)
.
cnt
<=
(
others
=>
'0'
);
ch
(
i
)
.
state
<=
WAIT_PPS
;
ch
(
i
)
.
delay_load
<=
'1'
;
else
ch
(
i
)
.
delay_load
<=
'0'
;
ch
(
i
)
.
ready
<=
'1'
;
end
if
;
when
WAIT_PPS_FORCED
=>
ch
(
i
)
.
trig_p
<=
'0'
;
ch
(
i
)
.
delay_load
<=
'0'
;
if
pps_ext
=
'1'
then
ch
(
i
)
.
state
<=
WAIT_TRIGGER
;
end
if
;
when
WAIT_PPS
=>
ch
(
i
)
.
trig_p
<=
'0'
;
ch
(
i
)
.
delay_load
<=
'0'
;
if
ch
(
i
)
.
trig_in
=
'1'
and
ch
(
i
)
.
trig_in_d
=
'0'
then
ch
(
i
)
.
state
<=
WAIT_TRIGGER
;
end
if
;
when
WAIT_TRIGGER
=>
if
ch
(
i
)
.
cnt
=
ch
(
i
)
.
pps_offs
then
ch
(
i
)
.
trig_p
<=
'1'
;
ch
(
i
)
.
state
<=
IDLE
;
else
ch
(
i
)
.
trig_p
<=
'0'
;
end
if
;
ch
(
i
)
.
cnt
<=
ch
(
i
)
.
cnt
+
1
;
end
case
;
end
if
;
end
if
;
end
process
;
gen_is_kintex7_pg
:
if
g_target_platform
=
"Kintex7"
generate
U_Pulse_Gen
:
entity
work
.
fine_pulse_gen_kintex7
generic
map
(
g_sim_delay_tap_ps
=>
50
,
g_ref_clk_freq
=>
200
.
0
,
g_use_odelay
=>
f_to_bool
(
g_use_odelay
(
i
))
)
port
map
(
clk_par_i
=>
clk_par
,
clk_serdes_i
=>
clk_ser
,
rst_serdes_i
=>
rst_serdes
,
rst_sys_n_i
=>
rst_sys_n_i
,
trig_p_i
=>
ch
(
I
)
.
trig_p
,
cont_i
=>
ch
(
i
)
.
cont
,
coarse_i
=>
ch
(
I
)
.
mask
,
pol_i
=>
ch
(
I
)
.
pol
,
pulse_o
=>
pulse_o
(
i
),
dly_load_i
=>
ch
(
i
)
.
delay_load
,
dly_fine_i
=>
ch
(
i
)
.
delay_fine
(
4
downto
0
));
end
generate
gen_is_kintex7_pg
;
gen_is_kintex_us_pg
:
if
g_target_platform
=
"KintexUltrascale"
generate
U_Pulse_Gen
:
entity
work
.
fine_pulse_gen_kintexultrascale
generic
map
(
g_sim_delay_tap_ps
=>
50
,
g_idelayctrl_ref_clk_freq
=>
250
.
0
,
g_use_odelay
=>
f_to_bool
(
g_use_odelay
(
i
))
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_par_i
=>
clk_par
,
clk_ref_i
=>
clk_ref_i
,
clk_serdes_i
=>
clk_ser
,
rst_serdes_i
=>
rst_serdes
,
rst_sys_n_i
=>
rst_sys_n_i
,
trig_p_i
=>
ch
(
I
)
.
trig_p
,
cont_i
=>
ch
(
i
)
.
cont
,
coarse_i
=>
ch
(
I
)
.
mask
,
pol_i
=>
ch
(
I
)
.
pol
,
pulse_o
=>
pulse_o
(
i
),
dly_load_i
=>
ch
(
i
)
.
delay_load
,
dly_fine_i
=>
ch
(
i
)
.
delay_fine
,
odelay_load_i
=>
ch
(
i
)
.
odelay_load
,
odelay_en_vtc_i
=>
regs_out
.
odelay_calib_en_vtc_o
,
odelay_rst_i
=>
regs_out
.
odelay_calib_rst_odelay_o
,
odelay_value_in_i
=>
regs_out
.
odelay_calib_value_o
,
odelay_value_out_o
=>
ch
(
i
)
.
odelay_value_out
,
odelay_cal_latch_i
=>
regs_out
.
odelay_calib_cal_latch_o
);
end
generate
gen_is_kintex_us_pg
;
end
generate
;
regs_in
.
odelay_calib_taps_i
<=
ch
(
0
)
.
odelay_value_out
;
gen_is_kintex7
:
if
g_target_platform
=
"Kintex7"
generate
U_K7_Shared
:
fine_pulse_gen_kintex7_shared
generic
map
(
g_global_use_odelay
=>
f_global_use_odelay
,
g_use_external_serdes_clock
=>
g_use_external_serdes_clock
)
port
map
(
pll_rst_i
=>
regs_out
.
csr_pll_rst_o
,
clk_ref_i
=>
clk_ref_i
,
clk_par_o
=>
clk_par
,
clk_ser_o
=>
clk_ser
,
clk_ser_ext_i
=>
clk_ser_ext_i
,
-- clk_odelay_o => clk_odelay,
pll_locked_o
=>
pll_locked
);
end
generate
gen_is_kintex7
;
gen_is_kintex_ultrascale
:
if
g_target_platform
=
"KintexUltrascale"
generate
U_K7U_Shared
:
entity
work
.
fine_pulse_gen_kintexultrascale_shared
generic
map
(
g_global_use_odelay
=>
f_global_use_odelay
,
g_use_external_serdes_clock
=>
g_use_external_serdes_clock
)
port
map
(
pll_rst_i
=>
regs_out
.
csr_pll_rst_o
,
clk_ref_i
=>
clk_ref_i
,
clk_par_o
=>
clk_par
,
clk_ser_o
=>
clk_ser
,
clk_ser_ext_i
=>
clk_ser_ext_i
,
-- clk_odelay_o => clk_odelay,
pll_locked_o
=>
pll_locked
,
odelayctrl_rdy_o
=>
odelay_calib_rdy
,
odelayctrl_rst_i
=>
regs_out
.
odelay_calib_rst_idelayctrl_o
);
U_Sync_Reset
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
data_i
=>
odelay_calib_rdy
,
synced_o
=>
regs_in
.
odelay_calib_rdy_i
);
end
generate
gen_is_kintex_ultrascale
;
clk_par_o
<=
clk_par
;
regs_in
.
csr_pll_locked_i
<=
pll_locked
;
end
rtl
;
modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
View file @
8649d40d
...
...
@@ -691,50 +691,6 @@ port map(
D_CYC_O
=>
D_CYC
,
D_CTI_O
=>
D_CTI
);
end
generate
gen_profile_full_debug
;
gen_profile_wr_node
:
if
(
g_profile
=
"wr_node"
)
generate
U_Wrapped_LM32
:
lm32_top_wr_node
generic
map
(
eba_reset
=>
g_reset_vector
,
sdb_address
=>
g_sdb_address
)
port
map
(
clk_i
=>
clk_sys_i
,
rst_i
=>
rst
,
interrupt
=>
irq_i
,
-- Pass slave responses through unmodified
I_DAT_I
=>
strip_undefined
(
iwb_i
.
DAT
),
I_ACK_I
=>
iwb_i
.
ACK
,
I_ERR_I
=>
iwb_i
.
ERR
,
I_RTY_I
=>
iwb_i
.
RTY
,
D_DAT_I
=>
strip_undefined
(
dwb_i
.
DAT
),
D_ACK_I
=>
dwb_i
.
ACK
,
D_ERR_I
=>
dwb_i
.
ERR
,
D_RTY_I
=>
dwb_i
.
RTY
,
-- Writes can only happen as a single cycle
I_DAT_O
=>
iwb_o
.
DAT
,
D_DAT_O
=>
dwb_o
.
DAT
,
I_WE_O
=>
iwb_o
.
WE
,
D_WE_O
=>
dwb_o
.
WE
,
-- SEL /= 1111 only for single cycles
I_SEL_O
=>
iwb_o
.
SEL
,
D_SEL_O
=>
dwb_o
.
SEL
,
-- We can ignore BTE as we know it's always linear burst mode
I_BTE_O
=>
open
,
D_BTE_O
=>
open
,
-- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
I_LOCK_O
=>
open
,
D_LOCK_O
=>
open
,
-- The LM32 has STB=CYC always
I_STB_O
=>
open
,
D_STB_O
=>
open
,
-- We monitor these pins to direct the adapter's logic
I_ADR_O
=>
I_ADR
,
I_CYC_O
=>
I_CYC
,
I_CTI_O
=>
I_CTI
,
D_ADR_O
=>
D_ADR
,
D_CYC_O
=>
D_CYC
,
D_CTI_O
=>
D_CTI
);
end
generate
gen_profile_wr_node
;
-- Cycle durations always match in our adapter
iwb_o
.
CYC
<=
I_CYC
;
...
...
modules/wishbone/wb_uart/build_wb.sh
View file @
8649d40d
#!/bin/bash
mkdir
-p
doc
wbgen2
-D
./doc/wb_simple_uart.html
-V
simple_uart_wb.vhd
-p
simple_uart_pkg.vhd
-
-cstyle
struct
-C
wb_uart.h
--hstyle
record
--lang
vhdl simple_uart_wb.wb
wbgen2
-D
./doc/wb_simple_uart.html
-V
simple_uart_wb.vhd
-p
simple_uart_pkg.vhd
-
K
../../../testbench/wishbone/include/wb_uart_regs.vh
--cstyle
defines
-C
wb_uart.h
--hstyle
record
--lang
vhdl simple_uart_wb.wb
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @
8649d40d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug
15 10:16:30 2017
-- Created : Tue Aug
25 17:17:50 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
...
...
@@ -22,78 +22,134 @@ package uart_wbgen2_pkg is
type
t_uart_in_registers
is
record
sr_tx_busy_i
:
std_logic
;
sr_rx_rdy_i
:
std_logic
;
sr_rx_fifo_supported_i
:
std_logic
;
sr_tx_fifo_supported_i
:
std_logic
;
sr_rx_fifo_valid_i
:
std_logic
;
sr_tx_fifo_empty_i
:
std_logic
;
sr_tx_fifo_full_i
:
std_logic
;
sr_rx_fifo_overflow_i
:
std_logic
;
sr_rx_fifo_bytes_i
:
std_logic_vector
(
7
downto
0
);
rdr_rx_data_i
:
std_logic_vector
(
7
downto
0
);
host_tdr_rdy_i
:
std_logic
;
host_rdr_data_i
:
std_logic_vector
(
7
downto
0
);
host_rdr_rdy_i
:
std_logic
;
host_rdr_count_i
:
std_logic_vector
(
15
downto
0
);
end
record
;
end
record
;
constant
c_uart_in_registers_init_value
:
t_uart_in_registers
:
=
(
sr_tx_busy_i
=>
'0'
,
sr_rx_rdy_i
=>
'0'
,
sr_rx_fifo_supported_i
=>
'0'
,
sr_tx_fifo_supported_i
=>
'0'
,
sr_rx_fifo_valid_i
=>
'0'
,
sr_tx_fifo_empty_i
=>
'0'
,
sr_tx_fifo_full_i
=>
'0'
,
sr_rx_fifo_overflow_i
=>
'0'
,
sr_rx_fifo_bytes_i
=>
(
others
=>
'0'
),
rdr_rx_data_i
=>
(
others
=>
'0'
),
host_tdr_rdy_i
=>
'0'
,
host_rdr_data_i
=>
(
others
=>
'0'
),
host_rdr_rdy_i
=>
'0'
,
host_rdr_count_i
=>
(
others
=>
'0'
)
);
-- Output registers (WB slave -> user design)
type
t_uart_out_registers
is
record
bcr_o
:
std_logic_vector
(
31
downto
0
);
bcr_wr_o
:
std_logic
;
tdr_tx_data_o
:
std_logic_vector
(
7
downto
0
);
tdr_tx_data_wr_o
:
std_logic
;
host_tdr_data_o
:
std_logic_vector
(
7
downto
0
);
host_tdr_data_wr_o
:
std_logic
;
end
record
;
constant
c_uart_out_registers_init_value
:
t_uart_out_registers
:
=
(
bcr_o
=>
(
others
=>
'0'
),
bcr_wr_o
=>
'0'
,
tdr_tx_data_o
=>
(
others
=>
'0'
),
tdr_tx_data_wr_o
=>
'0'
,
host_tdr_data_o
=>
(
others
=>
'0'
),
host_tdr_data_wr_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_uart_in_registers
)
return
t_uart_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
);
-- Output registers (WB slave -> user design)
type
t_uart_out_registers
is
record
sr_rx_fifo_overflow_o
:
std_logic
;
sr_rx_fifo_overflow_load_o
:
std_logic
;
bcr_o
:
std_logic_vector
(
31
downto
0
);
bcr_wr_o
:
std_logic
;
tdr_tx_data_o
:
std_logic_vector
(
7
downto
0
);
tdr_tx_data_wr_o
:
std_logic
;
host_tdr_data_o
:
std_logic_vector
(
7
downto
0
);
host_tdr_data_wr_o
:
std_logic
;
cr_rx_fifo_purge_o
:
std_logic
;
cr_tx_fifo_purge_o
:
std_logic
;
end
record
;
constant
c_uart_out_registers_init_value
:
t_uart_out_registers
:
=
(
sr_rx_fifo_overflow_o
=>
'0'
,
sr_rx_fifo_overflow_load_o
=>
'0'
,
bcr_o
=>
(
others
=>
'0'
),
bcr_wr_o
=>
'0'
,
tdr_tx_data_o
=>
(
others
=>
'0'
),
tdr_tx_data_wr_o
=>
'0'
,
host_tdr_data_o
=>
(
others
=>
'0'
),
host_tdr_data_wr_o
=>
'0'
,
cr_rx_fifo_purge_o
=>
'0'
,
cr_tx_fifo_purge_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_uart_in_registers
)
return
t_uart_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
component
simple_uart_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
rdr_rack_o
:
out
std_logic
;
host_rack_o
:
out
std_logic
;
regs_i
:
in
t_uart_in_registers
;
regs_o
:
out
t_uart_out_registers
);
end
component
;
end
package
;
package
body
uart_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
x
(
i
)
=
'1'
then
tmp
(
i
):
=
'1
'
;
else
tmp
(
i
):
=
'0'
;
end
if
;
end
loop
;
return
tmp
;
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
tmp
(
i
):
=
'0
'
;
else
tmp
(
i
):
=
x
(
i
)
;
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_uart_in_registers
)
return
t_uart_in_registers
is
variable
tmp
:
t_uart_in_registers
;
variable
tmp
:
t_uart_in_registers
;
begin
tmp
.
sr_tx_busy_i
:
=
f_x_to_zero
(
left
.
sr_tx_busy_i
)
or
f_x_to_zero
(
right
.
sr_tx_busy_i
);
tmp
.
sr_rx_rdy_i
:
=
f_x_to_zero
(
left
.
sr_rx_rdy_i
)
or
f_x_to_zero
(
right
.
sr_rx_rdy_i
);
tmp
.
rdr_rx_data_i
:
=
f_x_to_zero
(
left
.
rdr_rx_data_i
)
or
f_x_to_zero
(
right
.
rdr_rx_data_i
);
tmp
.
host_tdr_rdy_i
:
=
f_x_to_zero
(
left
.
host_tdr_rdy_i
)
or
f_x_to_zero
(
right
.
host_tdr_rdy_i
);
tmp
.
host_rdr_data_i
:
=
f_x_to_zero
(
left
.
host_rdr_data_i
)
or
f_x_to_zero
(
right
.
host_rdr_data_i
);
tmp
.
host_rdr_rdy_i
:
=
f_x_to_zero
(
left
.
host_rdr_rdy_i
)
or
f_x_to_zero
(
right
.
host_rdr_rdy_i
);
tmp
.
host_rdr_count_i
:
=
f_x_to_zero
(
left
.
host_rdr_count_i
)
or
f_x_to_zero
(
right
.
host_rdr_count_i
);
return
tmp
;
tmp
.
sr_tx_busy_i
:
=
f_x_to_zero
(
left
.
sr_tx_busy_i
)
or
f_x_to_zero
(
right
.
sr_tx_busy_i
);
tmp
.
sr_rx_rdy_i
:
=
f_x_to_zero
(
left
.
sr_rx_rdy_i
)
or
f_x_to_zero
(
right
.
sr_rx_rdy_i
);
tmp
.
sr_rx_fifo_supported_i
:
=
f_x_to_zero
(
left
.
sr_rx_fifo_supported_i
)
or
f_x_to_zero
(
right
.
sr_rx_fifo_supported_i
);
tmp
.
sr_tx_fifo_supported_i
:
=
f_x_to_zero
(
left
.
sr_tx_fifo_supported_i
)
or
f_x_to_zero
(
right
.
sr_tx_fifo_supported_i
);
tmp
.
sr_rx_fifo_valid_i
:
=
f_x_to_zero
(
left
.
sr_rx_fifo_valid_i
)
or
f_x_to_zero
(
right
.
sr_rx_fifo_valid_i
);
tmp
.
sr_tx_fifo_empty_i
:
=
f_x_to_zero
(
left
.
sr_tx_fifo_empty_i
)
or
f_x_to_zero
(
right
.
sr_tx_fifo_empty_i
);
tmp
.
sr_tx_fifo_full_i
:
=
f_x_to_zero
(
left
.
sr_tx_fifo_full_i
)
or
f_x_to_zero
(
right
.
sr_tx_fifo_full_i
);
tmp
.
sr_rx_fifo_overflow_i
:
=
f_x_to_zero
(
left
.
sr_rx_fifo_overflow_i
)
or
f_x_to_zero
(
right
.
sr_rx_fifo_overflow_i
);
tmp
.
sr_rx_fifo_bytes_i
:
=
f_x_to_zero
(
left
.
sr_rx_fifo_bytes_i
)
or
f_x_to_zero
(
right
.
sr_rx_fifo_bytes_i
);
tmp
.
rdr_rx_data_i
:
=
f_x_to_zero
(
left
.
rdr_rx_data_i
)
or
f_x_to_zero
(
right
.
rdr_rx_data_i
);
tmp
.
host_tdr_rdy_i
:
=
f_x_to_zero
(
left
.
host_tdr_rdy_i
)
or
f_x_to_zero
(
right
.
host_tdr_rdy_i
);
tmp
.
host_rdr_data_i
:
=
f_x_to_zero
(
left
.
host_rdr_data_i
)
or
f_x_to_zero
(
right
.
host_rdr_data_i
);
tmp
.
host_rdr_rdy_i
:
=
f_x_to_zero
(
left
.
host_rdr_rdy_i
)
or
f_x_to_zero
(
right
.
host_rdr_rdy_i
);
tmp
.
host_rdr_count_i
:
=
f_x_to_zero
(
left
.
host_rdr_count_i
)
or
f_x_to_zero
(
right
.
host_rdr_count_i
);
return
tmp
;
end
function
;
end
package
body
;
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @
8649d40d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_wb.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug
15 10:16:30 2017
-- Created : Tue Aug
25 17:17:50 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
...
...
@@ -18,298 +18,387 @@ use work.uart_wbgen2_pkg.all;
entity
simple_uart_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
rdr_rack_o
:
out
std_logic
;
host_rack_o
:
out
std_logic
;
regs_i
:
in
t_uart_in_registers
;
regs_o
:
out
t_uart_out_registers
);
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
rdr_rack_o
:
out
std_logic
;
host_rack_o
:
out
std_logic
;
regs_i
:
in
t_uart_in_registers
;
regs_o
:
out
t_uart_out_registers
);
end
simple_uart_wb
;
architecture
syn
of
simple_uart_wb
is
signal
uart_cr_rx_fifo_purge_dly0
:
std_logic
;
signal
uart_cr_rx_fifo_purge_int
:
std_logic
;
signal
uart_cr_tx_fifo_purge_dly0
:
std_logic
;
signal
uart_cr_tx_fifo_purge_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
regs_o
.
bcr_wr_o
<=
'0'
;
regs_o
.
tdr_tx_data_wr_o
<=
'0'
;
rdr_rack_o
<=
'0'
;
regs_o
.
host_tdr_data_wr_o
<=
'0'
;
host_rack_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
regs_o
.
sr_rx_fifo_overflow_load_o
<=
'0'
;
regs_o
.
bcr_wr_o
<=
'0'
;
regs_o
.
tdr_tx_data_wr_o
<=
'0'
;
rdr_rack_o
<=
'0'
;
regs_o
.
host_tdr_data_wr_o
<=
'0'
;
host_rack_o
<=
'0'
;
uart_cr_rx_fifo_purge_int
<=
'0'
;
uart_cr_tx_fifo_purge_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
regs_o
.
bcr_wr_o
<=
'0'
;
regs_o
.
tdr_tx_data_wr_o
<=
'0'
;
rdr_rack_o
<=
'0'
;
regs_o
.
host_tdr_data_wr_o
<=
'0'
;
host_rack_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
regs_o
.
bcr_wr_o
<=
'0'
;
regs_o
.
tdr_tx_data_wr_o
<=
'0'
;
regs_o
.
host_tdr_data_wr_o
<=
'0'
;
end
if
;
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
regs_o
.
sr_rx_fifo_overflow_load_o
<=
'0'
;
regs_o
.
bcr_wr_o
<=
'0'
;
regs_o
.
tdr_tx_data_wr_o
<=
'0'
;
rdr_rack_o
<=
'0'
;
regs_o
.
host_tdr_data_wr_o
<=
'0'
;
host_rack_o
<=
'0'
;
uart_cr_rx_fifo_purge_int
<=
'0'
;
uart_cr_tx_fifo_purge_int
<=
'0'
;
ack_in_progress
<=
'0'
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
2
downto
0
)
is
when
"000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
regs_i
.
sr_tx_busy_i
;
rddata_reg
(
1
)
<=
regs_i
.
sr_rx_rdy_i
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"001"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
bcr_wr_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
tdr_tx_data_wr_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
rdr_rx_data_i
;
rdr_rack_o
<=
'1'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
host_tdr_data_wr_o
<=
'1'
;
end
if
;
rddata_reg
(
8
)
<=
regs_i
.
host_tdr_rdy_i
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"101"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
host_rdr_data_i
;
host_rack_o
<=
'1'
;
rddata_reg
(
8
)
<=
regs_i
.
host_rdr_rdy_i
;
rddata_reg
(
24
downto
9
)
<=
regs_i
.
host_rdr_count_i
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
regs_o
.
sr_rx_fifo_overflow_load_o
<=
'0'
;
regs_o
.
bcr_wr_o
<=
'0'
;
regs_o
.
tdr_tx_data_wr_o
<=
'0'
;
regs_o
.
host_tdr_data_wr_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
2
downto
0
)
is
when
"000"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
sr_rx_fifo_overflow_load_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
regs_i
.
sr_tx_busy_i
;
rddata_reg
(
1
)
<=
regs_i
.
sr_rx_rdy_i
;
rddata_reg
(
2
)
<=
regs_i
.
sr_rx_fifo_supported_i
;
rddata_reg
(
3
)
<=
regs_i
.
sr_tx_fifo_supported_i
;
rddata_reg
(
4
)
<=
regs_i
.
sr_rx_fifo_valid_i
;
rddata_reg
(
5
)
<=
regs_i
.
sr_tx_fifo_empty_i
;
rddata_reg
(
6
)
<=
regs_i
.
sr_tx_fifo_full_i
;
rddata_reg
(
7
)
<=
regs_i
.
sr_rx_fifo_overflow_i
;
rddata_reg
(
15
downto
8
)
<=
regs_i
.
sr_rx_fifo_bytes_i
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"001"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
bcr_wr_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
tdr_tx_data_wr_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
rdr_rx_data_i
;
rdr_rack_o
<=
'1'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
host_tdr_data_wr_o
<=
'1'
;
end
if
;
rddata_reg
(
8
)
<=
regs_i
.
host_tdr_rdy_i
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"101"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
host_rdr_data_i
;
host_rack_o
<=
'1'
;
rddata_reg
(
8
)
<=
regs_i
.
host_rdr_rdy_i
;
rddata_reg
(
24
downto
9
)
<=
regs_i
.
host_rdr_count_i
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"110"
=>
if
(
wb_we_i
=
'1'
)
then
uart_cr_rx_fifo_purge_int
<=
wrdata_reg
(
0
);
uart_cr_tx_fifo_purge_int
<=
wrdata_reg
(
1
);
end
if
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
1
)
<=
'0'
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
process
;
end
if
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
wb_dat_o
<=
rddata_reg
;
-- TX busy
-- RX ready
-- RX FIFO supported
-- TX FIFO supported
-- RX FIFO data valid
-- TX FIFO empty
-- TX FIFO full
-- RX FIFO overflow
regs_o
.
sr_rx_fifo_overflow_o
<=
wrdata_reg
(
7
);
-- RX FIFO data count
-- Baudrate divider setting
-- pass-through field: Baudrate divider setting in register: Baudrate control register
regs_o
.
bcr_o
<=
wrdata_reg
(
31
downto
0
);
regs_o
.
bcr_o
<=
wrdata_reg
(
31
downto
0
);
-- Transmit data
-- pass-through field: Transmit data in register: Transmit data regsiter
regs_o
.
tdr_tx_data_o
<=
wrdata_reg
(
7
downto
0
);
regs_o
.
tdr_tx_data_o
<=
wrdata_reg
(
7
downto
0
);
-- Received data
-- TX Data
-- pass-through field: TX Data in register: Host VUART Tx register
regs_o
.
host_tdr_data_o
<=
wrdata_reg
(
7
downto
0
);
regs_o
.
host_tdr_data_o
<=
wrdata_reg
(
7
downto
0
);
-- TX Ready
-- RX Data
-- RX Ready
-- RX FIFO Count
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- RX FIFO purge
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
uart_cr_rx_fifo_purge_dly0
<=
'0'
;
regs_o
.
cr_rx_fifo_purge_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
uart_cr_rx_fifo_purge_dly0
<=
uart_cr_rx_fifo_purge_int
;
regs_o
.
cr_rx_fifo_purge_o
<=
uart_cr_rx_fifo_purge_int
and
(
not
uart_cr_rx_fifo_purge_dly0
);
end
if
;
end
process
;
-- TX FIFO purge
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
uart_cr_tx_fifo_purge_dly0
<=
'0'
;
regs_o
.
cr_tx_fifo_purge_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
uart_cr_tx_fifo_purge_dly0
<=
uart_cr_tx_fifo_purge_int
;
regs_o
.
cr_tx_fifo_purge_o
<=
uart_cr_tx_fifo_purge_int
and
(
not
uart_cr_tx_fifo_purge_dly0
);
end
if
;
end
process
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_rty_o
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
modules/wishbone/wb_uart/simple_uart_wb.wb
View file @
8649d40d
...
...
@@ -28,9 +28,84 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO supported";
description = "1: UART supports RX FIFO";
prefix = "RX_FIFO_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO supported";
description = "1: UART supports TX FIFO";
prefix = "TX_FIFO_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO data valid";
description = "1: there's some data in the RX FIFO";
prefix = "RX_FIFO_VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO empty";
description = "1: TX FIFO is empty";
prefix = "TX_FIFO_EMPTY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO full";
description = "1: TX FIFO is full";
prefix = "TX_FIFO_FULL";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO overflow";
description = "1: RX FIFO overflow occured (latched bit, write 1 to clear)";
prefix = "RX_FIFO_OVERFLOW";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "RX FIFO data count";
description = "Number of bytes currently in the RX FIFO";
prefix = "RX_FIFO_BYTES";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Baudrate control register";
description = "Register controlling the UART baudrate";
...
...
@@ -122,4 +197,28 @@ peripheral {
access_bus=READ_ONLY;
};
};
};
\ No newline at end of file
reg {
name = "UART General Control Register";
prefix = "CR";
field {
name = "RX FIFO purge";
description = "write 1: clears RX FIFO";
prefix = "RX_FIFO_PURGE";
type = MONOSTABLE;
};
field {
name = "TX FIFO purge";
description = "write 1: clears TX FIFO";
prefix = "TX_FIFO_PURGE";
type = MONOSTABLE;
};
};
};
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @
8649d40d
...
...
@@ -31,6 +31,7 @@
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
...
...
@@ -38,11 +39,15 @@ use work.UART_wbgen2_pkg.all;
entity
wb_simple_uart
is
generic
(
g_WITH_VIRTUAL_UART
:
boolean
;
g_WITH_PHYSICAL_UART
:
boolean
;
g_INTERFACE_MODE
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_ADDRESS_GRANULARITY
:
t_wishbone_address_granularity
:
=
WORD
;
g_VUART_FIFO_SIZE
:
integer
:
=
1024
g_WITH_VIRTUAL_UART
:
boolean
;
g_WITH_PHYSICAL_UART
:
boolean
;
g_WITH_PHYSICAL_UART_FIFO
:
boolean
:
=
false
;
g_TX_FIFO_SIZE
:
integer
:
=
0
;
g_RX_FIFO_SIZE
:
integer
:
=
0
;
g_INTERFACE_MODE
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_ADDRESS_GRANULARITY
:
t_wishbone_address_granularity
:
=
WORD
;
g_VUART_FIFO_SIZE
:
integer
:
=
1024
;
g_PRESET_BCR
:
integer
:
=
0
);
port
(
...
...
@@ -88,23 +93,41 @@ architecture arch of wb_simple_uart is
signal
regs_in
:
t_UART_in_registers
;
signal
regs_out
:
t_UART_out_registers
;
signal
fifo_empty
:
std_logic
;
signal
fifo_full
:
std_logic
;
signal
fifo_rd
:
std_logic
;
signal
fifo_wr
:
std_logic
;
signal
fifo_count
:
std_logic_vector
(
f_log2_size
(
g_VUART_FIFO_SIZE
)
-1
downto
0
);
signal
vuart_
fifo_empty
:
std_logic
;
signal
vuart_
fifo_full
:
std_logic
;
signal
vuart_
fifo_rd
:
std_logic
;
signal
vuart_
fifo_wr
:
std_logic
;
signal
vuart_
fifo_count
:
std_logic_vector
(
f_log2_size
(
g_VUART_FIFO_SIZE
)
-1
downto
0
);
signal
phys_rx_ready
,
phys_tx_busy
:
std_logic
;
signal
tx_fifo_empty
:
std_logic
;
signal
tx_fifo_full
:
std_logic
;
signal
tx_fifo_rd
:
std_logic
;
signal
tx_fifo_wr
:
std_logic
;
signal
tx_fifo_count
:
std_logic_vector
(
f_log2_size
(
g_TX_FIFO_SIZE
)
-1
downto
0
);
signal
tx_fifo_reset_n
:
std_logic
;
signal
phys_rx_data
:
std_logic_vector
(
7
downto
0
);
signal
rx_fifo_empty
:
std_logic
;
signal
rx_fifo_full
:
std_logic
;
signal
rx_fifo_overflow
:
std_logic
;
signal
rx_fifo_rd
:
std_logic
;
signal
rx_fifo_wr
:
std_logic
;
signal
rx_fifo_count
:
std_logic_vector
(
f_log2_size
(
g_RX_FIFO_SIZE
)
-1
downto
0
);
signal
rx_fifo_reset_n
:
std_logic
;
signal
phys_rx_ready
,
phys_tx_busy
,
phys_tx_start
:
std_logic
;
signal
phys_rx_data
,
phys_tx_data
:
std_logic_vector
(
7
downto
0
);
type
t_tx_fifo_state
is
(
IDLE
,
TRANSMIT_PENDING
);
signal
tx_fifo_state
:
t_tx_fifo_state
;
begin
-- arch
gen_check_generics
:
if
(
not
g_WITH_PHYSICAL_UART
and
not
g_WITH_VIRTUAL_UART
)
generate
assert
FALSE
report
assert
false
report
"wb_simple_uart: dummy configuration (use virtual, physical or both uarts)"
severity
FAILURE
;
severity
failure
;
end
generate
gen_check_generics
;
resized_addr
(
4
downto
0
)
<=
wb_adr_i
;
...
...
@@ -112,10 +135,10 @@ begin -- arch
U_Adapter
:
wb_slave_adapter
generic
map
(
g_MASTER_USE_STRUCT
=>
TRUE
,
g_MASTER_USE_STRUCT
=>
true
,
g_MASTER_MODE
=>
CLASSIC
,
g_MASTER_GRANULARITY
=>
WORD
,
g_SLAVE_USE_STRUCT
=>
FALSE
,
g_SLAVE_USE_STRUCT
=>
false
,
g_SLAVE_MODE
=>
g_INTERFACE_MODE
,
g_SLAVE_GRANULARITY
=>
g_ADDRESS_GRANULARITY
)
port
map
(
...
...
@@ -161,8 +184,8 @@ begin -- arch
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
uart_bcr
<=
(
others
=>
'0'
);
elsif
regs_out
.
bcr_wr_o
=
'1'
then
uart_bcr
<=
std_logic_vector
(
to_unsigned
(
g_preset_bcr
,
uart_bcr
'length
)
);
elsif
(
regs_out
.
bcr_wr_o
=
'1'
)
then
uart_bcr
<=
regs_out
.
bcr_o
;
end
if
;
end
if
;
...
...
@@ -184,8 +207,8 @@ begin -- arch
rst_n_i
=>
rst_n_i
,
baud_tick_i
=>
baud_tick
,
txd_o
=>
uart_txd_o
,
tx_start_p_i
=>
regs_out
.
tdr_tx_data_wr_o
,
tx_data_i
=>
regs_out
.
tdr_tx_data_o
,
tx_start_p_i
=>
phys_tx_start
,
tx_data_i
=>
phys_tx_data
,
tx_busy_o
=>
phys_tx_busy
);
U_RX
:
entity
work
.
uart_async_rx
...
...
@@ -200,36 +223,168 @@ begin -- arch
end
generate
gen_phys_uart
;
gen_phys_fifos
:
if
g_WITH_PHYSICAL_UART_FIFO
generate
rx_fifo_wr
<=
not
rx_fifo_full
and
phys_rx_ready
;
tx_fifo_wr
<=
not
tx_fifo_full
and
regs_out
.
tdr_tx_data_wr_o
;
tx_fifo_reset_n
<=
rst_n_i
and
not
regs_out
.
cr_tx_fifo_purge_o
;
rx_fifo_reset_n
<=
rst_n_i
and
not
regs_out
.
cr_rx_fifo_purge_o
;
rx_fifo_rd
<=
not
rx_fifo_empty
and
rdr_rack
;
U_UART_RX_FIFO
:
generic_sync_fifo
generic
map
(
g_DATA_WIDTH
=>
8
,
g_SIZE
=>
g_RX_FIFO_SIZE
,
g_WITH_COUNT
=>
true
,
g_SHOW_AHEAD
=>
true
)
port
map
(
rst_n_i
=>
rx_fifo_reset_n
,
clk_i
=>
clk_sys_i
,
d_i
=>
phys_rx_data
,
we_i
=>
rx_fifo_wr
,
q_o
=>
regs_in
.
rdr_rx_data_i
,
rd_i
=>
rdr_rack
,
empty_o
=>
rx_fifo_empty
,
full_o
=>
rx_fifo_full
,
count_o
=>
rx_fifo_count
);
U_UART_TX_FIFO
:
generic_sync_fifo
generic
map
(
g_DATA_WIDTH
=>
8
,
g_SIZE
=>
g_TX_FIFO_SIZE
,
g_WITH_COUNT
=>
false
,
g_SHOW_AHEAD
=>
true
)
port
map
(
rst_n_i
=>
tx_fifo_reset_n
,
clk_i
=>
clk_sys_i
,
d_i
=>
regs_out
.
tdr_tx_data_o
,
we_i
=>
tx_fifo_wr
,
q_o
=>
phys_tx_data
,
rd_i
=>
phys_tx_start
,
empty_o
=>
tx_fifo_empty
,
full_o
=>
tx_fifo_full
);
regs_in
.
sr_rx_fifo_supported_i
<=
'1'
;
regs_in
.
sr_tx_fifo_supported_i
<=
'1'
;
regs_in
.
sr_rx_fifo_valid_i
<=
not
rx_fifo_empty
;
regs_in
.
sr_rx_rdy_i
<=
not
rx_fifo_empty
;
regs_in
.
sr_rx_fifo_overflow_i
<=
rx_fifo_overflow
;
regs_in
.
sr_tx_fifo_full_i
<=
tx_fifo_full
;
regs_in
.
sr_tx_fifo_empty_i
<=
tx_fifo_empty
;
phys_tx_start
<=
'1'
when
tx_fifo_state
=
IDLE
and
tx_fifo_empty
=
'0'
else
'0'
;
p_rx_fifo_overflow
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rx_fifo_reset_n
=
'0'
then
rx_fifo_overflow
<=
'0'
;
else
end
if
;
end
if
;
end
process
;
p_tx_fifo_fsm
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
tx_fifo_reset_n
=
'0'
then
tx_fifo_state
<=
IDLE
;
tx_fifo_rd
<=
'0'
;
else
case
tx_fifo_state
is
when
IDLE
=>
if
tx_fifo_empty
=
'0'
then
tx_fifo_rd
<=
'1'
;
tx_fifo_state
<=
TRANSMIT_PENDING
;
end
if
;
when
TRANSMIT_PENDING
=>
tx_fifo_rd
<=
'0'
;
if
phys_tx_busy
=
'0'
then
tx_fifo_state
<=
IDLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
regs_in
.
sr_tx_busy_i
<=
tx_fifo_full
;
end
generate
gen_phys_fifos
;
gen_phys_nofifos
:
if
not
g_WITH_PHYSICAL_UART_FIFO
generate
phys_tx_data
<=
regs_out
.
tdr_tx_data_o
;
phys_tx_start
<=
regs_out
.
tdr_tx_data_wr_o
and
not
phys_tx_busy
;
regs_in
.
sr_tx_busy_i
<=
phys_tx_busy
when
(
g_WITH_PHYSICAL_UART
)
else
'0'
;
p_drive_rx_ready
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
regs_in
.
sr_rx_rdy_i
<=
'0'
;
int_o
<=
'0'
;
regs_in
.
rdr_rx_data_i
<=
(
others
=>
'0'
);
else
if
rdr_rack
=
'1'
and
phys_rx_ready
=
'0'
then
regs_in
.
sr_rx_rdy_i
<=
'0'
;
int_o
<=
'0'
;
elsif
phys_rx_ready
=
'1'
and
g_WITH_PHYSICAL_UART
then
regs_in
.
sr_rx_rdy_i
<=
'1'
;
int_o
<=
'1'
;
regs_in
.
rdr_rx_data_i
<=
phys_rx_data
;
elsif
regs_out
.
host_tdr_data_wr_o
=
'1'
and
g_WITH_VIRTUAL_UART
then
regs_in
.
sr_rx_rdy_i
<=
'1'
;
int_o
<=
'1'
;
regs_in
.
rdr_rx_data_i
<=
regs_out
.
host_tdr_data_o
;
end
if
;
end
if
;
end
if
;
end
process
p_drive_rx_ready
;
end
generate
gen_phys_nofifos
;
gen_vuart
:
if
(
g_WITH_VIRTUAL_UART
)
generate
fifo_wr
<=
not
fifo_full
and
regs_out
.
tdr_tx_data_wr_o
;
fifo_rd
<=
not
fifo_empty
and
not
regs_in
.
host_rdr_rdy_i
;
vuart_fifo_wr
<=
not
vuart_
fifo_full
and
regs_out
.
tdr_tx_data_wr_o
;
vuart_fifo_rd
<=
not
vuart_
fifo_empty
and
not
regs_in
.
host_rdr_rdy_i
;
U_VUART_FIFO
:
generic_sync_fifo
generic
map
(
g_DATA_WIDTH
=>
8
,
g_SIZE
=>
g_VUART_FIFO_SIZE
,
g_WITH_COUNT
=>
TRUE
)
g_WITH_COUNT
=>
true
,
g_SHOW_AHEAD
=>
false
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_sys_i
,
d_i
=>
regs_out
.
tdr_tx_data_o
,
we_i
=>
fifo_wr
,
we_i
=>
vuart_
fifo_wr
,
q_o
=>
regs_in
.
host_rdr_data_i
,
rd_i
=>
fifo_rd
,
empty_o
=>
fifo_empty
,
full_o
=>
fifo_full
,
count_o
=>
fifo_count
);
rd_i
=>
vuart_
fifo_rd
,
empty_o
=>
vuart_
fifo_empty
,
full_o
=>
vuart_
fifo_full
,
count_o
=>
vuart_
fifo_count
);
regs_in
.
host_rdr_count_i
(
fifo_count
'LEFT
downto
0
)
<=
fifo_count
;
regs_in
.
host_rdr_count_i
(
15
downto
fifo_count
'length
)
<=
(
others
=>
'0'
);
regs_in
.
host_rdr_count_i
(
vuart_fifo_count
'left
downto
0
)
<=
vuart_
fifo_count
;
regs_in
.
host_rdr_count_i
(
15
downto
vuart_
fifo_count
'length
)
<=
(
others
=>
'0'
);
p_vuart_rx_ready
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
regs_in
.
host_rdr_rdy_i
<=
'0'
;
elsif
fifo_rd
=
'1'
then
elsif
vuart_
fifo_rd
=
'1'
then
regs_in
.
host_rdr_rdy_i
<=
'1'
;
elsif
host_rack
=
'1'
then
regs_in
.
host_rdr_rdy_i
<=
'0'
;
...
...
@@ -245,31 +400,6 @@ begin -- arch
regs_in
.
host_rdr_rdy_i
<=
'0'
;
end
generate
gen_no_vuart
;
p_drive_rx_ready
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
regs_in
.
sr_rx_rdy_i
<=
'0'
;
int_o
<=
'0'
;
regs_in
.
rdr_rx_data_i
<=
(
others
=>
'0'
);
else
if
rdr_rack
=
'1'
and
phys_rx_ready
=
'0'
and
regs_out
.
host_tdr_data_wr_o
=
'0'
then
regs_in
.
sr_rx_rdy_i
<=
'0'
;
int_o
<=
'0'
;
elsif
phys_rx_ready
=
'1'
and
g_WITH_PHYSICAL_UART
then
regs_in
.
sr_rx_rdy_i
<=
'1'
;
int_o
<=
'1'
;
regs_in
.
rdr_rx_data_i
<=
phys_rx_data
;
elsif
regs_out
.
host_tdr_data_wr_o
=
'1'
and
g_WITH_VIRTUAL_UART
then
regs_in
.
sr_rx_rdy_i
<=
'1'
;
int_o
<=
'1'
;
regs_in
.
rdr_rx_data_i
<=
regs_out
.
host_tdr_data_o
;
end
if
;
end
if
;
end
if
;
end
process
p_drive_rx_ready
;
regs_in
.
sr_tx_busy_i
<=
phys_tx_busy
when
(
g_WITH_PHYSICAL_UART
)
else
'0'
;
regs_in
.
host_tdr_rdy_i
<=
not
regs_in
.
sr_rx_rdy_i
;
end
arch
;
modules/wishbone/wb_uart/xwb_simple_uart.vhd
View file @
8649d40d
...
...
@@ -39,9 +39,14 @@ entity xwb_simple_uart is
generic
(
g_WITH_VIRTUAL_UART
:
boolean
:
=
TRUE
;
g_WITH_PHYSICAL_UART
:
boolean
:
=
TRUE
;
g_WITH_PHYSICAL_UART_FIFO
:
boolean
:
=
false
;
g_TX_FIFO_SIZE
:
integer
:
=
0
;
g_RX_FIFO_SIZE
:
integer
:
=
0
;
g_INTERFACE_MODE
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_ADDRESS_GRANULARITY
:
t_wishbone_address_granularity
:
=
WORD
;
g_VUART_FIFO_SIZE
:
integer
:
=
1024
);
g_VUART_FIFO_SIZE
:
integer
:
=
1024
;
g_PRESET_BCR
:
integer
:
=
0
);
port
(
clk_sys_i
:
in
std_logic
;
...
...
@@ -68,7 +73,11 @@ begin -- arch
g_WITH_PHYSICAL_UART
=>
g_WITH_PHYSICAL_UART
,
g_INTERFACE_MODE
=>
g_INTERFACE_MODE
,
g_ADDRESS_GRANULARITY
=>
g_ADDRESS_GRANULARITY
,
g_VUART_FIFO_SIZE
=>
g_VUART_FIFO_SIZE
)
g_VUART_FIFO_SIZE
=>
g_VUART_FIFO_SIZE
,
g_WITH_PHYSICAL_UART_FIFO
=>
g_WITH_PHYSICAL_UART_FIFO
,
g_TX_FIFO_SIZE
=>
g_TX_FIFO_SIZE
,
g_RX_FIFO_SIZE
=>
g_RX_FIFO_SIZE
,
g_PRESET_BCR
=>
g_PRESET_BCR
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
...
...
modules/wishbone/wishbone_pkg.vhd
View file @
8649d40d
...
...
@@ -944,13 +944,19 @@ package wishbone_pkg is
uart_txd_o
:
out
std_logic
);
end
component
;
component
xwb_simple_uart
generic
(
g_with_virtual_uart
:
boolean
:
=
false
;
g_with_physical_uart
:
boolean
:
=
true
;
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_vuart_fifo_size
:
integer
:
=
1024
);
g_WITH_VIRTUAL_UART
:
boolean
:
=
TRUE
;
g_WITH_PHYSICAL_UART
:
boolean
:
=
TRUE
;
g_WITH_PHYSICAL_UART_FIFO
:
boolean
:
=
false
;
g_TX_FIFO_SIZE
:
integer
:
=
0
;
g_RX_FIFO_SIZE
:
integer
:
=
0
;
g_INTERFACE_MODE
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_ADDRESS_GRANULARITY
:
t_wishbone_address_granularity
:
=
WORD
;
g_VUART_FIFO_SIZE
:
integer
:
=
1024
;
g_PRESET_BCR
:
integer
:
=
0
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
sim/vhdl/sim_wishbone.vhd
View file @
8649d40d
...
...
@@ -5,8 +5,23 @@ use ieee.numeric_std.all;
use
work
.
wishbone_pkg
.
all
;
package
sim_wishbone
is
procedure
init
(
signal
wb_o
:
out
t_wishbone_master_out
);
-- Classic
procedure
write32
(
signal
clk
:
std_logic
;
signal
wb_o
:
out
t_wishbone_master_out
;
signal
wb_i
:
in
t_wishbone_master_in
;
addr
:
std_logic_vector
(
31
downto
0
);
data
:
std_logic_vector
(
31
downto
0
));
procedure
read32
(
signal
clk
:
std_logic
;
signal
wb_o
:
out
t_wishbone_master_out
;
signal
wb_i
:
in
t_wishbone_master_in
;
addr
:
std_logic_vector
(
31
downto
0
);
data
:
out
std_logic_vector
(
31
downto
0
));
-- PL: pipelined versions.
procedure
write32_pl
(
signal
clk
:
std_logic
;
signal
wb_o
:
out
t_wishbone_master_out
;
signal
wb_i
:
in
t_wishbone_master_in
;
...
...
@@ -52,10 +67,52 @@ package body sim_wishbone is
wait
until
rising_edge
(
clk
);
end
loop
;
wb_o
.
cyc
<=
'0'
;
wb_o
.
stb
<=
'0'
;
wb_o
.
adr
<=
(
others
=>
'X'
);
wb_o
.
dat
<=
(
others
=>
'X'
);
end
wait_ack
;
procedure
init
(
signal
wb_o
:
out
t_wishbone_master_out
)
is
begin
wb_o
.
stb
<=
'0'
;
wb_o
.
cyc
<=
'0'
;
end
init
;
procedure
write32
(
signal
clk
:
std_logic
;
signal
wb_o
:
out
t_wishbone_master_out
;
signal
wb_i
:
in
t_wishbone_master_in
;
addr
:
std_logic_vector
(
31
downto
0
);
data
:
std_logic_vector
(
31
downto
0
))
is
begin
wb_o
.
adr
<=
addr
;
wb_o
.
dat
<=
data
;
wb_o
.
sel
<=
"1111"
;
wb_o
.
we
<=
'1'
;
wb_o
.
cyc
<=
'1'
;
wb_o
.
stb
<=
'1'
;
wait
until
rising_edge
(
clk
);
wait_ack
(
clk
,
wb_o
,
wb_i
);
wait
until
rising_edge
(
clk
);
end
write32
;
procedure
read32
(
signal
clk
:
std_logic
;
signal
wb_o
:
out
t_wishbone_master_out
;
signal
wb_i
:
in
t_wishbone_master_in
;
addr
:
std_logic_vector
(
31
downto
0
);
data
:
out
std_logic_vector
(
31
downto
0
))
is
begin
wb_o
.
adr
<=
addr
;
wb_o
.
we
<=
'0'
;
wb_o
.
cyc
<=
'1'
;
wb_o
.
stb
<=
'1'
;
wait
until
rising_edge
(
clk
);
wait_ack
(
clk
,
wb_o
,
wb_i
);
data
:
=
wb_i
.
dat
;
wait
until
rising_edge
(
clk
);
end
read32
;
procedure
write32_pl
(
signal
clk
:
std_logic
;
signal
wb_o
:
out
t_wishbone_master_out
;
signal
wb_i
:
in
t_wishbone_master_in
;
...
...
@@ -104,5 +161,5 @@ package body sim_wishbone is
begin
read32_pl
(
clk
,
wb_o
,
wb_i
,
std_logic_vector
(
to_unsigned
(
addr
,
32
)),
data
);
end
read32_pl
;
end
sim_wishbone
;
software/htvic/drivers/htvic.c
View file @
8649d40d
...
...
@@ -320,6 +320,7 @@ static int htvic_irq_mapping(struct htvic_device *htvic)
&
htvic_irq_domain_ops
,
htvic
);
if
(
!
htvic
->
domain
)
{
irq_domain_free_fwnode
(
htvic
->
pdev
->
dev
.
fwnode
);
htvic
->
pdev
->
dev
.
fwnode
=
NULL
;
return
-
ENOMEM
;
}
#else
...
...
@@ -353,6 +354,7 @@ out:
irq_domain_remove
(
htvic
->
domain
);
#if KERNEL_VERSION(4, 4, 0) <= LINUX_VERSION_CODE
irq_domain_free_fwnode
(
htvic
->
pdev
->
dev
.
fwnode
);
htvic
->
pdev
->
dev
.
fwnode
=
NULL
;
#endif
return
-
EPERM
;
}
...
...
@@ -607,6 +609,7 @@ static int htvic_remove(struct platform_device *pdev)
irq_domain_remove
(
htvic
->
domain
);
#if KERNEL_VERSION(4, 4, 0) <= LINUX_VERSION_CODE
irq_domain_free_fwnode
(
htvic
->
pdev
->
dev
.
fwnode
);
htvic
->
pdev
->
dev
.
fwnode
=
NULL
;
#endif
kfree
(
htvic
);
dev_set_drvdata
(
&
pdev
->
dev
,
NULL
);
...
...
software/spi-ocores/drivers/spi/spi-ocores.c
View file @
8649d40d
...
...
@@ -481,6 +481,12 @@ static int spi_ocores_sw_xfer_next_init(struct spi_ocores *sp)
else
hz
=
sp
->
master
->
cur_msg
->
spi
->
max_speed_hz
;
divider
=
(
sp
->
clock_hz
/
(
hz
*
2
))
-
1
;
if
(
WARN_ON
(
divider
==
0
))
{
dev_warn
(
&
sp
->
master
->
dev
,
"divider value is 0
\n
"
);
divider
=
1
;
}
spi_ocores_hw_xfer_config
(
sp
,
ctrl
,
divider
);
...
...
testbench/common/gc_ds182x_readout/Manifest.py
0 → 100644
View file @
8649d40d
action
=
"simulation"
sim_tool
=
"ghdl"
target
=
"xilinx"
syn_device
=
"xc6slx45t"
sim_top
=
"gc_ds182x_readout_tb"
files
=
[
"gc_ds182x_readout_tb.vhd"
,
]
modules
=
{
"local"
:
[
"../../../"
,
],
}
testbench/common/gc_ds182x_readout/gc_ds182x_readout_tb.vhd
0 → 100644
View file @
8649d40d
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
gc_ds182x_readout_tb
is
end
gc_ds182x_readout_tb
;
architecture
behav
of
gc_ds182x_readout_tb
is
constant
C_PERIOD_NS
:
time
:
=
500
ns
;
constant
g_CLOCK_FREQ_KHZ
:
integer
:
=
1
_
000
_
000
ns
/
C_PERIOD_NS
;
signal
clk
:
std_logic
:
=
'0'
;
signal
rst_n
:
std_logic
;
signal
onewire
:
std_logic
;
-- IO to be connected to the chip(DS1820/DS1822)
signal
onewire_b
:
std_logic
;
signal
id
:
std_logic_vector
(
63
downto
0
);
-- id_o value
signal
temper
:
std_logic_vector
(
15
downto
0
);
-- temperature value (refreshed every second)
signal
id_read
:
std_logic
;
-- id_o value is valid_o
signal
id_ok
:
std_logic
;
-- Same as id_read_o, but not reset with rst_n_i
signal
pps
:
std_logic
:
=
'0'
;
signal
pps_cnt
:
natural
;
begin
dut
:
entity
work
.
gc_ds182x_readout
generic
map
(
g_CLOCK_FREQ_KHZ
=>
g_CLOCK_FREQ_KHZ
,
g_USE_INTERNAL_PPS
=>
False
)
port
map
(
clk_i
=>
clk
,
rst_n_i
=>
rst_n
,
pps_p_i
=>
pps
,
onewire_b
=>
onewire_b
,
id_o
=>
id
,
temper_o
=>
temper
,
id_read_o
=>
id_read
,
id_ok_o
=>
id_ok
);
clk
<=
not
clk
after
C_PERIOD_NS
/
2
;
process
(
clk
)
is
begin
if
rising_edge
(
clk
)
then
pps_cnt
<=
pps_cnt
+
1
;
-- Cheat on pps: one pulse every 10 ms, to speed up simulation
if
pps_cnt
=
10
ms
/
C_PERIOD_NS
then
pps
<=
'1'
;
pps_cnt
<=
0
;
else
pps
<=
'0'
;
end
if
;
end
if
;
end
process
;
-- Pull-up on onewire
onewire_b
<=
'H'
;
onewire
<=
to_x01
(
onewire_b
);
process
begin
rst_n
<=
'0'
;
wait
for
C_PERIOD_NS
*
2
;
rst_n
<=
'1'
;
wait
;
end
process
;
blk_slave
:
block
type
ow_lstate_t
is
(
UNSYNC
,
IDLE
,
START
,
WAIT_END
,
RESET
,
PRESENCE_WAIT
,
PRESENCE_PULSE
);
signal
state
:
ow_lstate_t
:
=
UNSYNC
;
signal
count
:
natural
;
signal
ow_byte
:
std_logic_vector
(
7
downto
0
);
signal
ow_tx
:
std_logic_vector
(
7
downto
0
);
signal
bit_cnt
:
natural
;
signal
ow_rst
:
std_logic
:
=
'0'
;
signal
ow_dat
:
std_logic
:
=
'0'
;
signal
ow_rd
:
std_logic
:
=
'1'
;
type
ow_hstate_t
is
(
WAIT_RST
,
WAIT_CMD
,
TX_REPLY
);
signal
hstate
:
ow_hstate_t
:
=
WAIT_RST
;
signal
ow_cmd
:
std_logic_vector
(
7
downto
0
);
begin
-- Dummy DS1852
proc_low
:
process
variable
val
:
std_logic
;
begin
count
<=
count
+
1
;
onewire_b
<=
'Z'
;
ow_rst
<=
'0'
;
ow_dat
<=
'0'
;
case
state
is
when
UNSYNC
=>
if
onewire
=
'1'
then
state
<=
IDLE
;
end
if
;
when
IDLE
=>
if
onewire
=
'0'
then
-- Start of slot
state
<=
START
;
count
<=
0
;
end
if
;
when
START
=>
if
ow_rd
=
'1'
and
count
=
30
then
-- Sample
val
:
=
onewire
;
ow_byte
<=
onewire
&
ow_byte
(
7
downto
1
);
if
bit_cnt
=
7
then
ow_dat
<=
'1'
;
bit_cnt
<=
0
;
else
bit_cnt
<=
bit_cnt
+
1
;
end
if
;
state
<=
WAIT_END
;
elsif
ow_rd
=
'0'
then
if
count
=
0
then
if
bit_cnt
=
0
then
ow_byte
<=
ow_tx
;
end
if
;
elsif
count
<
45
then
if
ow_byte
(
0
)
=
'0'
then
onewire_b
<=
'0'
;
end
if
;
else
onewire_b
<=
'Z'
;
if
bit_cnt
=
7
then
bit_cnt
<=
0
;
ow_dat
<=
'1'
;
else
ow_byte
(
6
downto
0
)
<=
ow_byte
(
7
downto
1
);
bit_cnt
<=
bit_cnt
+
1
;
end
if
;
state
<=
WAIT_END
;
end
if
;
end
if
;
when
WAIT_END
=>
if
onewire
=
'1'
then
state
<=
IDLE
;
end
if
;
if
count
>
470
then
state
<=
RESET
;
ow_rst
<=
'1'
;
end
if
;
when
RESET
=>
if
onewire
=
'1'
then
state
<=
PRESENCE_WAIT
;
count
<=
0
;
bit_cnt
<=
0
;
end
if
;
when
PRESENCE_WAIT
=>
if
count
=
40
then
state
<=
PRESENCE_PULSE
;
count
<=
0
;
end
if
;
when
PRESENCE_PULSE
=>
onewire_b
<=
'0'
;
if
count
=
100
then
onewire_b
<=
'Z'
;
state
<=
UNSYNC
;
end
if
;
end
case
;
wait
for
1
us
;
end
process
;
proc_h
:
process
(
ow_rst
,
ow_dat
)
variable
reply
:
std_logic_vector
(
0
to
71
);
variable
rep_len
:
natural
;
begin
case
hstate
is
when
WAIT_RST
=>
if
ow_rst
=
'1'
then
report
"DS182x: reset"
;
ow_rd
<=
'1'
;
hstate
<=
WAIT_CMD
;
end
if
;
when
WAIT_CMD
=>
if
ow_dat
=
'1'
then
report
"DS182x: cmd "
&
to_hstring
(
ow_byte
);
ow_cmd
<=
ow_byte
;
if
ow_byte
=
x"33"
then
-- Read ROM
reply
:
=
x"28_12_34_56_78_9a_bc_1e_00"
;
rep_len
:
=
8
;
hstate
<=
TX_REPLY
;
elsif
ow_byte
=
x"cc"
then
-- Skip ROM
hstate
<=
WAIT_CMD
;
elsif
ow_byte
=
x"44"
then
-- Convert
-- TODO: send status.
hstate
<=
WAIT_CMD
;
elsif
ow_byte
=
x"be"
then
-- Read scratchpad
reply
:
=
x"50_05_11_22_1f_ff_00_10_2e"
;
rep_len
:
=
9
;
hstate
<=
TX_REPLY
;
end
if
;
end
if
;
when
TX_REPLY
=>
ow_tx
<=
reply
(
0
to
7
);
ow_rd
<=
'0'
;
if
ow_dat
=
'1'
then
reply
(
0
to
reply
'right
-
8
)
:
=
reply
(
8
to
reply
'right
);
rep_len
:
=
rep_len
-
1
;
if
rep_len
=
0
then
ow_rd
<=
'1'
;
hstate
<=
WAIT_CMD
;
end
if
;
end
if
;
end
case
;
end
process
;
end
block
blk_slave
;
end
behav
;
testbench/wishbone/include/wb_fine_pulse_gen_regs.vh
0 → 100644
View file @
8649d40d
`define ADDR_FPG_CSR 6'h0
`define FPG_CSR_TRIG0_OFFSET 0
`define FPG_CSR_TRIG0 32'h00000001
`define FPG_CSR_TRIG1_OFFSET 1
`define FPG_CSR_TRIG1 32'h00000002
`define FPG_CSR_TRIG2_OFFSET 2
`define FPG_CSR_TRIG2 32'h00000004
`define FPG_CSR_TRIG3_OFFSET 3
`define FPG_CSR_TRIG3 32'h00000008
`define FPG_CSR_TRIG4_OFFSET 4
`define FPG_CSR_TRIG4 32'h00000010
`define FPG_CSR_TRIG5_OFFSET 5
`define FPG_CSR_TRIG5 32'h00000020
`define FPG_CSR_TRIG6_OFFSET 6
`define FPG_CSR_TRIG6 32'h00000040
`define FPG_CSR_TRIG7_OFFSET 7
`define FPG_CSR_TRIG7 32'h00000080
`define FPG_CSR_FORCE0_OFFSET 8
`define FPG_CSR_FORCE0 32'h00000100
`define FPG_CSR_FORCE1_OFFSET 9
`define FPG_CSR_FORCE1 32'h00000200
`define FPG_CSR_FORCE2_OFFSET 10
`define FPG_CSR_FORCE2 32'h00000400
`define FPG_CSR_FORCE3_OFFSET 11
`define FPG_CSR_FORCE3 32'h00000800
`define FPG_CSR_FORCE4_OFFSET 12
`define FPG_CSR_FORCE4 32'h00001000
`define FPG_CSR_FORCE5_OFFSET 13
`define FPG_CSR_FORCE5 32'h00002000
`define FPG_CSR_READY_OFFSET 14
`define FPG_CSR_READY 32'h000fc000
`define FPG_CSR_PLL_RST_OFFSET 20
`define FPG_CSR_PLL_RST 32'h00100000
`define FPG_CSR_SERDES_RST_OFFSET 21
`define FPG_CSR_SERDES_RST 32'h00200000
`define FPG_CSR_PLL_LOCKED_OFFSET 22
`define FPG_CSR_PLL_LOCKED 32'h00400000
`define ADDR_FPG_OCR0 6'h4
`define FPG_OCR0_PPS_OFFS_OFFSET 0
`define FPG_OCR0_PPS_OFFS 32'h0000000f
`define FPG_OCR0_FINE_OFFSET 4
`define FPG_OCR0_FINE 32'h00001ff0
`define FPG_OCR0_POL_OFFSET 13
`define FPG_OCR0_POL 32'h00002000
`define FPG_OCR0_MASK_OFFSET 14
`define FPG_OCR0_MASK 32'h003fc000
`define FPG_OCR0_CONT_OFFSET 22
`define FPG_OCR0_CONT 32'h00400000
`define FPG_OCR0_TRIG_SEL_OFFSET 23
`define FPG_OCR0_TRIG_SEL 32'h00800000
`define ADDR_FPG_OCR1 6'h8
`define FPG_OCR1_PPS_OFFS_OFFSET 0
`define FPG_OCR1_PPS_OFFS 32'h0000000f
`define FPG_OCR1_FINE_OFFSET 4
`define FPG_OCR1_FINE 32'h00001ff0
`define FPG_OCR1_POL_OFFSET 13
`define FPG_OCR1_POL 32'h00002000
`define FPG_OCR1_MASK_OFFSET 14
`define FPG_OCR1_MASK 32'h003fc000
`define FPG_OCR1_CONT_OFFSET 22
`define FPG_OCR1_CONT 32'h00400000
`define FPG_OCR1_TRIG_SEL_OFFSET 23
`define FPG_OCR1_TRIG_SEL 32'h00800000
`define ADDR_FPG_OCR2 6'hc
`define FPG_OCR2_PPS_OFFS_OFFSET 0
`define FPG_OCR2_PPS_OFFS 32'h0000000f
`define FPG_OCR2_FINE_OFFSET 4
`define FPG_OCR2_FINE 32'h00001ff0
`define FPG_OCR2_POL_OFFSET 13
`define FPG_OCR2_POL 32'h00002000
`define FPG_OCR2_MASK_OFFSET 14
`define FPG_OCR2_MASK 32'h003fc000
`define FPG_OCR2_CONT_OFFSET 22
`define FPG_OCR2_CONT 32'h00400000
`define FPG_OCR2_TRIG_SEL_OFFSET 23
`define FPG_OCR2_TRIG_SEL 32'h00800000
`define ADDR_FPG_OCR3 6'h10
`define FPG_OCR3_PPS_OFFS_OFFSET 0
`define FPG_OCR3_PPS_OFFS 32'h0000000f
`define FPG_OCR3_FINE_OFFSET 4
`define FPG_OCR3_FINE 32'h00001ff0
`define FPG_OCR3_POL_OFFSET 13
`define FPG_OCR3_POL 32'h00002000
`define FPG_OCR3_MASK_OFFSET 14
`define FPG_OCR3_MASK 32'h003fc000
`define FPG_OCR3_CONT_OFFSET 22
`define FPG_OCR3_CONT 32'h00400000
`define FPG_OCR3_TRIG_SEL_OFFSET 23
`define FPG_OCR3_TRIG_SEL 32'h00800000
`define ADDR_FPG_OCR4 6'h14
`define FPG_OCR4_PPS_OFFS_OFFSET 0
`define FPG_OCR4_PPS_OFFS 32'h0000000f
`define FPG_OCR4_FINE_OFFSET 4
`define FPG_OCR4_FINE 32'h00001ff0
`define FPG_OCR4_POL_OFFSET 13
`define FPG_OCR4_POL 32'h00002000
`define FPG_OCR4_MASK_OFFSET 14
`define FPG_OCR4_MASK 32'h003fc000
`define FPG_OCR4_CONT_OFFSET 22
`define FPG_OCR4_CONT 32'h00400000
`define FPG_OCR4_TRIG_SEL_OFFSET 23
`define FPG_OCR4_TRIG_SEL 32'h00800000
`define ADDR_FPG_OCR5 6'h18
`define FPG_OCR5_PPS_OFFS_OFFSET 0
`define FPG_OCR5_PPS_OFFS 32'h0000000f
`define FPG_OCR5_FINE_OFFSET 4
`define FPG_OCR5_FINE 32'h00001ff0
`define FPG_OCR5_POL_OFFSET 13
`define FPG_OCR5_POL 32'h00002000
`define FPG_OCR5_MASK_OFFSET 14
`define FPG_OCR5_MASK 32'h003fc000
`define FPG_OCR5_CONT_OFFSET 22
`define FPG_OCR5_CONT 32'h00400000
`define FPG_OCR5_TRIG_SEL_OFFSET 23
`define FPG_OCR5_TRIG_SEL 32'h00800000
`define ADDR_FPG_OCR6 6'h1c
`define FPG_OCR6_PPS_OFFS_OFFSET 0
`define FPG_OCR6_PPS_OFFS 32'h0000000f
`define FPG_OCR6_FINE_OFFSET 4
`define FPG_OCR6_FINE 32'h00001ff0
`define FPG_OCR6_POL_OFFSET 13
`define FPG_OCR6_POL 32'h00002000
`define FPG_OCR6_MASK_OFFSET 14
`define FPG_OCR6_MASK 32'h003fc000
`define FPG_OCR6_CONT_OFFSET 22
`define FPG_OCR6_CONT 32'h00400000
`define FPG_OCR6_TRIG_SEL_OFFSET 23
`define FPG_OCR6_TRIG_SEL 32'h00800000
`define ADDR_FPG_OCR7 6'h20
`define FPG_OCR7_PPS_OFFS_OFFSET 0
`define FPG_OCR7_PPS_OFFS 32'h0000000f
`define FPG_OCR7_FINE_OFFSET 4
`define FPG_OCR7_FINE 32'h00001ff0
`define FPG_OCR7_POL_OFFSET 13
`define FPG_OCR7_POL 32'h00002000
`define FPG_OCR7_MASK_OFFSET 14
`define FPG_OCR7_MASK 32'h003fc000
`define FPG_OCR7_CONT_OFFSET 22
`define FPG_OCR7_CONT 32'h00400000
`define FPG_OCR7_TRIG_SEL_OFFSET 23
`define FPG_OCR7_TRIG_SEL 32'h00800000
`define ADDR_FPG_ODELAY_CALIB 6'h24
`define FPG_ODELAY_CALIB_RST_IDELAYCTRL_OFFSET 0
`define FPG_ODELAY_CALIB_RST_IDELAYCTRL 32'h00000001
`define FPG_ODELAY_CALIB_RST_ODELAY_OFFSET 1
`define FPG_ODELAY_CALIB_RST_ODELAY 32'h00000002
`define FPG_ODELAY_CALIB_RST_OSERDES_OFFSET 2
`define FPG_ODELAY_CALIB_RST_OSERDES 32'h00000004
`define FPG_ODELAY_CALIB_RDY_OFFSET 3
`define FPG_ODELAY_CALIB_RDY 32'h00000008
`define FPG_ODELAY_CALIB_VALUE_OFFSET 4
`define FPG_ODELAY_CALIB_VALUE 32'h00001ff0
`define FPG_ODELAY_CALIB_VALUE_UPDATE_OFFSET 13
`define FPG_ODELAY_CALIB_VALUE_UPDATE 32'h00002000
`define FPG_ODELAY_CALIB_EN_VTC_OFFSET 14
`define FPG_ODELAY_CALIB_EN_VTC 32'h00004000
`define FPG_ODELAY_CALIB_CAL_LATCH_OFFSET 15
`define FPG_ODELAY_CALIB_CAL_LATCH 32'h00008000
`define FPG_ODELAY_CALIB_TAPS_OFFSET 16
`define FPG_ODELAY_CALIB_TAPS 32'h01ff0000
testbench/wishbone/wb_fine_pulse_gen/Manifest.py
0 → 100644
View file @
8649d40d
sim_tool
=
"modelsim"
top_module
=
"main"
action
=
"simulation"
target
=
"xilinx"
fetchto
=
"../../ip_cores"
vcom_opt
=
"-mixedsvvh l -2008"
sim_top
=
"main"
syn_device
=
"xc7k70t"
include_dirs
=
[
"../../../sim"
,
"../include"
]
modelsim_ini_path
=
"~/eda/modelsim-lib-2016.4"
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../../../"
]
}
testbench/wishbone/wb_fine_pulse_gen/main.sv
0 → 100644
View file @
8649d40d
//------------------------------------------------------------------------------
// Copyright CERN 2018
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale
1
ps
/
1
ps
`include
"vhd_wishbone_master.svh"
`include
"wb_fine_pulse_gen_regs.vh"
module
dupa
;
xwb_fine_pulse_gen
dut
()
;
endmodule
// dupa
class
IBusDevice
;
CBusAccessor
m_acc
;
uint64_t
m_base
;
function
new
(
CBusAccessor
acc
,
uint64_t
base
)
;
m_acc
=
acc
;
m_base
=
base
;
endfunction
// new
virtual
task
write32
(
uint32_t
addr
,
uint32_t
val
)
;
m_acc
.
write
(
m_base
+
addr
,
val
)
;
endtask
// write
virtual
task
read32
(
uint32_t
addr
,
output
uint32_t
val
)
;
uint64_t
val64
;
m_acc
.
read
(
m_base
+
addr
,
val64
)
;
val
=
val64
;
endtask
// write
endclass
// BusDevice
class
FinePulseGenDriver
extends
IBusDevice
;
protected
int
m_use_delayctrl
=
1
;
protected
real
m_coarse_range
=
16.0
;
protected
real
m_delay_tap_size
=
0.078
;
/*ns*/
protected
int
m_fine_taps
;
function
new
(
CBusAccessor
acc
,
int
base
)
;
super
.
new
(
acc
,
base
)
;
endfunction
// new
task
automatic
calibrate
()
;
int
rv
;
real
calib_time
;
int
calib_taps
;
$
error
(
"Calibrate start"
)
;
write32
(
`ADDR_FPG_ODELAY_CALIB
,
`FPG_ODELAY_CALIB_EN_VTC
)
;
write32
(
`ADDR_FPG_ODELAY_CALIB
,
`FPG_ODELAY_CALIB_RST_IDELAYCTRL
|
`FPG_ODELAY_CALIB_RST_OSERDES
|
`FPG_ODELAY_CALIB_RST_ODELAY
)
;
#
100
ns
;
write32
(
`ADDR_FPG_ODELAY_CALIB
,
`FPG_ODELAY_CALIB_RST_IDELAYCTRL
|
`FPG_ODELAY_CALIB_RST_OSERDES
)
;
#
100
ns
;
write32
(
`ADDR_FPG_ODELAY_CALIB
,
`FPG_ODELAY_CALIB_RST_IDELAYCTRL
)
;
#
100
ns
;
write32
(
`ADDR_FPG_ODELAY_CALIB
,
0
)
;
#
100
ns
;
while
(
1
)
begin
read32
(
`ADDR_FPG_ODELAY_CALIB
,
rv
)
;
$
display
(
"odelay = %x"
,
rv
)
;
if
(
rv
&
`FPG_ODELAY_CALIB_RDY
)
break
;
end
write32
(
`ADDR_FPG_ODELAY_CALIB
,
0
)
;
write32
(
`ADDR_FPG_ODELAY_CALIB
,
`FPG_ODELAY_CALIB_CAL_LATCH
)
;
read32
(
`ADDR_FPG_ODELAY_CALIB
,
rv
)
;
calib_time
=
real
'
(
1.0
)
;
calib_taps
=
(
rv
&
`FPG_ODELAY_CALIB_TAPS
)
>>
`FPG_ODELAY_CALIB_TAPS_OFFSET
;
$
display
(
"FPG ODELAY calibration done, %.1f ns = %d taps
\n
"
,
calib_time
,
calib_taps
)
;
m_delay_tap_size
=
calib_time
/
real
'
(
calib_taps
)
;
endtask
// calibrate
task
automatic
pulse
(
int
out
,
int
polarity
,
int
cont
,
real
delta
,
int
tr_force
=
0
)
;
uint64_t
rv
;
int
coarse_par
=
int
'
($
floor
(
delta
/
16.0
))
;
int
coarse_ser
=
int
'
($
floor
(
delta
/
1.0
)
-
coarse_par
*
16
)
;
int
fine
=
int
'
((
delta
/
1.0
-
$
floor
(
delta
/
1.0
))
*
1.0
/
m_delay_tap_size
)
;
int
mask
=
coarse_ser
;
uint32_t
ocr
;
$
display
(
"Tapsize %.5f Fine %d"
,
m_delay_tap_size
,
fine
)
;
ocr
=
(
coarse_par
<<
`FPG_OCR0_PPS_OFFS_OFFSET
)
|
(
mask
<<
`FPG_OCR0_MASK_OFFSET
)
|
(
fine
<<
`FPG_OCR0_FINE_OFFSET
)
|
(
cont
?
`FPG_OCR0_CONT
:
0
)
|
(
polarity
?
`FPG_OCR0_POL
:
0
)
;
m_acc
.
write
(
m_base
+
`ADDR_FPG_OCR0
+
4
*
out
,
ocr
)
;
if
(
tr_force
)
m_acc
.
write
(
m_base
+
`ADDR_FPG_CSR
,
1
<<
(
6
+
out
)
)
;
else
m_acc
.
write
(
m_base
+
`ADDR_FPG_CSR
,
1
<<
(
out
)
)
;
// $display("triggered");
forever
begin
m_acc
.
read
(
m_base
+
`ADDR_FPG_CSR
,
rv
)
;
if
(
rv
&
(
1
<<
(
`FPG_CSR_READY_OFFSET
+
out
)
)
)
break
;
end
endtask
endclass
// FinePulseGenDriver
module
main
;
reg
rst_n
=
0
;
reg
clk_125m
=
0
;
reg
clk_250m
=
0
;
reg
clk_62m5
=
0
;
reg
clk_dmtd
=
0
;
always
#
2
ns
clk_250m
<=
~
clk_250m
;
always
@
(
posedge
clk_250m
)
clk_125m
<=
~
clk_125m
;
always
#(
7.9
ns
)
clk_dmtd
<=
~
clk_dmtd
;
always
@
(
posedge
clk_125m
)
clk_62m5
<=
~
clk_62m5
;
initial
begin
repeat
(
20
)
@
(
posedge
clk_125m
)
;
rst_n
=
1
;
end
wire
loop_p
,
loop_n
;
reg
pps_p
=
0
;
initial
forever
begin
repeat
(
100
)
@
(
posedge
clk_62m5
)
;
pps_p
<=
1
;
@
(
posedge
clk_62m5
)
;
pps_p
<=
0
;
end
time
t_pps
,
t_pulse
;
real
dlys
[$]
;
time
first_delay
=
0
;
time
delta_prev
=
0
,
delta
;
int
t_pps_valid
=
0
;
always
@
(
posedge
pps_p
)
begin
t_pps
=
$
time
;
t_pps_valid
=
1
;
end
always
@
(
posedge
DUT
.
pulse_o
[
0
])
begin
t_pulse
=
$
time
;
if
(
dlys
.
size
()
&&
t_pps_valid
)
begin
automatic
real
t_req
=
dlys
.
pop_front
()
;
automatic
time
dly
=
t_pulse
-
t_pps
;
t_pps_valid
=
0
;
if
(
!
first_delay
)
first_delay
=
dly
;
$
display
(
"t_pps %t t_pulse %t delta %.2f"
,
t_pps
,
t_pulse
,
real
'
(
t_pulse
-
t_pps
)
/
real
'
(
1
ns
)
)
;
/* delta = dly-first_delay;
$display("delta: %-20d ps, ddelta : %-20d ps", delta, delta-delta_prev );
delta_prev = delta;*/
end
end
// the Device Under Test
xwb_fine_pulse_gen
#(
.
g_target_platform
(
"KintexUltrascale"
)
,
.
g_use_external_serdes_clock
(
0
)
,
.
g_num_channels
(
1
)
,
.
g_use_odelay
(
6'b1
)
)
DUT
(
.
rst_sys_n_i
(
rst_n
)
,
// .clk_ser_ext_i(clk_250m),
.
clk_sys_i
(
clk_62m5
)
,
.
clk_ref_i
(
clk_62m5
)
,
.
pps_p_i
(
pps_p
)
,
.
slave_i
(
Host
.
out
)
,
.
slave_o
(
Host
.
in
)
)
;
IVHDWishboneMaster
Host
(
.
clk_i
(
clk_62m5
)
,
.
rst_n_i
(
rst_n
))
;
initial
begin
real
t
;
CWishboneAccessor
acc
;
FinePulseGenDriver
drv
;
@
(
posedge
rst_n
)
;
@
(
posedge
clk_62m5
)
;
@
(
posedge
pps_p
)
;
#
1u
s
;
acc
=
Host
.
get_accessor
()
;
acc
.
set_mode
(
PIPELINED
)
;
drv
=
new
(
acc
,
0
)
;
drv
.
calibrate
()
;
/* -----\/----- EXCLUDED -----\/-----
drv.pulse(1, 0, 1, 100);
drv.pulse(4, 0, 0, 100, 1);
-----/\----- EXCLUDED -----/\----- */
for
(
t
=
1.0
;
t
<=
200.9
;
t
+=
0.1
)
begin
$
display
(
"Pulse @ %f"
,
t
)
;
dlys
.
push_back
(
t
)
;
drv
.
pulse
(
0
,
1
,
0
,
t
)
;
end
#
1u
s
;
end
// initial begin
endmodule
// main
testbench/wishbone/wb_fine_pulse_gen/run.do
0 → 100644
View file @
8649d40d
#vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../include/vme64x_bfm +incdir+../../include +incdir+../include +incdir+../../sim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
vsim -modelsimini /home/twl/eda/modelsim-lib-2016.4/modelsim.ini -L unisim -L secureip -L XilinxCoreLib work.main work.glbl -voptargs=+acc -t 10fs
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 15us
wave zoomfull
\ No newline at end of file
testbench/wishbone/wb_spi/Manifest.py
0 → 100644
View file @
8649d40d
action
=
"simulation"
target
=
"generic"
sim_top
=
"tb_spi"
sim_tool
=
"modelsim"
modules
=
{
"local"
:
[
"../../../"
,
"../../../sim/vhdl"
]
};
files
=
[
"tb_spi.vhd"
]
testbench/wishbone/wb_spi/run.do
0 → 100644
View file @
8649d40d
vsim -t 1ps -voptargs="+acc" -lib work work.tb_spi
radix -hexadecimal
#add wave *
#do wave.do
run 400ns
#wave zoomfull
testbench/wishbone/wb_spi/tb_spi.vhd
0 → 100644
View file @
8649d40d
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
sim_wishbone
.
all
;
entity
tb_spi
is
end
tb_spi
;
architecture
behav
of
tb_spi
is
signal
clk_sys
:
std_logic
:
=
'0'
;
signal
rst_n
:
std_logic
;
signal
wb_in
:
t_wishbone_slave_in
;
signal
wb_out
:
t_wishbone_slave_out
;
signal
int
:
std_logic
;
signal
pad_cs
:
std_logic_vector
(
4-1
downto
0
);
signal
pad_sclk
:
std_logic
;
signal
pad_mosi
:
std_logic
;
signal
pad_miso
:
std_logic
;
begin
xwb_spi_1
:
entity
work
.
xwb_spi
generic
map
(
g_interface_mode
=>
CLASSIC
,
g_address_granularity
=>
BYTE
,
g_divider_len
=>
8
,
g_max_char_len
=>
128
,
g_num_slaves
=>
4
)
port
map
(
clk_sys_i
=>
clk_sys
,
rst_n_i
=>
rst_n
,
slave_i
=>
wb_in
,
slave_o
=>
wb_out
,
desc_o
=>
open
,
int_o
=>
int
,
pad_cs_o
=>
pad_cs
,
pad_sclk_o
=>
pad_sclk
,
pad_mosi_o
=>
pad_mosi
,
pad_miso_i
=>
pad_miso
);
clk_sys
<=
not
clk_sys
after
5
ns
;
rst_n
<=
'0'
,
'1'
after
20
ns
;
pad_miso
<=
pad_mosi
;
process
variable
v
:
std_logic_vector
(
31
downto
0
);
begin
init
(
wb_in
);
wait
until
rst_n
=
'1'
;
wait
until
rising_edge
(
clk_sys
);
-- Set divider to 2
write32
(
clk_sys
,
wb_in
,
wb_out
,
x"0000_0014"
,
x"0000_0002"
);
-- Set control
write32
(
clk_sys
,
wb_in
,
wb_out
,
x"0000_0010"
,
x"0000_2408"
);
-- Set data
write32
(
clk_sys
,
wb_in
,
wb_out
,
x"0000_0000"
,
x"0000_008d"
);
-- Set CS
write32
(
clk_sys
,
wb_in
,
wb_out
,
x"0000_0018"
,
x"0000_0001"
);
-- Go
write32
(
clk_sys
,
wb_in
,
wb_out
,
x"0000_0010"
,
x"0000_2508"
);
loop
read32
(
clk_sys
,
wb_in
,
wb_out
,
x"0000_0010"
,
v
);
exit
when
v
(
8
)
=
'0'
;
end
loop
;
wait
;
end
process
;
end
behav
;
testbench/wishbone/wb_uart/Manifest.py
0 → 100644
View file @
8649d40d
sim_tool
=
"modelsim"
top_module
=
"main"
action
=
"simulation"
target
=
"xilinx"
fetchto
=
"../../ip_cores"
vcom_opt
=
"-mixedsvvh l -2008"
sim_top
=
"main"
syn_device
=
"xc7k70t"
include_dirs
=
[
"../../../sim"
,
"../include"
]
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../../../"
]
}
testbench/wishbone/wb_uart/main.sv
0 → 100644
View file @
8649d40d
//------------------------------------------------------------------------------
// Copyright CERN 2018
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale
1
ps
/
1
ps
`include
"vhd_wishbone_master.svh"
`include
"wb_uart_regs.vh"
import
wishbone_pkg
::*;
module
dupa
;
xwb_simple_uart
dut
()
;
endmodule
// dupa
class
IBusDevice
;
CBusAccessor
m_acc
;
uint64_t
m_base
;
function
new
(
CBusAccessor
acc
,
uint64_t
base
)
;
m_acc
=
acc
;
m_base
=
base
;
endfunction
// new
virtual
task
write32
(
uint32_t
addr
,
uint32_t
val
)
;
m_acc
.
write
(
m_base
+
addr
,
val
)
;
endtask
// write
virtual
task
read32
(
uint32_t
addr
,
output
uint32_t
val
)
;
uint64_t
val64
;
m_acc
.
read
(
m_base
+
addr
,
val64
)
;
val
=
val64
;
endtask
// write
endclass
// BusDevice
class
WBUartDriver
extends
IBusDevice
;
function
new
(
CBusAccessor
bus
,
uint64_t
base
)
;
super
.
new
(
bus
,
base
)
;
endfunction
// new
protected
bit
m_with_fifo
;
protected
byte
m_tx_queue
[$]
;
protected
byte
m_rx_queue
[$]
;
protected
bit
m_tx_idle
;
function
automatic
uint32_t
calc_baudrate
(
uint64_t
baudrate
,
uint64_t
base_clock
)
;
return
(
(((
baudrate
<<
12
))
+
(
base_clock
>>
8
))
/
(
base_clock
>>
7
)
)
;
endfunction
task
automatic
init
(
uint32_t
baudrate
,
uint32_t
clock_freq
,
int
fifo_en
)
;
uint32_t
rv
;
read32
(
`ADDR_UART_SR
,
rv
)
;
write32
(
`ADDR_UART_BCR
,
calc_baudrate
(
baudrate
,
clock_freq
)
)
;
if
(
!
fifo_en
)
m_with_fifo
=
0
;
else
m_with_fifo
=
(
rv
&
`UART_SR_RX_FIFO_SUPPORTED
)
?
1
:
0
;
m_tx_idle
=
0
;
$
display
(
"wb_simple_uart: FIFO supported = %d"
,
m_with_fifo
)
;
endtask
// init
task
automatic
send
(
byte
value
)
;
m_tx_queue
.
push_back
(
value
)
;
m_tx_idle
=
0
;
update
()
;
endtask
// send
function
automatic
byte
recv
()
;
if
(
rx_count
()
==
0
)
return
-
1
;
return
m_rx_queue
.
pop_front
()
;
endfunction
// recv
function
automatic
int
rx_count
()
;
return
m_rx_queue
.
size
()
;
endfunction
// rx_count
function
automatic
bit
poll
()
;
return
m_rx_queue
.
size
()
>
0
;
endfunction
// has_data
function
automatic
bit
tx_idle
()
;
return
m_tx_idle
;
endfunction
// tx_idle
function
automatic
bit
rx_overflow
()
;
endfunction
// rx_overflow
task
automatic
update
()
;
automatic
uint32_t
sr
;
automatic
time
ts
=
$
time
;
read32
(
`ADDR_UART_SR
,
sr
)
;
if
(
m_with_fifo
)
begin
if
(
sr
&
`UART_SR_RX_RDY
)
begin
automatic
uint32_t
d
;
read32
(
`ADDR_UART_RDR
,
d
)
;
// $display("FifoRx: %x", d);
m_rx_queue
.
push_back
(
d
)
;
end
if
(
!
(
sr
&
`UART_SR_TX_FIFO_FULL
)
&&
m_tx_queue
.
size
()
>
0
)
begin
byte
d
=
m_tx_queue
.
pop_front
()
;
// $display("-> FifoTX %x", d);
write32
(
`ADDR_UART_TDR
,
d
)
;
end
else
if
(
!
m_tx_queue
.
size
()
)
begin
m_tx_idle
=
1
;
end
end
else
begin
if
(
!
(
sr
&
`UART_SR_TX_BUSY
)
&&
m_tx_queue
.
size
()
>
0
)
begin
byte
d
=
m_tx_queue
.
pop_front
()
;
// $display("NoFifoTX");
write32
(
`ADDR_UART_TDR
,
d
)
;
end
else
if
(
!
m_tx_queue
.
size
()
)
begin
m_tx_idle
=
1
;
end
if
(
sr
&
`UART_SR_RX_RDY
)
begin
automatic
uint32_t
d
;
read32
(
`ADDR_UART_RDR
,
d
)
;
// $display("NoFifoRx: %x", d);
m_rx_queue
.
push_back
(
d
)
;
end
end
endtask
// update
endclass
// WBUartDriver
module
main
;
reg
rst_n
=
0
;
reg
clk_62m5
=
0
;
always
#
8
ns
clk_62m5
<=
~
clk_62m5
;
initial
begin
repeat
(
20
)
@
(
posedge
clk_62m5
)
;
rst_n
=
1
;
end
// the Device Under Test
xwb_simple_uart
#(
.
g_WITH_PHYSICAL_UART
(
1'b1
)
,
.
g_WITH_PHYSICAL_UART_FIFO
(
1'b1
)
,
.
g_TX_FIFO_SIZE
(
64
)
,
.
g_RX_FIFO_SIZE
(
64
)
,
.
g_INTERFACE_MODE
(
PIPELINED
)
,
.
g_ADDRESS_GRANULARITY
(
0
)
)
DUT_FIFO
(
.
rst_n_i
(
rst_n
)
,
.
clk_sys_i
(
clk_62m5
)
,
.
slave_i
(
Host1
.
out
)
,
.
slave_o
(
Host1
.
in
)
,
.
uart_txd_o
(
txd
)
,
.
uart_rxd_i
(
rxd
)
)
;
// the Device Under Test
xwb_simple_uart
#(
.
g_WITH_PHYSICAL_UART
(
1'b1
)
,
.
g_WITH_PHYSICAL_UART_FIFO
(
1'b0
)
,
.
g_INTERFACE_MODE
(
PIPELINED
)
,
.
g_ADDRESS_GRANULARITY
(
0
)
)
DUT_NO_FIFO
(
.
rst_n_i
(
rst_n
)
,
.
clk_sys_i
(
clk_62m5
)
,
.
slave_i
(
Host2
.
out
)
,
.
slave_o
(
Host2
.
in
)
,
.
uart_txd_o
(
rxd
)
,
.
uart_rxd_i
(
txd
)
)
;
IVHDWishboneMaster
Host1
(
.
clk_i
(
clk_62m5
)
,
.
rst_n_i
(
rst_n
))
;
IVHDWishboneMaster
Host2
(
.
clk_i
(
clk_62m5
)
,
.
rst_n_i
(
rst_n
))
;
initial
begin
real
t
;
automatic
CWishboneAccessor
acc1
=
Host1
.
get_accessor
()
;
automatic
WBUartDriver
drv_fifo
=
new
(
acc1
,
0
)
;
automatic
CWishboneAccessor
acc2
=
Host2
.
get_accessor
()
;
automatic
WBUartDriver
drv_no_fifo
=
new
(
acc2
,
0
)
;
automatic
int
i
;
acc1
.
set_mode
(
PIPELINED
)
;
acc2
.
set_mode
(
PIPELINED
)
;
#
100
ns
;
// $stop;
@
(
posedge
rst_n
)
;
@
(
posedge
clk_62m5
)
;
drv_fifo
.
init
(
9216000
,
62500000
,
0
)
;
drv_no_fifo
.
init
(
9216000
,
62500000
,
0
)
;
#
1u
s
;
for
(
i
=
0
;
i
<
100
;
i
++
)
begin
drv_no_fifo
.
send
(
i
)
;
drv_fifo
.
send
(
i
)
;
drv_no_fifo
.
update
()
;
drv_fifo
.
update
()
;
end
forever
begin
// $display("%d %d", drv_fifo.tx_idle(), drv_no_fifo.tx_idle() );
drv_fifo
.
update
()
;
drv_no_fifo
.
update
()
;
if
(
drv_fifo
.
tx_idle
()
&&
drv_no_fifo
.
tx_idle
()
)
break
;
end
$
display
(
"TX Complete"
)
;
for
(
i
=
0
;
i
<
500
;
i
++
)
begin
drv_fifo
.
update
()
;
drv_no_fifo
.
update
()
;
end
$
display
(
"TX Idle!"
)
;
for
(
i
=
0
;
i
<
100
;
i
++
)
begin
automatic
int
rx
=
drv_no_fifo
.
recv
()
;
if
(
rx
!=
i
)
$
error
(
"NoFifo err %x vs %x"
,
i
,
rx
)
;
rx
=
drv_fifo
.
recv
()
;
if
(
rx
!=
i
)
$
error
(
"Fifo err %x vs %x"
,
i
,
rx
)
;
end
$
display
(
"Test complete"
)
;
$
stop
;
end
// initial begin
endmodule
// main
testbench/wishbone/wb_uart/run.do
0 → 100644
View file @
8649d40d
#vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../include/vme64x_bfm +incdir+../../include +incdir+../include +incdir+../../sim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
vsim -L unisim -L XilinxCoreLib work.main -voptargs=+acc -t 10fs
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 10ms
\ No newline at end of file
testbench/wishbone/wb_uart/wave.do
0 → 100644
View file @
8649d40d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/clk_sys_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rst_n_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_adr_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_dat_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_dat_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_cyc_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_sel_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_stb_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_we_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_ack_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_stall_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/int_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/uart_rxd_i
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/uart_txd_o
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_ready_reg
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_ready
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/uart_bcr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rdr_rack
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/host_rack
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/baud_tick
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/baud_tick8
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/resized_addr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_in
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/wb_out
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/regs_in
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/regs_out
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_empty
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_full
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_rd
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_wr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/vuart_fifo_count
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_empty
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_full
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_rd
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_wr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_count
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_reset_n
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_empty
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_full
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_overflow
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_rd
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_wr
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_count
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/rx_fifo_reset_n
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_rx_ready
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_tx_busy
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_tx_start
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_rx_data
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/phys_tx_data
add wave -noupdate -group UartFifo /main/DUT_FIFO/U_Wrapped_UART/tx_fifo_state
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/rst_n_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/clk_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/d_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/we_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/q_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/rd_i
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/empty_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/full_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/almost_empty_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/almost_full_o
add wave -noupdate -group TXFIFO /main/DUT_FIFO/U_Wrapped_UART/gen_phys_fifos/U_UART_TX_FIFO/count_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/clk_sys_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rst_n_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_adr_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_dat_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_dat_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_cyc_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_sel_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_stb_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_we_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_ack_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_stall_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/int_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/uart_rxd_i
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/uart_txd_o
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_ready_reg
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_ready
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/uart_bcr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rdr_rack
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/host_rack
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/baud_tick
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/baud_tick8
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/resized_addr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_in
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/wb_out
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/regs_in
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/regs_out
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_empty
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_full
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_rd
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_wr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/vuart_fifo_count
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_empty
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_full
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_rd
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_wr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_count
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_reset_n
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_empty
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_full
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_overflow
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_rd
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_wr
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_count
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/rx_fifo_reset_n
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_rx_ready
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_tx_busy
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_tx_start
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_rx_data
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/phys_tx_data
add wave -noupdate -expand -group UartNoFifo /main/DUT_NO_FIFO/U_Wrapped_UART/tx_fifo_state
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {12968000000 fs} 0}
configure wave -namecolwidth 298
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {109552789280 fs}
tools/gen_sourceid.py
View file @
8649d40d
...
...
@@ -11,7 +11,7 @@ with open("sourceid_{}_pkg.vhd".format(project), "w") as f:
[
"git"
,
"log"
,
"-1"
,
"--format=
%
H"
])
.
decode
()
.
strip
()
sourceid
=
sourceid
[
0
:
32
]
except
:
commit
id
=
16
*
"00"
source
id
=
16
*
"00"
# Extract current tag + dirty indicator.
# It is not sure if the definition of dirty is stable across all git versions.
...
...
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