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Commit 632dab24 authored by A. Hahn's avatar A. Hahn
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gsi_pexaria2a: removed unmaintained device

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syn/gsi_pexaria2a/wishbone_demo/Manifest.py deleted 100644 → 0
View file @ 45b7e8ea
target = "altera"
action = "synthesis"
#syn_device = "xc6slx45t"
#syn_grade = "-3"
#syn_package = "fgg484"
syn_top = "wishbone_demo"
syn_project = "wishbone_demo.qpf"
modules = {
"local" : [ "../../../top/gsi_pexaria2a/wishbone_demo" ]
}
syn/gsi_pexaria2a/wishbone_demo/wishbone_demo.qpf deleted 100644 → 0
View file @ 45b7e8ea
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
# Date created = 12:33:22 May 18, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "12:33:22 May 18, 2012"
# Revisions
PROJECT_REVISION = "wishbone_demo"
syn/gsi_pexaria2a/wishbone_demo/wishbone_demo.qsf deleted 100644 → 0
View file @ 45b7e8ea
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
# Date created = 12:33:22 May 18, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# wishbone_demo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Arria II GX"
set_global_assignment -name DEVICE EP2AGX125DF25C6ES
set_global_assignment -name TOP_LEVEL_ENTITY wishbone_demo_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:33:22 MAY 18, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_U23 -to pcie_refclk_i
set_location_assignment PIN_W1 -to pcie_rstn_i
set_location_assignment PIN_N23 -to pcie_rx_i[3]
set_location_assignment PIN_R23 -to pcie_rx_i[2]
set_location_assignment PIN_W23 -to pcie_rx_i[1]
set_location_assignment PIN_AA23 -to pcie_rx_i[0]
set_location_assignment PIN_M21 -to pcie_tx_o[3]
set_location_assignment PIN_P21 -to pcie_tx_o[2]
set_location_assignment PIN_V21 -to pcie_tx_o[1]
set_location_assignment PIN_Y21 -to pcie_tx_o[0]
set_location_assignment PIN_U9 -to leds_o[0]
set_location_assignment PIN_V9 -to leds_o[1]
set_location_assignment PIN_AA7 -to leds_o[2]
set_location_assignment PIN_AB7 -to leds_o[3]
set_location_assignment PIN_W9 -to leds_o[4]
set_location_assignment PIN_W10 -to leds_o[5]
set_location_assignment PIN_AA10 -to leds_o[6]
set_location_assignment PIN_AB10 -to leds_o[7]
set_location_assignment PIN_D11 -to clk125_i
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2]
set_location_assignment PIN_R24 -to "pcie_rx_i[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1]
set_location_assignment PIN_W24 -to "pcie_rx_i[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0]
set_location_assignment PIN_AA24 -to "pcie_rx_i[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3]
set_location_assignment PIN_M22 -to "pcie_tx_o[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2]
set_location_assignment PIN_P22 -to "pcie_tx_o[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1]
set_location_assignment PIN_V22 -to "pcie_tx_o[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0]
set_location_assignment PIN_Y22 -to "pcie_tx_o[0](n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pcie_rstn_i
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
set_instance_assignment -name IO_STANDARD LVDS -to clk125_i
set_location_assignment PIN_C11 -to "clk125_i(n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[0]
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_JAM_FILE ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name SDC_FILE ../../../top/gsi_pexaria2a/wishbone_demo/wishbone_demo.sdc
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
set_global_assignment -name QIP_FILE ../../../modules/wishbone/wb_pcie/altera_pcie.qip
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_pcie.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_pcie_core.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_pcie_serdes.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_reconfig.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_dma/xwb_dma.vhd
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/platform/altera/jtag_tap.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_shifter.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_ram.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_logic_op.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_dp_ram.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_addsub.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_adder.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/jtag_cores.v
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
set_global_assignment -name VERILOG_FILE ../../../modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_crossbar/xwb_crossbar.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_crossbar/sdb_rom.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_dpram/xwb_dpram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wishbone_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_sync_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_spram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_dpram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/altera/generic_async_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/genrams/generic_shiftreg_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_wfifo.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_dual_clock_ram.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_sync_ffs.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_reset.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_dual_pi_controller.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_delay_gen.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_extend_pulse.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_moving_average.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_crc_gen.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gencores_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_pexaria2a/wishbone_demo/sys_pll.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_pexaria2a/wishbone_demo/wishbone_demo_top.vhd
set_global_assignment -name QIP_FILE ../../../top/gsi_pexaria2a/wishbone_demo/sys_pll.qip
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
top/gsi_pexaria2a/wishbone_demo/Manifest.py deleted 100644 → 0
View file @ 45b7e8ea
files = ["wishbone_demo_top.vhd", "sys_pll.vhd"]
modules = {
"local" : ["../../../" ]
}
top/gsi_pexaria2a/wishbone_demo/sys_pll.vhd deleted 100644 → 0
View file @ 45b7e8ea
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: sys_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sys_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END sys_pll;
ARCHITECTURE SYN OF sys_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 25,
clk0_duty_cycle => 50,
clk0_multiply_by => 26,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Arria II GX",
lpm_hint => "CBX_MODULE_PREFIX=sys_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "Left_Right",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
using_fbmimicbidir_port => "OFF",
width_clock => 7
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "130.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "26"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "135.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "26"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
-- Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
top/gsi_pexaria2a/wishbone_demo/wishbone_demo.sdc deleted 100644 → 0
View file @ 45b7e8ea
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous \
-group { PCIe|* } \
-group { clk125_i sys_pll_inst|*|clk[1] } \
-group { sys_pll_inst|*|clk[0] }
top/gsi_pexaria2a/wishbone_demo/wishbone_demo_top.vhd deleted 100644 → 0
View file @ 45b7e8ea
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.pcie_wb_pkg.all;
use work.gencores_pkg.all;
entity wishbone_demo_top is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
clk125_i : in std_logic;
-----------------------------------------
-- PCI express pins
-----------------------------------------
pcie_refclk_i : in std_logic;
pcie_rstn_i : in std_logic;
pcie_rx_i : in std_logic_vector(3 downto 0);
pcie_tx_o : out std_logic_vector(3 downto 0);
-----------------------------------------------------------------------
-- User LEDs
-----------------------------------------------------------------------
leds_o : out std_logic_vector(7 downto 0));
end wishbone_demo_top;
architecture rtl of wishbone_demo_top is
component sys_pll -- Altera megafunction
port(
inclk0 : in std_logic;
areset : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
locked : out std_logic);
end component;
constant c_xwb_gpio32_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000007", -- Two 4 byte registers
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"35aa6b95",
version => x"00000001",
date => x"20120305",
name => "GSI_GPIO_32 ")));
-- Top crossbar layout
constant c_slaves : natural := 3;
constant c_masters : natural := 5;
constant c_dpram_size : natural := 16384; -- in 32-bit words (64KB)
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"),
1 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"00100400"),
2 => f_sdb_embed_device(c_xwb_dma_sdb, x"00100500"));
constant c_sdb_address : t_wishbone_address := x"00100000";
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
signal clk_sys, clk_cal : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
signal gpio_slave_o : t_wishbone_slave_out;
signal gpio_slave_i : t_wishbone_slave_in;
signal r_leds : std_logic_vector(7 downto 0);
signal r_reset : std_logic;
begin
-- Obtain core clocking
sys_pll_inst : sys_pll -- Altera megafunction
port map (
inclk0 => clk125_i, -- 125Mhz oscillator from board
areset => '0',
c0 => clk_sys, -- 130MHz system clk (to test clock crossing from clk125_i)
c1 => clk_cal, -- 50Mhz calibration clock for Altera reconfig cores
locked => locked); -- '1' when the PLL has locked
reset : gc_reset
port map(
free_clk_i => clk125_i,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0);
-- The top-most Wishbone B.4 crossbar
interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o);
-- Master 0 is the PCIe bridge
PCIe : pcie_wb
generic map(
sdb_addr => c_sdb_address)
port map(
clk125_i => clk125_i, -- Free running clock
cal_clk50_i => clk_cal, -- Transceiver global calibration clock
pcie_refclk_i => pcie_refclk_i, -- External PCIe 100MHz bus clock
pcie_rstn_i => pcie_rstn_i, -- External PCIe system reset pin
pcie_rx_i => pcie_rx_i,
pcie_tx_o => pcie_tx_o,
wb_clk => clk_sys, -- Desired clock for the WB bus
wb_rstn_i => clk_sys_rstn,
master_o => cbar_slave_i(0),
master_i => cbar_slave_o(0));
-- The LM32 is master 1+2
lm32_rstn <= clk_sys_rstn and not r_reset;
LM32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug") -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(1), -- Data bus
dwb_i => cbar_slave_o(1),
iwb_o => cbar_slave_i(2), -- Instruction bus
iwb_i => cbar_slave_o(2));
-- The other 31 interrupt pins are unconnected
lm32_interrupt(31 downto 1) <= (others => '0');
-- A DMA controller is master 3+4, slave 2, and interrupt 0
dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
r_master_i => cbar_slave_o(3),
r_master_o => cbar_slave_i(3),
w_master_i => cbar_slave_o(4),
w_master_o => cbar_slave_i(4),
interrupt_o => lm32_interrupt(0));
-- Slave 0 is the RAM
ram : xwb_dpram
generic map(
g_size => c_dpram_size,
g_slave1_interface_mode => PIPELINED, -- Why isn't this the default?!
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => WORD)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port disconnected
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open);
-- Slave 1 is the example LED driver
gpio_slave_i <= cbar_master_o(1);
cbar_master_i(1) <= gpio_slave_o;
leds_o <= not r_leds;
-- There is a tool called 'wbgen2' which can autogenerate a Wishbone
-- interface and C header file, but this is a simple example.
gpio : process(clk_sys)
begin
if rising_edge(clk_sys) then
-- It is vitally important that for each occurance of
-- (cyc and stb and not stall) there is (ack or rty or err)
-- sometime later on the bus.
--
-- This is an easy solution for a device that never stalls:
gpio_slave_o.ack <= gpio_slave_i.cyc and gpio_slave_i.stb;
-- Detect a write to the register byte
if gpio_slave_i.cyc = '1' and gpio_slave_i.stb = '1' and
gpio_slave_i.we = '1' and gpio_slave_i.sel(0) = '1' then
-- Register 0x0 = LEDs, 0x4 = CPU reset
if gpio_slave_i.adr(2) = '0' then
r_leds <= gpio_slave_i.dat(7 downto 0);
else
r_reset <= gpio_slave_i.dat(0);
end if;
end if;
if gpio_slave_i.adr(2) = '0' then
gpio_slave_o.dat(31 downto 8) <= (others => '0');
gpio_slave_o.dat(7 downto 0) <= r_leds;
else
gpio_slave_o.dat(31 downto 2) <= (others => '0');
gpio_slave_o.dat(0) <= r_reset;
end if;
end if;
end process;
gpio_slave_o.err <= '0';
gpio_slave_o.rty <= '0';
gpio_slave_o.stall <= '0'; -- This simple example is always ready
end rtl;
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