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Platform-independent core collection
Commit 380cde1d authored by Dimitris Lampridis's avatar Dimitris Lampridis
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wb_uart: code cleanup

parent a993f050
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modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 380cde1d
......@@ -16,7 +16,7 @@
-- records, see xwb_simple_uart.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2010-2018
-- Copyright CERN 2010-2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -38,11 +38,11 @@ use work.UART_wbgen2_pkg.all;
entity wb_simple_uart is
generic(
g_with_virtual_uart : boolean;
g_with_physical_uart : boolean;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024
g_WITH_VIRTUAL_UART : boolean;
g_WITH_PHYSICAL_UART : boolean;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024
);
port (
......@@ -59,81 +59,28 @@ entity wb_simple_uart is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
int_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
);
end wb_simple_uart;
architecture syn of wb_simple_uart is
constant c_baud_acc_width : integer := 16;
component uart_baud_gen
generic (
g_baud_acc_width : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baudrate_i : in std_logic_vector(g_baud_acc_width downto 0);
baud_tick_o : out std_logic;
baud8_tick_o : out std_logic);
end component;
component uart_async_rx
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud8_tick_i : in std_logic;
rxd_i : in std_logic;
rx_ready_o : out std_logic;
rx_error_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0));
end component;
component uart_async_tx
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud_tick_i : in std_logic;
txd_o : out std_logic;
tx_start_p_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_busy_o : out std_logic);
end component;
component simple_uart_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers
);
end component;
architecture arch of wb_simple_uart is
constant c_BAUD_ACC_WIDTH : integer := 16;
signal rx_ready_reg : std_logic;
signal rx_ready : std_logic;
signal uart_bcr : std_logic_vector(31 downto 0);
signal rx_ready_reg : std_logic;
signal rx_ready : std_logic;
signal uart_bcr : std_logic_vector(31 downto 0);
signal rdr_rack : std_logic;
signal rdr_rack : std_logic;
signal host_rack : std_logic;
signal baud_tick : std_logic;
signal baud_tick8 : std_logic;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal resized_addr : std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0);
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
......@@ -141,31 +88,36 @@ architecture syn of wb_simple_uart is
signal regs_in : t_UART_in_registers;
signal regs_out : t_UART_out_registers;
signal fifo_empty, fifo_full, fifo_rd, fifo_wr : std_logic;
signal fifo_count : std_logic_vector(f_log2_size(g_vuart_fifo_size)-1 downto 0);
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_rd : std_logic;
signal fifo_wr : std_logic;
signal fifo_count : std_logic_vector(f_log2_size(g_VUART_FIFO_SIZE)-1 downto 0);
signal phys_rx_ready, phys_tx_busy : std_logic;
signal phys_rx_data : std_logic_vector(7 downto 0);
begin -- syn
gen_check_generics : if(not g_with_physical_uart and not g_with_virtual_uart) generate
assert false report "wb_simple_uart: dummy configuration (use virtual, physical or both uarts)" severity failure;
begin -- arch
gen_check_generics : if (not g_WITH_PHYSICAL_UART and not g_WITH_VIRTUAL_UART) generate
assert FALSE report
"wb_simple_uart: dummy configuration (use virtual, physical or both uarts)"
severity FAILURE;
end generate gen_check_generics;
resized_addr(4 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
resized_addr(c_WISHBONE_ADDRESS_WIDTH-1 downto 5) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
g_MASTER_USE_STRUCT => TRUE,
g_MASTER_MODE => CLASSIC,
g_MASTER_GRANULARITY => WORD,
g_SLAVE_USE_STRUCT => FALSE,
g_SLAVE_MODE => g_INTERFACE_MODE,
g_SLAVE_GRANULARITY => g_ADDRESS_GRANULARITY)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -181,7 +133,7 @@ begin -- syn
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
U_WB_SLAVE : simple_uart_wb
U_WB_SLAVE : entity work.simple_uart_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......@@ -203,30 +155,30 @@ begin -- syn
wb_out.err <= '0';
wb_out.rty <= '0';
gen_phys_uart : if(g_with_physical_uart) generate
gen_phys_uart : if (g_WITH_PHYSICAL_UART) generate
p_bcr_reg : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
uart_bcr <= (others => '0');
elsif(regs_out.bcr_wr_o = '1')then
elsif regs_out.bcr_wr_o = '1' then
uart_bcr <= regs_out.bcr_o;
end if;
end if;
end process;
end process p_bcr_reg;
U_BAUD_GEN : uart_baud_gen
U_BAUD_GEN : entity work.uart_baud_gen
generic map (
g_baud_acc_width => c_baud_acc_width)
g_BAUD_ACC_WIDTH => c_BAUD_ACC_WIDTH)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
baudrate_i => uart_bcr(c_baud_acc_width downto 0),
baudrate_i => uart_bcr(c_BAUD_ACC_WIDTH downto 0),
baud_tick_o => baud_tick,
baud8_tick_o => baud_tick8);
U_TX : uart_async_tx
U_TX : entity work.uart_async_tx
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -236,7 +188,7 @@ begin -- syn
tx_data_i => regs_out.tdr_tx_data_o,
tx_busy_o => phys_tx_busy);
U_RX : uart_async_rx
U_RX : entity work.uart_async_rx
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -247,17 +199,17 @@ begin -- syn
rx_data_o => phys_rx_data);
end generate gen_phys_uart;
gen_vuart : if(g_with_virtual_uart) generate
gen_vuart : if (g_WITH_VIRTUAL_UART) generate
fifo_wr <= not fifo_full and regs_out.tdr_tx_data_wr_o;
fifo_rd <= not fifo_empty and not regs_in.host_rdr_rdy_i;
U_VUART_FIFO : generic_sync_fifo
generic map (
g_data_width => 8,
g_size => g_vuart_fifo_size,
g_with_count => true)
g_DATA_WIDTH => 8,
g_SIZE => g_VUART_FIFO_SIZE,
g_WITH_COUNT => TRUE)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
......@@ -269,7 +221,7 @@ begin -- syn
full_o => fifo_full,
count_o => fifo_count);
regs_in.host_rdr_count_i(fifo_count'left downto 0) <= fifo_count;
regs_in.host_rdr_count_i(fifo_count'LEFT downto 0) <= fifo_count;
regs_in.host_rdr_count_i(15 downto fifo_count'length) <= (others => '0');
p_vuart_rx_ready : process(clk_sys_i)
......@@ -277,47 +229,47 @@ begin -- syn
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_in.host_rdr_rdy_i <= '0';
elsif(fifo_rd = '1') then
elsif fifo_rd = '1' then
regs_in.host_rdr_rdy_i <= '1';
elsif(host_rack = '1') then
elsif host_rack = '1' then
regs_in.host_rdr_rdy_i <= '0';
end if;
end if;
end process;
end process p_vuart_rx_ready;
end generate gen_vuart;
dont_gen_vuart : if (not g_with_virtual_uart) generate
regs_in.host_rdr_data_i <= (others => '0');
gen_no_vuart : if (not g_WITH_VIRTUAL_UART) generate
regs_in.host_rdr_data_i <= (others => '0');
regs_in.host_rdr_count_i <= (others => '0');
regs_in.host_rdr_rdy_i <= '0';
end generate dont_gen_vuart;
regs_in.host_rdr_rdy_i <= '0';
end generate gen_no_vuart;
p_drive_rx_ready : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_in.sr_rx_rdy_i <= '0';
int_o <= '0';
int_o <= '0';
regs_in.rdr_rx_data_i <= (others => '0');
else
if(rdr_rack = '1' and phys_rx_ready = '0' and regs_out.host_tdr_data_wr_o = '0') then
if rdr_rack = '1' and phys_rx_ready = '0' and regs_out.host_tdr_data_wr_o = '0' then
regs_in.sr_rx_rdy_i <= '0';
int_o <= '0';
elsif(phys_rx_ready = '1' and g_with_physical_uart) then
int_o <= '0';
elsif phys_rx_ready = '1' and g_WITH_PHYSICAL_UART then
regs_in.sr_rx_rdy_i <= '1';
int_o <= '1';
int_o <= '1';
regs_in.rdr_rx_data_i <= phys_rx_data;
elsif(regs_out.host_tdr_data_wr_o = '1' and g_with_virtual_uart) then
elsif regs_out.host_tdr_data_wr_o = '1' and g_WITH_VIRTUAL_UART then
regs_in.sr_rx_rdy_i <= '1';
int_o <= '1';
int_o <= '1';
regs_in.rdr_rx_data_i <= regs_out.host_tdr_data_o;
end if;
end if;
end if;
end process;
end process p_drive_rx_ready;
regs_in.sr_tx_busy_i <= phys_tx_busy when (g_with_physical_uart) else '0';
regs_in.sr_tx_busy_i <= phys_tx_busy when (g_WITH_PHYSICAL_UART) else '0';
regs_in.host_tdr_rdy_i <= not regs_in.sr_rx_rdy_i;
end syn;
end arch;
modules/wishbone/wb_uart/xwb_simple_uart.vhd
View file @ 380cde1d
......@@ -16,7 +16,7 @@
-- wb_simple_uart.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2010-2018
-- Copyright CERN 2010-2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -36,15 +36,14 @@ library work;
use work.wishbone_pkg.all;
entity xwb_simple_uart is
generic(
g_with_virtual_uart : boolean := true;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024
);
generic (
g_WITH_VIRTUAL_UART : boolean := TRUE;
g_WITH_PHYSICAL_UART : boolean := TRUE;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024);
port(
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -54,48 +53,22 @@ entity xwb_simple_uart is
desc_o : out t_wishbone_device_descriptor;
int_o : out std_logic;
uart_rxd_i: in std_logic;
uart_txd_o: out std_logic
);
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic);
end xwb_simple_uart;
architecture rtl of xwb_simple_uart is
architecture arch of xwb_simple_uart is
component wb_simple_uart
generic (
g_with_virtual_uart : boolean;
g_with_physical_uart : boolean;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_vuart_fifo_size : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic);
end component;
begin -- rtl
begin -- arch
U_Wrapped_UART: wb_simple_uart
U_Wrapped_UART : entity work.wb_simple_uart
generic map (
g_with_virtual_uart => g_with_virtual_uart,
g_with_physical_uart => g_with_physical_uart,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_vuart_fifo_size => g_vuart_fifo_size)
g_WITH_VIRTUAL_UART => g_WITH_VIRTUAL_UART,
g_WITH_PHYSICAL_UART => g_WITH_PHYSICAL_UART,
g_INTERFACE_MODE => g_INTERFACE_MODE,
g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY,
g_VUART_FIFO_SIZE => g_VUART_FIFO_SIZE)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -116,5 +89,5 @@ begin -- rtl
slave_o.rty <= '0';
desc_o <= (others => '0');
end rtl;
end arch;
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