modules/wishbone/wb_i2c_master/i2c_master_top.vhd · 63f3671351127a398006e01f66b37adb7eda9a37 · Projects / Platform-independent core collection · Open Hardware Repository

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[hdl][wb_i2c_master] fix async reset logic · d7bf5216
Dimitris Lampridis authored Mar 05, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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d7bf5216

i2c_master_top.vhd 16.8 KB