sdb_address: add to the lm32 the generic for passing

the sdb address of the wb crossbar. The sdb address
is store in a CSR, 0xb, and it can be retrieved from the
firmware using an asm macro call.

modules/wishbone/wb_lm32/gen_lmcores.py

@@ -74,6 +74,7 @@ def gen_customized_version(profile_name, feats):
 			f.write("`define " + feat + "\n");
 
 	f.write("`define CFG_EBA_RESET  32'h00000000\n\
+	`define CFG_SDB  32'h00000000\n\
 	`define CFG_DEBA_RESET 32'h10000000\n\
 	`define CFG_EBR_POSEDGE_REGISTER_FILE\n\
 	`define CFG_ICACHE_ASSOCIATIVITY   1\n\
@@ -123,7 +124,8 @@ def parse_profiles():
 
 def gen_vhdl_component(f, profile_name):
 	f.write("component lm32_top_"+profile_name+" is \n")
-	f.write("generic ( eba_reset: std_logic_vector(31 downto 0) );\n");
+	f.write("generic ( eba_reset: std_logic_vector(31 downto 0);\n");
+	f.write("          sdb_address: std_logic_vector(31 downto 0));\n");
 	f.write("port (\n");
 	f.write(""" 
   clk_i    : in  std_logic;
@@ -177,7 +179,8 @@ use ieee.numeric_std.all;
 use work.wishbone_pkg.all;
 entity xwb_lm32 is
 generic(g_profile: string;
-g_reset_vector: std_logic_vector(31 downto 0) := x"00000000");
+g_reset_vector: std_logic_vector(31 downto 0) := x"00000000";
+g_sdb_address: std_logic_vector(31 downto 0) := x"00000000");
 port(
 clk_sys_i : in  std_logic;
 rst_n_i : in  std_logic;
@@ -263,7 +266,8 @@ begin
 		f.write("U_Wrapped_LM32: lm32_top_"+p[0]+"\n");
 		f.write("""
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,

modules/wishbone/wb_lm32/generated/xwb_lm32.vhd

@@ -5,7 +5,8 @@ use ieee.numeric_std.all;
 use work.wishbone_pkg.all;
 entity xwb_lm32 is
 generic(g_profile: string;
-g_reset_vector: std_logic_vector(31 downto 0) := x"00000000");
+g_reset_vector: std_logic_vector(31 downto 0) := x"00000000";
+g_sdb_address: std_logic_vector(31 downto 0) := x"00000000");
 port(
 clk_sys_i : in  std_logic;
 rst_n_i : in  std_logic;
@@ -39,7 +40,8 @@ if profile_name = "full_debug" then return 4; end if;
 return 0;
 end function;
 component lm32_top_minimal is 
-generic ( eba_reset: std_logic_vector(31 downto 0) );
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
 port (
  
   clk_i    : in  std_logic;
@@ -73,7 +75,8 @@ port (
    D_BTE_O  : out std_logic_vector(1 downto 0));
 end component;
 component lm32_top_medium is 
-generic ( eba_reset: std_logic_vector(31 downto 0) );
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
 port (
  
   clk_i    : in  std_logic;
@@ -107,7 +110,8 @@ port (
    D_BTE_O  : out std_logic_vector(1 downto 0));
 end component;
 component lm32_top_medium_icache is 
-generic ( eba_reset: std_logic_vector(31 downto 0) );
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
 port (
  
   clk_i    : in  std_logic;
@@ -141,7 +145,8 @@ port (
    D_BTE_O  : out std_logic_vector(1 downto 0));
 end component;
 component lm32_top_medium_debug is 
-generic ( eba_reset: std_logic_vector(31 downto 0) );
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
 port (
  
   clk_i    : in  std_logic;
@@ -175,7 +180,8 @@ port (
    D_BTE_O  : out std_logic_vector(1 downto 0));
 end component;
 component lm32_top_medium_icache_debug is 
-generic ( eba_reset: std_logic_vector(31 downto 0) );
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
 port (
  
   clk_i    : in  std_logic;
@@ -209,7 +215,8 @@ port (
    D_BTE_O  : out std_logic_vector(1 downto 0));
 end component;
 component lm32_top_full is 
-generic ( eba_reset: std_logic_vector(31 downto 0) );
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
 port (
  
   clk_i    : in  std_logic;
@@ -243,7 +250,8 @@ port (
    D_BTE_O  : out std_logic_vector(1 downto 0));
 end component;
 component lm32_top_full_debug is 
-generic ( eba_reset: std_logic_vector(31 downto 0) );
+generic ( eba_reset: std_logic_vector(31 downto 0);
+          sdb_address: std_logic_vector(31 downto 0));
 port (
  
   clk_i    : in  std_logic;
@@ -342,7 +350,8 @@ gen_profile_minimal: if (g_profile = "minimal") generate
 U_Wrapped_LM32: lm32_top_minimal
 
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,
@@ -385,7 +394,8 @@ gen_profile_medium: if (g_profile = "medium") generate
 U_Wrapped_LM32: lm32_top_medium
 
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,
@@ -428,7 +438,8 @@ gen_profile_medium_icache: if (g_profile = "medium_icache") generate
 U_Wrapped_LM32: lm32_top_medium_icache
 
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,
@@ -471,7 +482,8 @@ gen_profile_medium_debug: if (g_profile = "medium_debug") generate
 U_Wrapped_LM32: lm32_top_medium_debug
 
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,
@@ -514,7 +526,8 @@ gen_profile_medium_icache_debug: if (g_profile = "medium_icache_debug") generate
 U_Wrapped_LM32: lm32_top_medium_icache_debug
 
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,
@@ -557,7 +570,8 @@ gen_profile_full: if (g_profile = "full") generate
 U_Wrapped_LM32: lm32_top_full
 
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,
@@ -600,7 +614,8 @@ gen_profile_full_debug: if (g_profile = "full_debug") generate
 U_Wrapped_LM32: lm32_top_full_debug
 
 generic map (
-			eba_reset => g_reset_vector)
+			eba_reset => g_reset_vector,
+                        sdb_address => g_sdb_address)
 port map(
       clk_i	=> clk_sys_i,
       rst_i	=> rst,

modules/wishbone/wb_lm32/src/lm32_cpu.v

@@ -156,6 +156,7 @@ parameter eba_reset = `CFG_EBA_RESET;                           // Reset value f
 `ifdef CFG_DEBUG_ENABLED
 parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
 `endif
+parameter sdb_address =  `CFG_SDB;
 
 `ifdef CFG_ICACHE_ENABLED
 parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
@@ -2077,6 +2078,7 @@ begin
     `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
 `endif
     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
+    `LM32_CSR_SDB:  csr_read_data_x = sdb_address;
       
     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
     endcase

modules/wishbone/wb_lm32/src/lm32_include.v

@@ -202,6 +202,7 @@
 `define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
 `endif
 `define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
+`define LM32_CSR_SDB                    `LM32_CSR_WIDTH'hb
 `ifdef CFG_JTAG_ENABLED
 `define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
 `define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf

modules/wishbone/wb_lm32/src/lm32_top.v

@@ -90,6 +90,7 @@ module lm32_top (
     );
 
 parameter eba_reset = 32'h00000000;
+parameter sdb_address = 32'h00000000;
 /////////////////////////////////////////////////////
 // Inputs
 /////////////////////////////////////////////////////
@@ -213,7 +214,8 @@ wire trace_bret;                                // Indicates a bret instruction
 // LM32 CPU   
 lm32_cpu 
 	#(
-		.eba_reset(eba_reset)
+		.eba_reset(eba_reset),
+    .sdb_address(sdb_address)
 	) cpu (
     // ----- Inputs -------
     .clk_i                 (clk_i),

modules/wishbone/wishbone_pkg.vhd

@@ -583,7 +583,8 @@ package wishbone_pkg is
   component xwb_lm32
     generic (
       g_profile : string;
-      g_reset_vector : std_logic_vector(31 downto 0) := x"00000000");
+      g_reset_vector : std_logic_vector(31 downto 0) := x"00000000";
+      g_sdb_address  : std_logic_vector(31 downto 0) := x"00000000");
     port (
       clk_sys_i : in  std_logic;
       rst_n_i   : in  std_logic;