Commits · 7c570f1bc5654db77d8fa26a019896d0e1e0be17 · Projects / FSI Data Acquisition Path Gateware and Software

23 Sep, 2021 1 commit
- fsi_adc_top: adjust blinking led · 7c570f1b
  Tristan Gingold authored Sep 23, 2021
  
  7c570f1b
14 Sep, 2021 7 commits
- diot_sys_top: add a register to improve timing · 99b9f930
  Tristan Gingold authored Sep 14, 2021
  
  99b9f930
- diot_sys_top: set DIFF_TERM to true for LVDS · 1bd7cec9
  Tristan Gingold authored Sep 14, 2021
  
  1bd7cec9
- periph_adc_top: adjust constraints (async clocks) · dad96b76
  Tristan Gingold authored Sep 14, 2021
  
  dad96b76
- fsi: add a synchronizer, adjust constraints. · 4ce12b7a
  Tristan Gingold authored Sep 14, 2021
  
  4ce12b7a
- fsi_control: add a register on prbs · 9d0cc7c3
  Tristan Gingold authored Sep 14, 2021
  
  9d0cc7c3
- fsi: one PRBS per lane · de0e58ab
  Tristan Gingold authored Sep 14, 2021
  
  de0e58ab
- prbs: use a 31 bit polynome, reverse bit order to match serdes. · d17c41a4
  Tristan Gingold authored Sep 14, 2021
  
  d17c41a4
13 Sep, 2021 5 commits
- sys_fsi_core: connect clock · 0c76f5d9
  Tristan Gingold authored Sep 13, 2021
  
  0c76f5d9
- ads5295: adjust model · 590ea82b
  Tristan Gingold authored Sep 13, 2021
  
  590ea82b
- tb/periph_adc_tb: adjust · 38f349ba
  Tristan Gingold authored Sep 13, 2021
  
  38f349ba
- rtl: move and rename prbs_chk · 604c7faf
  Tristan Gingold authored Sep 13, 2021
  
  604c7faf
- sys: add prbs · 3ad1c5a2
  Tristan Gingold authored Sep 13, 2021
  
  3ad1c5a2
10 Sep, 2021 4 commits
- sys fsi: minor improvment (handle board sel one-off once) · 4b9e1065
  Tristan Gingold authored Sep 10, 2021
  
  4b9e1065
- sys: add parity check · ffba65ec
  Tristan Gingold authored Sep 10, 2021
  
  ffba65ec
- tb: add a tb for prbs · f27ec628
  Tristan Gingold authored Sep 10, 2021
  
  f27ec628
- fsi periph: add prbs generator + parity lane · 131bd045
  Tristan Gingold authored Sep 10, 2021
  
  131bd045
08 Sep, 2021 6 commits
- sys: read byte lock stats, add freeze delays · d1de1c4a
  Tristan Gingold authored Sep 08, 2021
  
  d1de1c4a
- sys: minor fixes · 94040d44
  Tristan Gingold authored Sep 08, 2021
  
  94040d44
- sys: add delay inc/dec control · 63a23792
  Tristan Gingold authored Sep 08, 2021
  
  63a23792
- sys_fsi_rx: adjust previous commit · ba39babb
  Tristan Gingold authored Sep 08, 2021
  
  ba39babb
- rtl: adjust previous commit (can now read cntvalue) · d7d1318b
  Tristan Gingold authored Sep 08, 2021
  
  d7d1318b
- rtl: add an interface to read delay cntvalue · 85a6d28e
  Tristan Gingold authored Sep 08, 2021
  
  85a6d28e
07 Sep, 2021 1 commit
- system board: add statistic counters · b377e0c7
  Tristan Gingold authored Sep 07, 2021
  
  b377e0c7
03 Sep, 2021 1 commit
- diot_sys_top: trigger on a rising edge · c0be198f
  Tristan Gingold authored Sep 03, 2021
  
  c0be198f
02 Sep, 2021 1 commit
- fsi_adc: disable pattern by default, more status on led · 6d5f006a
  Tristan Gingold authored Sep 02, 2021
  
  6d5f006a
01 Sep, 2021 1 commit
- sys_fsi_rx: add comments · 8522c58d
  Tristan Gingold authored Sep 01, 2021
  
  8522c58d
25 Aug, 2021 5 commits
- sys_fsi_rx: adjust sampling point offset · f4443c30
  Tristan Gingold authored Aug 25, 2021
  
  f4443c30
- sys: connect fsi_ready · 9242a7e0
  Tristan Gingold authored Aug 25, 2021
  
  9242a7e0
- sys: remove fsi_ready (was not used) · 738a8204
  Tristan Gingold authored Aug 25, 2021
  
  738a8204
- sys_fsi_rx: renaming of lock_i · 0de2cfcd
  Tristan Gingold authored Aug 25, 2021
  
  0de2cfcd
- sys_fsi_rx: increase the locking delay · 0e787d7e
  Tristan Gingold authored Aug 25, 2021
  
  0e787d7e
24 Aug, 2021 2 commits
- sys_fsi_rx.vhd: per bit alignment, adjust locking · 7929d322
  Tristan Gingold authored Aug 24, 2021
  
  7929d322
- fsi_adc_rx.vhd: increase fifo depth · 9f20cd33
  Tristan Gingold authored Aug 24, 2021
  
  9f20cd33
30 Jul, 2021 3 commits
- fsi_adc_rx: add a comment · 7ec3007c
  Tristan Gingold authored Jul 30, 2021
  
  7ec3007c
- fsi: more ILA lines, polarity, patterns · b580d3c1
  Tristan Gingold authored Jul 30, 2021
  
  b580d3c1
- Add ILA. · 1dace496
  Tristan Gingold authored Jul 30, 2021
```
Also adjust SPI timing, reduce bitslip
```
  1dace496
24 Jun, 2021 1 commit
- sys_fsi_rx: adjust to generate bitstream · 00c0dabf
  Tristan Gingold authored Jun 24, 2021
  
  00c0dabf
23 Jun, 2021 2 commits
- diot_sys_top: fix timing issues · 28bb5892
  Tristan Gingold authored Jun 23, 2021
  
  28bb5892
- diot_sys_top: improve (again) timing · 1815be58
  Tristan Gingold authored Jun 23, 2021
  
  1815be58