fsi: add a synchronizer, adjust constraints.

4ce12b7a · Tristan Gingold · 9d0cc7c3 · 4ce12b7a · 4ce12b7a
Commit 4ce12b7a authored Sep 14, 2021 by Tristan Gingold
Hide whitespace changes
Inline Side-by-side

Showing with 13 additions and 3 deletions

fsi_adc_rx.vhd hdl/rtl/fsi/fsi_adc_rx.vhd +12 -2

periph_adc_top.xdc hdl/syn/periph_adc_top/periph_adc_top.xdc +1 -1

No files found.
--- a/hdl/rtl/fsi/fsi_adc_rx.vhd
+++ b/hdl/rtl/fsi/fsi_adc_rx.vhd
@@ -211,8 +211,18 @@ begin
        end if;
    end process;

-    locked_o <= locked;
-
+    --  Synchronizer for locked.
+    inst_sync_locked: entity work.gc_sync
+      generic map (
+        g_sync_edge => "positive"
+      )
+      port map (
+        clk_i => clk_100_i,
+        rst_n_a_i => rst_n_i,
+        d_i => locked,
+        q_o => locked_o
+      );
+    
    --  Resync.
    --  All the serdes was done in the adc clock domain, but the
    --  fpga uses a different clock domain.

--- a/hdl/syn/periph_adc_top/periph_adc_top.xdc
+++ b/hdl/syn/periph_adc_top/periph_adc_top.xdc
@@ -303,4 +303,4 @@ set_property DIFF_TERM TRUE [get_ports adc_adclk_n_i]

 # Clocks
 create_clock -period 10.000 -name fpga_clk -waveform {0.000  5.000} [get_ports {fpga_clk_p_i}]
-create_clock -period 10.000 -name adc_clk -waveform {0.000  5.000} [get_ports {adc_lclk_p_i}]
+create_clock -period 3.333 -name adc_clk -waveform {0.000  1.666} [get_ports {adc_lclk_p_i}]