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FSI Data Acquisition Path Gateware and Software
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FSI Data Acquisition Path Gateware and Software
Commits
eda04460
Commit
eda04460
authored
Nov 29, 2021
by
Maciej Lipinski
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port the previous commit to diot sys acq ip
parent
4b709eda
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2 deletions
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-2
diot_sys_acq_ip.vhd
hdl/rtl/sys/diot_sys_acq_ip.vhd
+17
-2
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hdl/rtl/sys/diot_sys_acq_ip.vhd
View file @
eda04460
...
...
@@ -107,6 +107,7 @@ architecture arch of diot_sys_acq_ip is
END
component
ila_0
;
signal
clk_100m
,
clk_300m
,
clk_400m
:
std_logic
;
signal
clk_100m_serdes
:
std_logic
;
signal
rst_n
:
std_logic
;
signal
pl_reset_n
:
std_logic
;
...
...
@@ -273,6 +274,20 @@ begin
I
=>
clk_400m_int
-- 1-bit input: Buffer
);
inst_bufg_clk100m_serdes
:
BUFGCE_DIV
generic
map
(
BUFGCE_DIVIDE
=>
4
,
IS_CE_INVERTED
=>
'0'
,
-- Optional inversion for CE
IS_CLR_INVERTED
=>
'0'
,
-- Optional inversion for CLR
IS_I_INVERTED
=>
'0'
-- Optional inversion for I
)
port
map
(
O
=>
clk_100m_serdes
,
-- 1-bit output: Buffer
CE
=>
'1'
,
-- 1-bit input: Buffer enable
CLR
=>
'0'
,
-- 1-bit input: Asynchronous clear
I
=>
clk_400m_int
-- 1-bit input: Buffer
);
inst_bufg_300m
:
BUFG
port
map
(
I
=>
clk_300m_int
,
...
...
@@ -499,11 +514,11 @@ begin
trigger_i
=>
trigger_in
);
inst_periph
:
entity
work
.
sys_fsi_core
inst_core
:
entity
work
.
sys_fsi_core
port
map
(
clk_100m_i
=>
clk_100m
,
clk_400m_i
=>
clk_400m
,
clk_100m_oserdes_i
=>
clk_100m
,
clk_100m_oserdes_i
=>
clk_100m
_serdes
,
rst_n_i
=>
rst_n
,
io_rst_i
=>
io_rst_r2
,
bp_io_p_i
=>
bp_io_p_i
,
...
...
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