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FSI Data Acquisition Path Gateware and Software
Commit 4b709eda authored by Tristan Gingold's avatar Tristan Gingold Committed by Maciej Lipinski
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diot_sys_top: use a new bufgce_div for clk_100m serdes (WIP, just a test)

parent d8b900a0
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Showing with 18 additions and 3 deletions
hdl/rtl/sys/diot_sys_top.vhd
View file @ 4b709eda
......@@ -158,6 +158,7 @@ architecture arch of diot_sys_top is
END component ila_0;
signal clk_100m, clk_300m, clk_400m: std_logic;
signal clk_100m_serdes : std_logic;
signal rst_n : std_logic;
signal pl_reset_n : std_logic;
......@@ -421,7 +422,21 @@ begin
I => clk_400m_int -- 1-bit input: Buffer
);
inst_bufg_300m: BUFG
inst_bufg_clk100m_serdes : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 4,
IS_CE_INVERTED => '0', -- Optional inversion for CE
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
IS_I_INVERTED => '0' -- Optional inversion for I
)
port map (
O => clk_100m_serdes, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => clk_400m_int -- 1-bit input: Buffer
);
inst_bufg_300m: BUFG
port map (
I => clk_300m_int,
O => clk_300m
......@@ -770,11 +785,11 @@ begin
trigger_i => trigger_in
);
inst_periph: entity work.sys_fsi_core
inst_core: entity work.sys_fsi_core
port map (
clk_100m_i => clk_100m,
clk_400m_i => clk_400m,
clk_100m_oserdes_i => clk_100m,
clk_100m_oserdes_i => clk_100m_serdes,
rst_n_i => rst_n,
io_rst_i => io_rst_r2,
bp_io_p_i => bp_io_p_i,
......
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