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FSI Data Acquisition Path Gateware and Software
Commit 528d3095 authored by Tristan Gingold's avatar Tristan Gingold Committed by Maciej Lipinski
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sys: add another bufgce_div for oserdes clk400. WIP

parent eda04460
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Showing with 22 additions and 6 deletions
hdl/rtl/sys/diot_sys_top.vhd
View file @ 528d3095
......@@ -158,7 +158,7 @@ architecture arch of diot_sys_top is
END component ila_0;
signal clk_100m, clk_300m, clk_400m: std_logic;
signal clk_100m_serdes : std_logic;
signal clk_100m_oserdes, clk_400m_oserdes : std_logic;
signal rst_n : std_logic;
signal pl_reset_n : std_logic;
......@@ -422,7 +422,7 @@ begin
I => clk_400m_int -- 1-bit input: Buffer
);
inst_bufg_clk100m_serdes : BUFGCE_DIV
inst_bufg_clk100m_oserdes : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 4,
IS_CE_INVERTED => '0', -- Optional inversion for CE
......@@ -430,7 +430,7 @@ begin
IS_I_INVERTED => '0' -- Optional inversion for I
)
port map (
O => clk_100m_serdes, -- 1-bit output: Buffer
O => clk_100m_oserdes, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => clk_400m_int -- 1-bit input: Buffer
......@@ -444,7 +444,7 @@ begin
-- Also use a bufgce_div for clk_400m to reduce (TBC) the skew between
-- clk_400m and clk_100m
inst_bufgdiv_clk100m : BUFGCE_DIV
inst_bufgdiv_clk400m : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 1,
IS_CE_INVERTED => '0',
......@@ -458,6 +458,20 @@ begin
I => clk_400m_int -- 1-bit input: Buffer
);
inst_bufgdiv_clk400m_oserdes : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 1,
IS_CE_INVERTED => '0',
IS_CLR_INVERTED => '0',
IS_I_INVERTED => '0'
)
port map (
O => clk_400m_oserdes, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => clk_400m_int -- 1-bit input: Buffer
);
process (pl_reset_n, clk_locked, clk_100m)
begin
if pl_reset_n = '0' or clk_locked = '0' then
......@@ -789,7 +803,8 @@ begin
port map (
clk_100m_i => clk_100m,
clk_400m_i => clk_400m,
clk_100m_oserdes_i => clk_100m_serdes,
clk_100m_oserdes_i => clk_100m_oserdes,
clk_400m_oserdes_i => clk_400m_oserdes,
rst_n_i => rst_n,
io_rst_i => io_rst_r2,
bp_io_p_i => bp_io_p_i,
......
hdl/rtl/sys/sys_fsi_core.vhd
View file @ 528d3095
......@@ -16,6 +16,7 @@ entity sys_fsi_core is
clk_100m_i : std_logic;
clk_400m_i : std_logic;
clk_100m_oserdes_i : std_logic;
clk_400m_oserdes_i : std_logic;
rst_n_i : std_logic;
io_rst_i : std_logic;
......@@ -149,7 +150,7 @@ begin
inst_fsi_tx: entity work.sys_fsi_tx
port map (
clk_100_i => clk_100m_oserdes_i,
clk_400_i => clk_400m_i,
clk_400_i => clk_400m_oserdes_i,
rst_n_i => rst_n_i,
bp_io_p_o => bp_io_p_o (i),
bp_io_n_o => bp_io_n_o (i),
......
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