- Feb 15, 2013
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- Nov 16, 2012
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Wesley W. Terpstra authored
* Dequeue operations as they arrive * Support variable WB bus size * Don't push zeros to client
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- Nov 15, 2012
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
* Had to re-order initialization; pci_device_enable must precede pci_enable_msi * Must enable master mode on the device to receive MSIs and/or bus master * Report the address/data from the bridge
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- Oct 02, 2012
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Debugging with bad information sucks!
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This would break the read (non-posted) and write (posted) ordering that Wishbone depends on.
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Currently hardcode SDWB address as hardware does not support it.
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Fixed bugs in kernel etherbone: record_len was shadowed by redeclation wrote maximum of possible bytes instead of minimum added non-blocking IO support
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