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Commit 7595c06b authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Import PCIe-WB project into git

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altera_pcie.qip 0 → 100644
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set_global_assignment -name IP_TOOL_NAME "IP Compiler for PCI Express"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie.vhd"]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie_core.vhd"]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) "." ]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) ip_compiler_for_pci_express-library ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_125.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_125_250.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy0.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_trans.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_phasefifo.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.cmp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.vho ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_dma_descriptor.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_dma_dt.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_dma_prg_reg.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_rc_slave.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_read_dma_requester.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_write_dma_requester.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcierd_example_app_chaining.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/init_ram.hex ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/init_ram.mif ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/altpcietb_bfm_driver_chaining.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/init_ram.hex ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/init_ram.mif ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/runtb.bat ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/runtb.do ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/runtb.sh ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/sim_filelist ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/altera_pcie_chaining_testbench.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_pipen1b.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_plus.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_rs_hip.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.qpf ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.qsf ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) altera_pcie.sdc ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.tcl ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/common ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/common/testbench ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_fifo.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_fifo_lkahd.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_msibridge.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_npbypassctl.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_rx.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_rxbridge.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_sideband.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_top.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_tx.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_tx_pktordering.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_txbridge.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_txbridge_withbypass.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altera_pcie_icm.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_serdes.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.ppx ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.ppf ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.cmp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.bsf ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.qip ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.html ]
altera_pcie.sdc 0 → 100644
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create_clock -period "100 MHz" -name {refclk} {pcie_refclk_i}
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
# The refclk assignment may need to be renamed to match design top level port name.
# May be desireable to move refclk assignment to a top level SDC file.
#create_clock -period "100 MHz" -name {refclk} {pcie_refclk_i}
#create_clock -period "125 MHz" -name {fixedclk_serdes} {pcie_clk125_i}
# testin bits are either static or treated asynchronously, cut the paths.
#set_false_path -to [get_pins -hierarchical {*hssi_pcie_hip|testin[*]} ]
# SERDES Digital Reset inputs are asynchronous
#set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
#set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
#
# The following multicycle path constraints are only valid if the logic use to sample the tl_cfg_ctl and tl_cfg_sts signals
# are as designed in the Altera provided files altpcierd_tl_cfg_sample.v and altpcierd_tl_cfg_sample.vhd
#
# These constraints are only valid when the altpcierd_tl_cfg_sample module or entity is used with the PCI Express
# Hard IP block in Stratix IV, Arria II, Cyclone IV and HardCopy IV devices.
# These constraints are not neccesary for PCI Express Hard IP in Stratix V devices.
#
#global tl_cfg_ctl_wr_setup
#global tl_cfg_sts_wr_setup
#
# If there are consistent hold time violations for the tl_cfg_ctl_wr signal in your chosen device and design,
# the multicycle setup constraint for tl_cfg_ctl_wr can be changed from 1 to 0 in the following variable:
#set tl_cfg_ctl_wr_setup 1
#
# If there are consistent hold time violations for the tl_cfg_sts_wr signal in your chosen device and design,
# the multicycle setup constraint for tl_cfg_sts_wr can be changed from 1 to 0 in the following variable:
#set tl_cfg_sts_wr_setup 1
#
#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr}] $tl_cfg_ctl_wr_setup
#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] [expr $tl_cfg_ctl_wr_setup + 2]
#set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] 3
#
#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr}] $tl_cfg_sts_wr_setup
#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts[*]}] [expr $tl_cfg_sts_wr_setup + 2]
#set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts[*]}] 3
altera_pcie.vhd 0 → 100644
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altera_pcie_core.vhd 0 → 100644
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altera_pcie_pll.qip 0 → 100644
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_pcie_pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_pcie_pll.ppf"]
altera_pcie_pll.vhd 0 → 100644
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View file @ 7595c06b
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altera_pcie_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altera_pcie_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altera_pcie_pll;
ARCHITECTURE SYN OF altera_pcie_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 25,
clk0_duty_cycle => 50,
clk0_multiply_by => 8,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Arria II GX",
lpm_hint => "CBX_MODULE_PREFIX=altera_pcie_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "Left_Right",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
using_fbmimicbidir_port => "OFF",
width_clock => 7
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altera_pcie_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
-- Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
altera_pcie_serdes.vhd 0 → 100644
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set_global_assignment -name IP_TOOL_NAME "ALTGX_RECONFIG"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_reconfig.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_reconfig.cmp"]
altera_reconfig.vhd 0 → 100644
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pcie_wb.qpf 0 → 100644
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
# Date created = 11:17:02 March 30, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "11:17:02 March 30, 2012"
# Revisions
PROJECT_REVISION = "pcie_wb"
pcie_wb.qsf 0 → 100644
+ 89
− 0
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
# Date created = 11:17:02 March 30, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# pcie_wb_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Arria II GX"
set_global_assignment -name DEVICE EP2AGX125DF25C6ES
set_global_assignment -name TOP_LEVEL_ENTITY pcie_wb
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:17:02 MARCH 30, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name QIP_FILE altera_pcie.qip
set_global_assignment -name VHDL_FILE pcie_wb.vhd
set_global_assignment -name QIP_FILE altera_reconfig.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_D11 -to pcie_clk125_i
set_location_assignment PIN_U23 -to pcie_refclk_i
set_location_assignment PIN_A11 -to pcie_rstn_i
set_location_assignment PIN_N23 -to pcie_rx_i[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
set_location_assignment PIN_R23 -to pcie_rx_i[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2]
set_location_assignment PIN_R24 -to "pcie_rx_i[2](n)"
set_location_assignment PIN_W23 -to pcie_rx_i[1]
set_location_assignment PIN_AA23 -to pcie_rx_i[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0]
set_location_assignment PIN_AA24 -to "pcie_rx_i[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1]
set_location_assignment PIN_W24 -to "pcie_rx_i[1](n)"
set_location_assignment PIN_M21 -to pcie_tx_o[3]
set_location_assignment PIN_P21 -to pcie_tx_o[2]
set_location_assignment PIN_V21 -to pcie_tx_o[1]
set_location_assignment PIN_Y21 -to pcie_tx_o[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0]
set_location_assignment PIN_Y22 -to "pcie_tx_o[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1]
set_location_assignment PIN_V22 -to "pcie_tx_o[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2]
set_location_assignment PIN_P22 -to "pcie_tx_o[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3]
set_location_assignment PIN_M22 -to "pcie_tx_o[3](n)"
set_instance_assignment -name IO_STANDARD LVDS -to pcie_clk125_i
set_location_assignment PIN_C11 -to "pcie_clk125_i(n)"
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
set_global_assignment -name QIP_FILE altera_pcie_pll.qip
set_location_assignment PIN_AB10 -to led_o
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
pcie_wb.vhd 0 → 100644
+ 0
− 0
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