Solve JTAG problems

Make shorter chains.

Consider using a buffer to slow down the edges.
Xilinx platform cable USB II has fast buffer causing reflection on the lines.

The JTAG lines from the cable have been buffered.
The TCK lines for the 2 FPGAs have been splitted and the same is true for the TMS lines.
The memories have been removed from the JTAG chain.
The SFP connectors have been removed from the programming chain: their JTAG lines have been connected via a buffer to the SFPGA. The buffer was necessary to adapt the levels.

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