02-02-2012: V2 design ready
added by Erik van der Bij on 2012-02-02 16:23:55.103167
Based on the experience with the V1 prototype, nine
Issues were found.
Corrections have been made to the schematics and PCB layout and these
will be reviewed on 7 February. After this CERN's design office will
generate the final production files.
The firmware VHDL code is under thorough review and production test software has to be written. This work should be ready by the end of the summer.
30-05-2011: 3 prototypes assembled
added by Erik van der Bij on 2011-05-30 13:35:49.879354
Three prototypes of the Time to Digital converter have been built. We made a start of the VHDL coding for use on the SPEC PCI Express FMC carrier.
18-03-2011: Schematics design review held
added by Erik van der Bij on 2011-03-18 14:58:49.834557
After a first global schematics review in the week before, a second schematics design review was held with five engineers who found a few details that will improve the functioning and the documentation of the schematics. The PCB layout will likely start in a week's time.