The FMC TDC 1ns 5cha Time to Digital Converter mezzanine board houses 5
input channels. It can calculate time differences between pulses
arriving to the channels with a precision of +-700 ps.
It can be carried by any of the carrier boards:
SVEC. It is implemented using a
dedicated time-to-digital converter IC from the European company
Acam chip in I-mode.
Linux software support for the board is available in the dedicated
project FMC TDC SW.
The provided software comprises: Linux device driver based on
ZIO and stacked on the SPEC or SVEC driver |
User space libraries |
Top view of TDC mezzanine board
5 channels TTL with software selectable 50 Ohm termination.
Inputs need to be protected against +15V pulses with a pulse width of at least 10us at 50Hz
Software controlled switch that enables/ disables all 5 channels
Circular buffer that keeps the last 128 pulses (256 rising and falling edges);
programmable interrupts implemented based on the number of accumulated timestamps or the amount of elapsed time
Timestamps precision (deviation)
+/- 700 ps
+/- 4 ppm from a local TCXO on FMC card; much better accuracy would be reached when used on a White Rabbit enabled FMC carrier
Maximum input pulse rate
31.25 MHz from all 5 channels
Timestamps apply to both rising and falling edges of incoming pulses;
on the software level the falling edges are only used for the calculation of the pulse width, ignoring pulses < 100 ns;
the rising edges are always subtracted between them
Minimum input pulse width
100 ns, narrower pulses are ignored on software level by subtracting a falling edge from the previous rising one