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FMC TDC 1ns 5cha
Commit aab56b90 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: cleanup of whitespace and fix of some misaligned code

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hdl/rtl/acam_databus_interface.vhd
View file @ aab56b90
...@@ -8,10 +8,10 @@ ...@@ -8,10 +8,10 @@
-- Description The unit interfaces with the ACAM chip pins for the configuration of the registers -- Description The unit interfaces with the ACAM chip pins for the configuration of the registers
-- and the acquisition of the timestamps. -- and the acquisition of the timestamps.
-- The ACAM proprietary interface is converted to a WISHBONE classic interface, with -- The ACAM proprietary interface is converted to a WISHBONE classic interface, with
-- which the unit communicates with the data_engine unit. -- which the unit communicates with the data_engine unit.
-- The WISHBONE master is implemented in the data_engine and the slave in this unit. -- The WISHBONE master is implemented in the data_engine and the slave in this unit.
-- --
-- ___________ ____________ ___________ -- ___________ ____________ ___________
-- | |___WRn_______| | | | -- | |___WRn_______| | | |
-- | |___RDn_______| |___stb______| | -- | |___RDn_______| |___stb______| |
-- | |___CSn_______| |___cyc______| | -- | |___CSn_______| |___cyc______| |
......
hdl/rtl/acam_timecontrol_interface.vhd
View file @ aab56b90
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Acam timebase control -- Title : Acam timebase control
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: Interface with the ACAM chip pins for control and timing. -- Description: Interface with the ACAM chip pins for control and timing.
-- the start pulse is sent only once upon the activation of the acquisition, -- the start pulse is sent only once upon the activation of the acquisition,
-- synchronously to the utc_p_i -- synchronously to the utc_p_i
...@@ -114,8 +114,8 @@ begin ...@@ -114,8 +114,8 @@ begin
stop_dis_o <= '1'; stop_dis_o <= '1';
else else
stop_dis_o <= stop_dis_d1; stop_dis_o <= stop_dis_d1;
end if; end if;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
hdl/rtl/clks_rsts_manager.vhd
View file @ aab56b90
...@@ -4,11 +4,11 @@ ...@@ -4,11 +4,11 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : clks_rsts_manager.vhd -- Title : clks_rsts_manager.vhd
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: Independent block that uses the clk_sys_i to parametrize the PLL and DAC on the -- Description: Independent block that uses the clk_sys_i to parametrize the PLL and DAC on the
-- TDC mezzanine -- TDC mezzanine
-- --
-- The PLL is programmed to generate a 125 MHz clock that arrives to the FPGA and -- The PLL is programmed to generate a 125 MHz clock that arrives to the FPGA and
-- is used by all the other units of the TDC core. -- is used by all the other units of the TDC core.
-- It is also programmed to generate a 31.25 MHz clock which is the reference clock -- It is also programmed to generate a 31.25 MHz clock which is the reference clock
-- for the ACAM chip. -- for the ACAM chip.
......
hdl/rtl/data_engine.vhd
View file @ aab56b90
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
-- o the reading back of the ACAM configuration. -- o the reading back of the ACAM configuration.
-- --
-- The signals: activate_acq, deactivate_acq, -- The signals: activate_acq, deactivate_acq,
-- acam_wr_config, acam_rst -- acam_wr_config, acam_rst
-- acam_rdbk_config, acam_rdbk_status, acam_rdbk_ififo1, -- acam_rdbk_config, acam_rdbk_status, acam_rdbk_ififo1,
-- acam_rdbk_ififo2, acam_rdbk_start01 -- acam_rdbk_ififo2, acam_rdbk_start01
-- coming from the reg_ctrl unit determine the actions of this unit. -- coming from the reg_ctrl unit determine the actions of this unit.
...@@ -163,7 +163,7 @@ begin ...@@ -163,7 +163,7 @@ begin
acam_ef2_i, acam_wr_config_p_i, acam_ef2_i, acam_wr_config_p_i,
acam_rdbk_config_p_i, acam_rdbk_status_p_i, acam_ack_i, acam_rst_p_i, acam_rdbk_config_p_i, acam_rdbk_status_p_i, acam_ack_i, acam_rst_p_i,
acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i, acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i,
start_from_fpga_i, time_c, time_c_full_p) start_from_fpga_i, time_c, time_c_full_p)
begin begin
case engine_st is case engine_st is
...@@ -261,7 +261,7 @@ begin ...@@ -261,7 +261,7 @@ begin
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '1'; time_c_rst <= '1';
----------------------------------------------- -----------------------------------------------
if start_from_fpga_i = '1' then if start_from_fpga_i = '1' then
nxt_engine_st <= WAIT_FOR_START01; nxt_engine_st <= WAIT_FOR_START01;
...@@ -279,7 +279,7 @@ begin ...@@ -279,7 +279,7 @@ begin
acam_we <= '0'; acam_we <= '0';
time_c_en <= '1'; time_c_en <= '1';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if time_c = x"00004000" then if time_c = x"00004000" then
nxt_engine_st <= RD_START01; nxt_engine_st <= RD_START01;
...@@ -295,7 +295,7 @@ begin ...@@ -295,7 +295,7 @@ begin
acam_stb <= '1'; acam_stb <= '1';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '1'; time_c_en <= '1';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if acam_ack_i ='1' then if acam_ack_i ='1' then
...@@ -306,14 +306,14 @@ begin ...@@ -306,14 +306,14 @@ begin
when WAIT_UTC => -- wait until the next UTC comes; now the offsets of the start_retrig_ctrl unit are defined when WAIT_UTC => -- wait until the next UTC comes; now the offsets of the start_retrig_ctrl unit are defined
-- the ACAM is disabled during this period -- the ACAM is disabled during this period
----------------------------------------------- -----------------------------------------------
acam_cyc <= '0'; acam_cyc <= '0';
acam_stb <= '0'; acam_stb <= '0';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '1'; time_c_en <= '1';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if time_c_full_p ='1' then if time_c_full_p ='1' then
nxt_engine_st <= ACTIVE; nxt_engine_st <= ACTIVE;
...@@ -328,7 +328,7 @@ begin ...@@ -328,7 +328,7 @@ begin
acam_stb <= '0'; acam_stb <= '0';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '1'; time_c_rst <= '1';
----------------------------------------------- -----------------------------------------------
if deactivate_acq_p_i = '1' then if deactivate_acq_p_i = '1' then
...@@ -378,7 +378,8 @@ begin ...@@ -378,7 +378,8 @@ begin
acam_stb <= '1'; acam_stb <= '1';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; ----------------------------------------------- time_c_rst <= '0';
-----------------------------------------------
if deactivate_acq_p_i = '1' then if deactivate_acq_p_i = '1' then
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
...@@ -404,7 +405,7 @@ begin ...@@ -404,7 +405,7 @@ begin
acam_we <= '1'; acam_we <= '1';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if acam_ack_i = '1' and acam_adr = x"0E" then -- last address if acam_ack_i = '1' and acam_adr = x"0E" then -- last address
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
...@@ -420,7 +421,8 @@ begin ...@@ -420,7 +421,8 @@ begin
acam_stb <= '1'; acam_stb <= '1';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; ----------------------------------------------- time_c_rst <= '0';
-----------------------------------------------
if acam_ack_i = '1' and acam_adr = x"0E" then -- last address if acam_ack_i = '1' and acam_adr = x"0E" then -- last address
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
...@@ -437,7 +439,7 @@ begin ...@@ -437,7 +439,7 @@ begin
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if acam_ack_i ='1' then if acam_ack_i ='1' then
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
......
hdl/rtl/data_formatting.vhd
View file @ aab56b90
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Timestamp data formatting -- Title : Timestamp data formatting
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: Formats in a 128-bit word the -- Description: Formats in a 128-bit word the
-- o fine timestamps coming directly from the ACAM -- o fine timestamps coming directly from the ACAM
-- o plus the coarse timing internally measured in the core -- o plus the coarse timing internally measured in the core
-- o plus the UTC time, coming from the WRabbit core if synchronization is -- o plus the UTC time, coming from the WRabbit core if synchronization is
......
hdl/rtl/decr_counter.vhd
View file @ aab56b90
...@@ -6,8 +6,8 @@ ...@@ -6,8 +6,8 @@
-- Title : Free-running counter -- Title : Free-running counter
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description Stop counter. Configurable "counter_top_i" and "width". -- Description Stop counter. Configurable "counter_top_i" and "width".
-- "Current count value" and "counting done" signals available. -- "Current count value" and "counting done" signals available.
-- "Counter done" signal asserted simultaneous to "current count value = 0". -- "Counter done" signal asserted simultaneous to "current count value = 0".
-- Countdown is launched each time "counter_load_i" is asserted for one clock tick. -- Countdown is launched each time "counter_load_i" is asserted for one clock tick.
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -103,4 +103,4 @@ end architecture rtl; ...@@ -103,4 +103,4 @@ end architecture rtl;
--================================================================================================= --=================================================================================================
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/rtl/fmc_tdc_core.vhd
View file @ aab56b90
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : FMC TDC Core -- Title : FMC TDC Core
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description The TDC core top level instantiates all the modules needed to provide to the -- Description The TDC core top level instantiates all the modules needed to provide to the
-- GN4124/VME interface the timestamps generated in the ACAM chip. -- GN4124/VME interface the timestamps generated in the ACAM chip.
......
hdl/rtl/free_counter.vhd
View file @ aab56b90
...@@ -6,8 +6,8 @@ ...@@ -6,8 +6,8 @@
-- Title : Free-running counter -- Title : Free-running counter
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description Free running counter. Configurable "counter_top_i" and "width". -- Description Free running counter. Configurable "counter_top_i" and "width".
-- "Current count value" and "counting done" signal available. -- "Current count value" and "counting done" signal available.
-- "Counting done" signal asserted simultaneous to "current count value = 0". -- "Counting done" signal asserted simultaneous to "current count value = 0".
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
hdl/rtl/incr_counter.vhd
View file @ aab56b90
...@@ -5,11 +5,11 @@ ...@@ -5,11 +5,11 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : incriment counter -- Title : incriment counter
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: Stop counter. Configurable "counter_top_i" and "width". -- Description: Stop counter. Configurable "counter_top_i" and "width".
-- "Current count value" and "counting done" signals available. -- "Current count value" and "counting done" signals available.
-- "Counting done" signal asserted simultaneous to"current count value=counter_top_i" -- "Counting done" signal asserted simultaneous to"current count value=counter_top_i"
-- Needs a rst_i to restart. -- Needs a rst_i to restart.
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
hdl/rtl/leds_manager.vhd
View file @ aab56b90
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: Generation of the signals that drive the LEDs on the TDC mezzanine. -- Description: Generation of the signals that drive the LEDs on the TDC mezzanine.
-- There are 6 LEDs on the front panel of the TDC mezzanine board: -- There are 6 LEDs on the front panel of the TDC mezzanine board:
-- ______ -- ______
-- | | -- | |
-- | O O | 1, 2 -- | O O | 1, 2
-- | O O | 3, 4 -- | O O | 3, 4
......
hdl/rtl/local_pps_gen.vhd
View file @ aab56b90
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Local PPS generator -- Title : Local PPS generator
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: Generates one pulse every second synchronously with the ACAM reference clock -- Description: Generates one pulse every second synchronously with the ACAM reference clock
-- It also keeps track of the UTC time based on the local clock. -- It also keeps track of the UTC time based on the local clock.
-- If there is no White Rabbit synchronization, this unit is the source of UTC timing -- If there is no White Rabbit synchronization, this unit is the source of UTC timing
......
hdl/rtl/tdc_core_pkg.vhd
View file @ aab56b90
...@@ -584,11 +584,11 @@ package tdc_core_pkg is ...@@ -584,11 +584,11 @@ package tdc_core_pkg is
clk_i : in std_logic; clk_i : in std_logic;
activate_acq_p_i : in std_logic; activate_acq_p_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
state_active_p_i : in std_logic; state_active_p_i : in std_logic;
deactivate_acq_p_i : in std_logic; deactivate_acq_p_i : in std_logic;
---------------------------------------------------------------------- ----------------------------------------------------------------------
start_from_fpga_o : out std_logic; start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
acam_errflag_r_edge_p_o : out std_logic; acam_errflag_r_edge_p_o : out std_logic;
acam_errflag_f_edge_p_o : out std_logic; acam_errflag_f_edge_p_o : out std_logic;
acam_intflag_f_edge_p_o : out std_logic); acam_intflag_f_edge_p_o : out std_logic);
...@@ -820,4 +820,3 @@ end tdc_core_pkg; ...@@ -820,4 +820,3 @@ end tdc_core_pkg;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
hdl/top/spec/wr_spec_tdc.vhd
View file @ aab56b90
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : TDC on SPEC with WR support -- Title : TDC on SPEC with WR support
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: TDC top level with White Rabbit support for a SPEC carrier. -- Description: TDC top level with White Rabbit support for a SPEC carrier.
-- --
......
hdl/top/svec/wr_svec_tdc.vhd
View file @ aab56b90
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : TDC on SVEC with WR support -- Title : TDC on SVEC with WR support
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description: Two TDC mezzanine cores are instantiated, for the boards on FMC1 and FMC2 -- Description: Two TDC mezzanine cores are instantiated, for the boards on FMC1 and FMC2
-- The svec_base_wr provides White Rabbit and host communication. -- The svec_base_wr provides White Rabbit and host communication.
......
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