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FMC TDC 1ns 5cha
Commit a15e1c3e authored by Federico Vaga's avatar Federico Vaga
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bld: autogenerate headers with wbgen2 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent adf37b2e
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Showing with 48 additions and 634 deletions
software/kernel/.gitignore
View file @ a15e1c3e
fmc-bus-link
hw/tdc_eic.h
hw/tdc_dma_eic.h
hw/tdc_onewire_regs.h
hw/tdc_buffer_control_regs.h
hw/timestamp_fifo_regs.h
hw/channel_regs.h
.tmp_versions
\ No newline at end of file
software/kernel/Makefile
View file @ a15e1c3e
......@@ -5,14 +5,18 @@
-include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/../..
TOPDIR ?= $(shell /bin/pwd)/../../
REPO_PARENT ?= $(TOPDIR)/../
-include $(REPO_PARENT)/parent_common.mk
TDC_HDL := $(TOPDIR)/hdl
CPPCHECK ?= cppcheck
DKMS ?= 0
CURDIR := $(shell /bin/pwd)
KVERSION ?= $(shell uname -r)
LINUX ?= /lib/modules/$(KVERSION)/build
WBGEN2 ?= wbgen2
ifdef REPO_PARENT
ZIO ?= $(REPO_PARENT)/fmc/zio
......@@ -49,7 +53,29 @@ VMEBUS_ABS ?= $(abspath $(VMEBUS) )
GIT_VERSION = $(shell git describe --always --dirty --long --tags)
all modules:
all: modules
hw_headers: tdc_eic.h tdc_dma_eic.h tdc_onewire_regs.h tdc_buffer_control_regs.h timestamp_fifo_regs.h channel_regs.h
tdc_eic.h: $(TDC_HDL)/rtl/wbgen/tdc_eic.wb
$(WBGEN2) -s defines -C hw/$@ $<
tdc_dma_eic.h: $(TDC_HDL)/rtl/wbgen/dma_eic.wb
$(WBGEN2) -s defines -C hw/$@ $<
tdc_onewire_regs.h: $(TDC_HDL)/rtl/wbgen/tdc_onewire_wb.wb
$(WBGEN2) -s defines -C hw/$@ $<
tdc_buffer_control_regs.h: $(TDC_HDL)/rtl/wbgen/tdc_buffer_control_regs.wb
$(WBGEN2) -s defines -C hw/$@ $<
timestamp_fifo_regs.h: $(TDC_HDL)/rtl/wbgen/timestamp_fifo_wb.wb
$(WBGEN2) -s defines -C hw/$@ $<
channel_regs.h: $(TDC_HDL)/rtl/wbgen/channel_regs.wb
$(WBGEN2) -s defines -C hw/$@ $<
modules: hw_headers
$(MAKE) -C $(LINUX) M=$(CURDIR) ZIO_ABS=$(ZIO_ABS) FMC_ABS=$(FMC_ABS) \
ZIO_EXTRA_SYMBOLS-y=$(ZIO_EXTRA_SYMBOLS-y) \
FMC_EXTRA_SYMBOLS-y=$(FMC_EXTRA_SYMBOLS-y) \
......@@ -64,6 +90,9 @@ install modules_install: modules
clean:
rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
Module.markers modules.order
rm -f hw/tdc_eic.h hw/tdc_dma_eic.h hw/tdc_onewire_regs.h
rm -f hw/tdc_buffer_control_regs.h hw/timestamp_fifo_regs.h
rm -f hw/channel_regs.h
cppcheck:
$(CPPCHECK) -q -I. -I$(ZIO_ABS)/include -I$(FMC_BUS_ABS)/ --enable=all *.c *.h
software/kernel/ft-zio.c
View file @ a15e1c3e
......@@ -22,6 +22,7 @@
#include <linux/zio-trigger.h>
#include "fmc-tdc.h"
#include "hw/channel_regs.h"
#include "hw/timestamp_fifo_regs.h"
#include "hw/tdc_onewire_regs.h"
......@@ -78,9 +79,9 @@ static void ft_update_offsets(struct fmctdc_dev *ft, int channel)
if (st->user_offset)
ft_ts_apply_offset(&hw_offset, st->user_offset);
ft_iowrite(ft, hw_offset.seconds, fifo_addr + TSF_REG_OFFSET1 );
ft_iowrite(ft, hw_offset.coarse, fifo_addr + TSF_REG_OFFSET2 );
ft_iowrite(ft, hw_offset.frac, fifo_addr + TSF_REG_OFFSET3 );
ft_iowrite(ft, hw_offset.seconds, fifo_addr + CH_REG_REG_OFFSET1);
ft_iowrite(ft, hw_offset.coarse, fifo_addr + CH_REG_REG_OFFSET2);
ft_iowrite(ft, hw_offset.frac, fifo_addr + CH_REG_REG_OFFSET3);
}
static enum ft_devtype __ft_get_type(struct device *dev)
......@@ -98,14 +99,14 @@ static void ft_raw_mode_set(struct fmctdc_dev *ft,
unsigned int raw_enable)
{
void *fifo_addr = ft->ft_fifo_base + TDC_FIFO_OFFSET * chan;
uint32_t csr = ft_ioread(ft, fifo_addr + TSF_REG_CSR);
uint32_t csr = ft_ioread(ft, fifo_addr + CH_REG_REG_CSR);
if (raw_enable)
csr |= TSF_CSR_RAW_MODE;
csr |= CH_REG_CSR_RAW_MODE;
else
csr &= ~TSF_CSR_RAW_MODE;
csr &= ~CH_REG_CSR_RAW_MODE;
ft_iowrite(ft, csr, fifo_addr + TSF_REG_CSR);
ft_iowrite(ft, csr, fifo_addr + CH_REG_REG_CSR);
}
......@@ -113,9 +114,9 @@ static int ft_raw_mode_get(struct fmctdc_dev *ft,
unsigned int chan)
{
void *fifo_addr = ft->ft_fifo_base + TDC_FIFO_OFFSET * chan;
uint32_t csr = ft_ioread(ft, fifo_addr + TSF_REG_CSR);
uint32_t csr = ft_ioread(ft, fifo_addr + CH_REG_REG_CSR);
return (csr & TSF_CSR_RAW_MODE) ? 1 : 0;
return (csr & CH_REG_CSR_RAW_MODE) ? 1 : 0;
}
......
software/kernel/hw/gennum-dma.h deleted 100644 → 0
View file @ adf37b2e
#ifndef __GENNUM_DMA__
#define __GENNUM_DMA__
/*
* fa_dma_item: The information about a DMA transfer
* @start_addr: pointer where start to retrieve data from device memory
* @dma_addr_l: low 32bit of the dma address on host memory
* @dma_addr_h: high 32bit of the dma address on host memory
* @dma_len: number of bytes to transfer from device to host
* @next_addr_l: low 32bit of the address of the next memory area to use
* @next_addr_h: high 32bit of the address of the next memory area to use
* @attribute: dma information about data transferm. At the moment it is used
* only to provide the "last item" bit, direction is fixed to
* device->host
*/
struct gncore_dma_item {
uint32_t start_addr; /* 0x00 */
uint32_t dma_addr_l; /* 0x04 */
uint32_t dma_addr_h; /* 0x08 */
uint32_t dma_len; /* 0x0C */
uint32_t next_addr_l; /* 0x10 */
uint32_t next_addr_h; /* 0x14 */
uint32_t attribute; /* 0x18 */
uint32_t reserved; /* ouch */
};
#define GENUM_DMA_STA_MASK 0x7
#define GENUM_DMA_STA_SHIFT 0
enum gncore_dma_status {
GENNUM_DMA_STA_IDLE = 0,
GENNUM_DMA_STA_DONE,
GENNUM_DMA_STA_BUSY,
GENNUM_DMA_STA_ERROR,
GENNUM_DMA_STA_ABORT,
};
#define GENNUM_DMA_STA_ERR_P2L_MASK 0x78
#define GENNUM_DMA_STA_ERR_P2L_SHIFT 3
enum gncore_dma_status_p2l {
GENNUM_DMA_STA_ERROR_P2L_COMP = 3,
GENNUM_DMA_STA_ERROR_P2L_BUSY,
};
#define GENNUM_DMA_STA_ERR_L2P_MASK 0x780
#define GENNUM_DMA_STA_ERR_L2P_SHIFT 7
enum gncore_dma_status_l2p {
GENNUM_DMA_STA_ERROR_L2P_TX = 7,
GENNUM_DMA_STA_ERROR_L2P_TIMEOUT,
GENNUM_DMA_STA_ERROR_L2P_ABORT,
};
#define GENNUM_DMA_CTL 0x00
#define GENNUM_DMA_STA 0x04
#define GENNUM_DMA_ADDR 0x08
#define GENNUM_DMA_ADDR_L 0x0C
#define GENNUM_DMA_ADDR_H 0x10
#define GENNUM_DMA_LEN 0x14
#define GENNUM_DMA_NEXT_L 0x18
#define GENNUM_DMA_NEXT_H 0x1C
#define GENNUM_DMA_ATTR 0x20
#define GENNUM_DMA_CTL_SWP 0xc
#define GENNUM_DMA_CTL_ABORT 0x2
#define GENNUM_DMA_CTL_START 0x1
#define GENNUM_DMA_ATTR_DIR 0x00000002
#define GENNUM_DMA_ATTR_MORE 0x00000001
#endif /* __GENNUM_DMA__ */
software/kernel/hw/tdc_buffer_control_regs.h deleted 100644 → 0
View file @ adf37b2e
/*
Register definitions for slave core: TDC DMA Buffer Control Registers
* File : tdc_buffer_control_regs.h
* Author : auto-generated by wbgen2 from wbgen/tdc_buffer_control_regs.wb
* Created : Thu Jul 19 16:52:59 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_buffer_control_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TDC_BUFFER_CONTROL_REGS_WB
#define __WBGEN2_REGDEFS_TDC_BUFFER_CONTROL_REGS_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control/Status register */
/* definitions for field: Enable DMA in reg: Control/Status register */
#define TDC_BUF_CSR_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: IRQ Timeout (ms) in reg: Control/Status register */
#define TDC_BUF_CSR_IRQ_TIMEOUT_MASK WBGEN2_GEN_MASK(1, 10)
#define TDC_BUF_CSR_IRQ_TIMEOUT_SHIFT 1
#define TDC_BUF_CSR_IRQ_TIMEOUT_W(value) WBGEN2_GEN_WRITE(value, 1, 10)
#define TDC_BUF_CSR_IRQ_TIMEOUT_R(reg) WBGEN2_GEN_READ(reg, 1, 10)
/* definitions for field: Burst size (timestamps) in reg: Control/Status register */
#define TDC_BUF_CSR_BURST_SIZE_MASK WBGEN2_GEN_MASK(11, 10)
#define TDC_BUF_CSR_BURST_SIZE_SHIFT 11
#define TDC_BUF_CSR_BURST_SIZE_W(value) WBGEN2_GEN_WRITE(value, 11, 10)
#define TDC_BUF_CSR_BURST_SIZE_R(reg) WBGEN2_GEN_READ(reg, 11, 10)
/* definitions for field: Switch buffers in reg: Control/Status register */
#define TDC_BUF_CSR_SWITCH_BUFFERS WBGEN2_GEN_MASK(21, 1)
/* definitions for field: DMA complete in reg: Control/Status register */
#define TDC_BUF_CSR_DONE WBGEN2_GEN_MASK(22, 1)
/* definitions for field: DMA overflow in reg: Control/Status register */
#define TDC_BUF_CSR_OVERFLOW WBGEN2_GEN_MASK(23, 1)
/* definitions for register: Current buffer base address register */
/* definitions for register: Current buffer base count register */
/* definitions for register: Current buffer base size/valid flag register */
/* definitions for field: Size (in transfers) in reg: Current buffer base size/valid flag register */
#define TDC_BUF_CUR_SIZE_SIZE_MASK WBGEN2_GEN_MASK(0, 30)
#define TDC_BUF_CUR_SIZE_SIZE_SHIFT 0
#define TDC_BUF_CUR_SIZE_SIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 30)
#define TDC_BUF_CUR_SIZE_SIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 30)
/* definitions for field: Valid flag in reg: Current buffer base size/valid flag register */
#define TDC_BUF_CUR_SIZE_VALID WBGEN2_GEN_MASK(30, 1)
/* definitions for register: Next buffer base address register */
/* definitions for register: Next buffer base size/valid flag register */
/* definitions for field: Size (in transfers) in reg: Next buffer base size/valid flag register */
#define TDC_BUF_NEXT_SIZE_SIZE_MASK WBGEN2_GEN_MASK(0, 30)
#define TDC_BUF_NEXT_SIZE_SIZE_SHIFT 0
#define TDC_BUF_NEXT_SIZE_SIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 30)
#define TDC_BUF_NEXT_SIZE_SIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 30)
/* definitions for field: Valid flag in reg: Next buffer base size/valid flag register */
#define TDC_BUF_NEXT_SIZE_VALID WBGEN2_GEN_MASK(30, 1)
/* [0x0]: REG Control/Status register */
#define TDC_BUF_REG_CSR 0x00000000
/* [0x4]: REG Current buffer base address register */
#define TDC_BUF_REG_CUR_BASE 0x00000004
/* [0x8]: REG Current buffer base count register */
#define TDC_BUF_REG_CUR_COUNT 0x00000008
/* [0xc]: REG Current buffer base size/valid flag register */
#define TDC_BUF_REG_CUR_SIZE 0x0000000c
/* [0x10]: REG Next buffer base address register */
#define TDC_BUF_REG_NEXT_BASE 0x00000010
/* [0x14]: REG Next buffer base size/valid flag register */
#define TDC_BUF_REG_NEXT_SIZE 0x00000014
#endif
software/kernel/hw/tdc_dma_eic.h deleted 100644 → 0
View file @ adf37b2e
/*
Register definitions for slave core: GN4124 DMA enhanced interrupt controller
* File : /afs/cern.ch/user/f/fvaga/workspace-afs/projects/fmc-tdc/sources/fmc-tdc-sw/kernel/hw/tdc_dma_eic.h
* Author : auto-generated by wbgen2 from dma_eic.wb
* Created : Fri Aug 10 12:07:55 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_DMA_EIC_WB
#define __WBGEN2_REGDEFS_DMA_EIC_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: DMA done interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: DMA done interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: DMA done interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: DMA done interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* [0x20]: REG Interrupt disable register */
#define DMA_EIC_REG_EIC_IDR 0x00000000
/* [0x24]: REG Interrupt enable register */
#define DMA_EIC_REG_EIC_IER 0x00000004
/* [0x28]: REG Interrupt mask register */
#define DMA_EIC_REG_EIC_IMR 0x00000008
/* [0x2c]: REG Interrupt status register */
#define DMA_EIC_REG_EIC_ISR 0x0000000c
#endif
software/kernel/hw/tdc_eic.h deleted 100644 → 0
View file @ adf37b2e
/*
Register definitions for slave core: TDC EIC
* File : /afs/cern.ch/user/f/fvaga/workspace-afs/projects/fmc-tdc/sources/fmc-tdc-sw/kernel/hw/tdc_eic.h
* Author : auto-generated by wbgen2 from tdc_eic.wb
* Created : Tue Aug 7 08:55:50 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TDC_EIC_WB
#define __WBGEN2_REGDEFS_TDC_EIC_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt disable register */
#define TDC_EIC_EIC_IDR_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt enable register */
#define TDC_EIC_EIC_IER_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt mask register */
#define TDC_EIC_EIC_IMR_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: FMC TDC timestamps interrupt (FIFO1) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO2) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO2 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO3) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO3 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO4) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO4 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: FMC TDC timestamps interrupt (FIFO5) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_FIFO5 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA1) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA1 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA2) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA2 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA3) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA3 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA4) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA4 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: FMC TDC timestamps interrupt (DMA5) in reg: Interrupt status register */
#define TDC_EIC_EIC_ISR_TDC_DMA5 WBGEN2_GEN_MASK(9, 1)
/* [0x20]: REG Interrupt disable register */
#define TDC_EIC_REG_EIC_IDR 0x00000000
/* [0x24]: REG Interrupt enable register */
#define TDC_EIC_REG_EIC_IER 0x00000004
/* [0x28]: REG Interrupt mask register */
#define TDC_EIC_REG_EIC_IMR 0x00000008
/* [0x2c]: REG Interrupt status register */
#define TDC_EIC_REG_EIC_ISR 0x0000000c
#endif
software/kernel/hw/tdc_onewire_regs.h deleted 100644 → 0
View file @ adf37b2e
/*
Register definitions for slave core: TDC Onewire Master
* File : tdc_onewire_regs.h
* Author : auto-generated by wbgen2 from wbgen/tdc_onewire_wb.wb
* Created : Tue Sep 11 11:16:49 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_onewire_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TDC_ONEWIRE_WB_WB
#define __WBGEN2_REGDEFS_TDC_ONEWIRE_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status Register */
/* definitions for field: Temperature & ID valid in reg: Status Register */
#define TDC_OW_CSR_VALID WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Board Temperature */
/* definitions for register: Board Unique ID (MSW) */
/* definitions for register: Board Unique ID (LSW) */
/* [0x0]: REG Status Register */
#define TDC_OW_REG_CSR 0x00000000
/* [0x4]: REG Board Temperature */
#define TDC_OW_REG_TEMP 0x00000004
/* [0x8]: REG Board Unique ID (MSW) */
#define TDC_OW_REG_ID_H 0x00000008
/* [0xc]: REG Board Unique ID (LSW) */
#define TDC_OW_REG_ID_L 0x0000000c
#endif
software/kernel/hw/tdc_regs.h
View file @ a15e1c3e
......@@ -12,7 +12,6 @@
#ifndef __TDC_REGISTERS_H
#define __TDC_REGISTERS_H
#include <hw/gennum-dma.h>
#include <hw/tdc_buffer_control_regs.h>
/* Gennum chip register */
......
software/kernel/hw/timestamp_fifo_regs.h deleted 100644 → 0
View file @ adf37b2e
/*
Register definitions for slave core: Timestamp FIFO
* File : timestamp_fifo_regs.h
* Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
* Created : Sun Sep 2 15:37:55 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TIMESTAMP_FIFO_WB_WB
#define __WBGEN2_REGDEFS_TIMESTAMP_FIFO_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Delta Timestamp Word 1 */
/* definitions for register: Delta Timestamp Word 2 */
/* definitions for register: Delta Timestamp Word 3 */
/* definitions for register: Channel Offset Word 1 */
/* definitions for register: Channel Offset Word 2 */
/* definitions for register: Channel Offset Word 3 */
/* definitions for register: Control/Status */
/* definitions for field: Delta Timestamp Ready in reg: Control/Status */
#define TSF_CSR_DELTA_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Read Delta Timestamp in reg: Control/Status */
#define TSF_CSR_DELTA_READ WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reset Sequence Counter in reg: Control/Status */
#define TSF_CSR_RST_SEQ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Delta Timestamp Reference Channel in reg: Control/Status */
#define TSF_CSR_DELTA_REF_MASK WBGEN2_GEN_MASK(3, 3)
#define TSF_CSR_DELTA_REF_SHIFT 3
#define TSF_CSR_DELTA_REF_W(value) WBGEN2_GEN_WRITE(value, 3, 3)
#define TSF_CSR_DELTA_REF_R(reg) WBGEN2_GEN_READ(reg, 3, 3)
/* definitions for field: Raw readout mode in reg: Control/Status */
#define TSF_CSR_RAW_MODE WBGEN2_GEN_MASK(6, 1)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 0 */
/* definitions for field: The timestamp (word 0) in reg: FIFO 'Timestamp FIFO' data output register 0 */
#define TSF_FIFO_R0_TS0_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R0_TS0_SHIFT 0
#define TSF_FIFO_R0_TS0_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R0_TS0_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 1 */
/* definitions for field: The timestamp (word 1) in reg: FIFO 'Timestamp FIFO' data output register 1 */
#define TSF_FIFO_R1_TS1_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R1_TS1_SHIFT 0
#define TSF_FIFO_R1_TS1_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R1_TS1_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 2 */
/* definitions for field: The timestamp (word 2) in reg: FIFO 'Timestamp FIFO' data output register 2 */
#define TSF_FIFO_R2_TS2_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R2_TS2_SHIFT 0
#define TSF_FIFO_R2_TS2_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R2_TS2_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 3 */
/* definitions for field: The timestamp (word 3) in reg: FIFO 'Timestamp FIFO' data output register 3 */
#define TSF_FIFO_R3_TS3_MASK WBGEN2_GEN_MASK(0, 32)
#define TSF_FIFO_R3_TS3_SHIFT 0
#define TSF_FIFO_R3_TS3_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define TSF_FIFO_R3_TS3_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Timestamp FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO clear in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_CLEAR_BUS WBGEN2_GEN_MASK(18, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO' control/status register */
#define TSF_FIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 6)
#define TSF_FIFO_CSR_USEDW_SHIFT 0
#define TSF_FIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define TSF_FIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* [0x0]: REG Delta Timestamp Word 1 */
#define TSF_REG_DELTA1 0x00000000
/* [0x4]: REG Delta Timestamp Word 2 */
#define TSF_REG_DELTA2 0x00000004
/* [0x8]: REG Delta Timestamp Word 3 */
#define TSF_REG_DELTA3 0x00000008
/* [0xc]: REG Channel Offset Word 1 */
#define TSF_REG_OFFSET1 0x0000000c
/* [0x10]: REG Channel Offset Word 2 */
#define TSF_REG_OFFSET2 0x00000010
/* [0x14]: REG Channel Offset Word 3 */
#define TSF_REG_OFFSET3 0x00000014
/* [0x18]: REG Control/Status */
#define TSF_REG_CSR 0x00000018
/* [0x1c]: REG FIFO 'Timestamp FIFO' data output register 0 */
#define TSF_REG_FIFO_R0 0x0000001c
/* [0x20]: REG FIFO 'Timestamp FIFO' data output register 1 */
#define TSF_REG_FIFO_R1 0x00000020
/* [0x24]: REG FIFO 'Timestamp FIFO' data output register 2 */
#define TSF_REG_FIFO_R2 0x00000024
/* [0x28]: REG FIFO 'Timestamp FIFO' data output register 3 */
#define TSF_REG_FIFO_R3 0x00000028
/* [0x2c]: REG FIFO 'Timestamp FIFO' control/status register */
#define TSF_REG_FIFO_CSR 0x0000002c
#endif
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