Skip to content

F
FMC TDC 1ns 5cha
Commit 58de2f4a authored by egousiou's avatar egousiou
Browse files
Options

- small correction on carrier_info inputs 

- removed 1-wire from sdb on designs with WRabbit
- doc updated

git-svn-id: http://svn.ohwr.org/fmc-tdc@180 85dfdc96-de2c-444c-878d-45b388be74a9
parent d567a391
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 4997 additions and 5285 deletions
hdl/syn/spec/no_wrabbit/spec_tdc.par
View file @ 58de2f4a
This diff is collapsed.
hdl/syn/spec/no_wrabbit/spec_tdc.twr
View file @ 58de2f4a
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/no_wrabbit/spec_tdc_map.map
View file @ 58de2f4a
...@@ -10,7 +10,7 @@ Target Device : xc6slx45t ...@@ -10,7 +10,7 @@ Target Device : xc6slx45t
Target Package : fgg484 Target Package : fgg484
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 10:48:16 2014 Mapped Date : Mon Jun 23 18:44:18 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part. INFO:Security:54 - 'xc6slx45t' is a WebPack part.
...@@ -25,56 +25,56 @@ Updating timing models... ...@@ -25,56 +25,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 16 secs Total REAL time at the beginning of Placer: 18 secs
Total CPU time at the beginning of Placer: 16 secs Total CPU time at the beginning of Placer: 16 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 18 secs Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 20 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 19 secs Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 20 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 19 secs Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 20 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:46e77852) REAL time: 49 secs (Checksum:46e77852) REAL time: 52 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 49 secs Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 49 secs Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 52 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 49 secs Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 50 secs Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
............................. ................................
...................................................................................................................... ....................................................................
.................................... ...............................................................
........................... ......................
Phase 9.8 Global Placement (Checksum:986ae115) REAL time: 1 mins 18 secs Phase 9.8 Global Placement (Checksum:bed8b73d) REAL time: 1 mins 24 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:986ae115) REAL time: 1 mins 18 secs Phase 10.5 Local Placement Optimization (Checksum:bed8b73d) REAL time: 1 mins 24 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:49eeddee) REAL time: 1 mins 33 secs Phase 11.18 Placement Optimization (Checksum:d7b12fa8) REAL time: 1 mins 39 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:49eeddee) REAL time: 1 mins 33 secs Phase 12.5 Local Placement Optimization (Checksum:d7b12fa8) REAL time: 1 mins 40 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:8fcb33fb) REAL time: 1 mins 33 secs Phase 13.34 Placement Validation (Checksum:ad8925d5) REAL time: 1 mins 40 secs
Total REAL time to Placer completion: 1 mins 40 secs Total REAL time to Placer completion: 1 mins 47 secs
Total CPU time to Placer completion: 1 mins 40 secs Total CPU time to Placer completion: 1 mins 44 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net WARNING:PhysDesignRules:372 - Gated clock. Clock net
...@@ -94,7 +94,7 @@ Slice Logic Utilization: ...@@ -94,7 +94,7 @@ Slice Logic Utilization:
Number used as Latches: 2 Number used as Latches: 2
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 23 Number used as AND/OR logics: 23
Number of Slice LUTs: 3,871 out of 27,288 14% Number of Slice LUTs: 3,896 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13% Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251 Number using O6 output only: 2,251
Number using O5 output only: 328 Number using O5 output only: 328
...@@ -107,18 +107,18 @@ Slice Logic Utilization: ...@@ -107,18 +107,18 @@ Slice Logic Utilization:
Number using O6 output only: 2 Number using O6 output only: 2
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 88 Number used exclusively as route-thrus: 113
Number with same-slice register load: 54 Number with same-slice register load: 67
Number with same-slice carry load: 34 Number with same-slice carry load: 46
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 1,514 out of 6,822 22% Number of occupied Slices: 1,433 out of 6,822 21%
Nummber of MUXCYs used: 1,284 out of 13,644 9% Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,830 Number of LUT Flip Flop pairs used: 4,679
Number with an unused Flip Flop: 1,533 out of 4,830 31% Number with an unused Flip Flop: 1,407 out of 4,679 30%
Number with an unused LUT: 959 out of 4,830 19% Number with an unused LUT: 783 out of 4,679 16%
Number of fully used LUT-FF pairs: 2,338 out of 4,830 48% Number of fully used LUT-FF pairs: 2,489 out of 4,679 53%
Number of unique control sets: 129 Number of unique control sets: 129
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1% to control set restrictions: 309 out of 54,576 1%
...@@ -174,9 +174,9 @@ Specific Feature Utilization: ...@@ -174,9 +174,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70 Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 355 MB Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 1 mins 45 secs Total REAL time to MAP completion: 1 mins 51 secs
Total CPU time to MAP completion: 1 mins 44 secs Total CPU time to MAP completion: 1 mins 48 secs
Mapping completed. Mapping completed.
See MAP report file "spec_tdc_map.mrp" for details. See MAP report file "spec_tdc_map.mrp" for details.
hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp
View file @ 58de2f4a
...@@ -10,7 +10,7 @@ Target Device : xc6slx45t ...@@ -10,7 +10,7 @@ Target Device : xc6slx45t
Target Package : fgg484 Target Package : fgg484
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 10:48:16 2014 Mapped Date : Mon Jun 23 18:44:18 2014
Design Summary Design Summary
-------------- --------------
...@@ -22,7 +22,7 @@ Slice Logic Utilization: ...@@ -22,7 +22,7 @@ Slice Logic Utilization:
Number used as Latches: 2 Number used as Latches: 2
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 23 Number used as AND/OR logics: 23
Number of Slice LUTs: 3,871 out of 27,288 14% Number of Slice LUTs: 3,896 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13% Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251 Number using O6 output only: 2,251
Number using O5 output only: 328 Number using O5 output only: 328
...@@ -35,18 +35,18 @@ Slice Logic Utilization: ...@@ -35,18 +35,18 @@ Slice Logic Utilization:
Number using O6 output only: 2 Number using O6 output only: 2
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 88 Number used exclusively as route-thrus: 113
Number with same-slice register load: 54 Number with same-slice register load: 67
Number with same-slice carry load: 34 Number with same-slice carry load: 46
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 1,514 out of 6,822 22% Number of occupied Slices: 1,433 out of 6,822 21%
Nummber of MUXCYs used: 1,284 out of 13,644 9% Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,830 Number of LUT Flip Flop pairs used: 4,679
Number with an unused Flip Flop: 1,533 out of 4,830 31% Number with an unused Flip Flop: 1,407 out of 4,679 30%
Number with an unused LUT: 959 out of 4,830 19% Number with an unused LUT: 783 out of 4,679 16%
Number of fully used LUT-FF pairs: 2,338 out of 4,830 48% Number of fully used LUT-FF pairs: 2,489 out of 4,679 53%
Number of unique control sets: 129 Number of unique control sets: 129
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1% to control set restrictions: 309 out of 54,576 1%
...@@ -102,9 +102,9 @@ Specific Feature Utilization: ...@@ -102,9 +102,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70 Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 355 MB Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 1 mins 45 secs Total REAL time to MAP completion: 1 mins 51 secs
Total CPU time to MAP completion: 1 mins 44 secs Total CPU time to MAP completion: 1 mins 48 secs
Table of Contents Table of Contents
----------------- -----------------
......
hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
View file @ 58de2f4a
This diff is collapsed.
hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
View file @ 58de2f4a
This diff is collapsed.
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp
View file @ 58de2f4a
...@@ -11,23 +11,23 @@ Target Device : xc6slx45t ...@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484 Target Package : fgg484
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 11:23:56 2014 Mapped Date : Mon Jun 23 19:09:15 2014
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 9 Number of warnings: 9
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 8,194 out of 54,576 15% Number of Slice Registers: 8,192 out of 54,576 15%
Number used as Flip Flops: 8,168 Number used as Flip Flops: 8,166
Number used as Latches: 2 Number used as Latches: 2
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 24 Number used as AND/OR logics: 24
Number of Slice LUTs: 10,661 out of 27,288 39% Number of Slice LUTs: 10,641 out of 27,288 38%
Number used as logic: 10,390 out of 27,288 38% Number used as logic: 10,381 out of 27,288 38%
Number using O6 output only: 7,383 Number using O6 output only: 7,374
Number using O5 output only: 776 Number using O5 output only: 775
Number using O5 and O6: 2,231 Number using O5 and O6: 2,232
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1% Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24 Number used as Dual Port RAM: 24
...@@ -39,21 +39,21 @@ Slice Logic Utilization: ...@@ -39,21 +39,21 @@ Slice Logic Utilization:
Number using O6 output only: 22 Number using O6 output only: 22
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 21 Number using O5 and O6: 21
Number used exclusively as route-thrus: 204 Number used exclusively as route-thrus: 193
Number with same-slice register load: 133 Number with same-slice register load: 116
Number with same-slice carry load: 71 Number with same-slice carry load: 77
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 4,024 out of 6,822 58% Number of occupied Slices: 3,975 out of 6,822 58%
Nummber of MUXCYs used: 2,388 out of 13,644 17% Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,505 Number of LUT Flip Flop pairs used: 12,385
Number with an unused Flip Flop: 4,934 out of 12,505 39% Number with an unused Flip Flop: 4,772 out of 12,385 38%
Number with an unused LUT: 1,844 out of 12,505 14% Number with an unused LUT: 1,744 out of 12,385 14%
Number of fully used LUT-FF pairs: 5,727 out of 12,505 45% Number of fully used LUT-FF pairs: 5,869 out of 12,385 47%
Number of unique control sets: 372 Number of unique control sets: 372
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 990 out of 54,576 1% to control set restrictions: 992 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -111,8 +111,8 @@ Specific Feature Utilization: ...@@ -111,8 +111,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59 Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 33 secs Total REAL time to MAP completion: 6 mins 32 secs
Total CPU time to MAP completion: 6 mins 26 secs Total CPU time to MAP completion: 6 mins 29 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -144,11 +144,11 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net ...@@ -144,11 +144,11 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
CE pin to control the loading of data into the flip-flop. CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
...@@ -156,15 +156,15 @@ WARNING:PhysDesignRules:367 - The signal ...@@ -156,15 +156,15 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
...@@ -380,7 +380,7 @@ and has been removed. ...@@ -380,7 +380,7 @@ and has been removed.
removed. removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
loadless and has been removed. loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0364_inv1" (ROM) Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0363_inv1" (ROM)
removed. removed.
Loadless block Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2) "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
......
hdl/syn/svec/no_wrabbit/svec_tdc.par
View file @ 58de2f4a
This diff is collapsed.
hdl/syn/svec/no_wrabbit/svec_tdc.twr
View file @ 58de2f4a
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/no_wrabbit/svec_tdc_map.map
View file @ 58de2f4a
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg900 Target Package : fgg900
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 12:27:04 2014 Mapped Date : Mon Jun 23 18:14:34 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part. INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
...@@ -25,56 +25,56 @@ Updating timing models... ...@@ -25,56 +25,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 33 secs Total REAL time at the beginning of Placer: 32 secs
Total CPU time at the beginning of Placer: 32 secs Total CPU time at the beginning of Placer: 31 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:a7de1977) REAL time: 39 secs Phase 1.1 Initial Placement Analysis (Checksum:8f55c916) REAL time: 39 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:a7de1977) REAL time: 41 secs Phase 2.7 Design Feasibility Check (Checksum:8f55c916) REAL time: 40 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:a7de1977) REAL time: 41 secs Phase 3.31 Local Placement Optimization (Checksum:8f55c916) REAL time: 40 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:2b539d14) REAL time: 55 secs (Checksum:a1530eec) REAL time: 54 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:2b539d14) REAL time: 55 secs Phase 5.36 Local Placement Optimization (Checksum:a1530eec) REAL time: 54 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:2b539d14) REAL time: 55 secs Phase 6.30 Global Clock Region Assignment (Checksum:a1530eec) REAL time: 54 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:2b539d14) REAL time: 55 secs Phase 7.3 Local Placement Optimization (Checksum:a1530eec) REAL time: 55 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:2b539d14) REAL time: 56 secs Phase 8.5 Local Placement Optimization (Checksum:a1530eec) REAL time: 55 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
......................................... ....................................................
............................................................................................................................................................................................................... .........................................................................................................................................................................................................
......................................................................................................................................................................................... ......................................................................................................................................................................................
....................................................................... ....................................................................
Phase 9.8 Global Placement (Checksum:4c7cc37c) REAL time: 2 mins Phase 9.8 Global Placement (Checksum:da2f71c0) REAL time: 1 mins 56 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:4c7cc37c) REAL time: 2 mins Phase 10.5 Local Placement Optimization (Checksum:da2f71c0) REAL time: 1 mins 56 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:4ab5face) REAL time: 2 mins 54 secs Phase 11.18 Placement Optimization (Checksum:f94a054e) REAL time: 2 mins 33 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:4ab5face) REAL time: 2 mins 54 secs Phase 12.5 Local Placement Optimization (Checksum:f94a054e) REAL time: 2 mins 33 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:ed98fec0) REAL time: 2 mins 55 secs Phase 13.34 Placement Validation (Checksum:3b63104b) REAL time: 2 mins 34 secs
Total REAL time to Placer completion: 3 mins 41 secs Total REAL time to Placer completion: 3 mins 23 secs
Total CPU time to Placer completion: 3 mins 39 secs Total CPU time to Placer completion: 3 mins 22 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net WARNING:PhysDesignRules:372 - Gated clock. Clock net
...@@ -102,7 +102,7 @@ Slice Logic Utilization: ...@@ -102,7 +102,7 @@ Slice Logic Utilization:
Number used as Latches: 4 Number used as Latches: 4
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 46 Number used as AND/OR logics: 46
Number of Slice LUTs: 9,203 out of 92,152 9% Number of Slice LUTs: 9,194 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9% Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909 Number using O6 output only: 5,909
Number using O5 output only: 351 Number using O5 output only: 351
...@@ -115,18 +115,18 @@ Slice Logic Utilization: ...@@ -115,18 +115,18 @@ Slice Logic Utilization:
Number using O6 output only: 9 Number using O6 output only: 9
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 26 Number using O5 and O6: 26
Number used exclusively as route-thrus: 142 Number used exclusively as route-thrus: 133
Number with same-slice register load: 67 Number with same-slice register load: 58
Number with same-slice carry load: 75 Number with same-slice carry load: 75
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 3,359 out of 23,038 14% Number of occupied Slices: 3,585 out of 23,038 15%
Nummber of MUXCYs used: 2,428 out of 46,076 5% Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,598 Number of LUT Flip Flop pairs used: 10,689
Number with an unused Flip Flop: 4,155 out of 10,598 39% Number with an unused Flip Flop: 4,235 out of 10,689 39%
Number with an unused LUT: 1,395 out of 10,598 13% Number with an unused LUT: 1,495 out of 10,689 13%
Number of fully used LUT-FF pairs: 5,048 out of 10,598 47% Number of fully used LUT-FF pairs: 4,959 out of 10,689 46%
Number of unique control sets: 264 Number of unique control sets: 264
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1% to control set restrictions: 486 out of 184,304 1%
...@@ -177,9 +177,9 @@ Specific Feature Utilization: ...@@ -177,9 +177,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 4.00 Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 529 MB Peak Memory Usage: 528 MB
Total REAL time to MAP completion: 3 mins 50 secs Total REAL time to MAP completion: 3 mins 32 secs
Total CPU time to MAP completion: 3 mins 47 secs Total CPU time to MAP completion: 3 mins 30 secs
Mapping completed. Mapping completed.
See MAP report file "svec_tdc_map.mrp" for details. See MAP report file "svec_tdc_map.mrp" for details.
hdl/syn/svec/no_wrabbit/svec_tdc_map.mrp
View file @ 58de2f4a
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg900 Target Package : fgg900
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 12:27:04 2014 Mapped Date : Mon Jun 23 18:14:34 2014
Design Summary Design Summary
-------------- --------------
...@@ -22,7 +22,7 @@ Slice Logic Utilization: ...@@ -22,7 +22,7 @@ Slice Logic Utilization:
Number used as Latches: 4 Number used as Latches: 4
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 46 Number used as AND/OR logics: 46
Number of Slice LUTs: 9,203 out of 92,152 9% Number of Slice LUTs: 9,194 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9% Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909 Number using O6 output only: 5,909
Number using O5 output only: 351 Number using O5 output only: 351
...@@ -35,18 +35,18 @@ Slice Logic Utilization: ...@@ -35,18 +35,18 @@ Slice Logic Utilization:
Number using O6 output only: 9 Number using O6 output only: 9
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 26 Number using O5 and O6: 26
Number used exclusively as route-thrus: 142 Number used exclusively as route-thrus: 133
Number with same-slice register load: 67 Number with same-slice register load: 58
Number with same-slice carry load: 75 Number with same-slice carry load: 75
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 3,359 out of 23,038 14% Number of occupied Slices: 3,585 out of 23,038 15%
Nummber of MUXCYs used: 2,428 out of 46,076 5% Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,598 Number of LUT Flip Flop pairs used: 10,689
Number with an unused Flip Flop: 4,155 out of 10,598 39% Number with an unused Flip Flop: 4,235 out of 10,689 39%
Number with an unused LUT: 1,395 out of 10,598 13% Number with an unused LUT: 1,495 out of 10,689 13%
Number of fully used LUT-FF pairs: 5,048 out of 10,598 47% Number of fully used LUT-FF pairs: 4,959 out of 10,689 46%
Number of unique control sets: 264 Number of unique control sets: 264
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1% to control set restrictions: 486 out of 184,304 1%
...@@ -97,9 +97,9 @@ Specific Feature Utilization: ...@@ -97,9 +97,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 4.00 Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 529 MB Peak Memory Usage: 528 MB
Total REAL time to MAP completion: 3 mins 50 secs Total REAL time to MAP completion: 3 mins 32 secs
Total CPU time to MAP completion: 3 mins 47 secs Total CPU time to MAP completion: 3 mins 30 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -142,7 +142,7 @@ Section 3 - Informational ...@@ -142,7 +142,7 @@ Section 3 - Informational
------------------------- -------------------------
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part. INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network VME_BBSY_n_i has no load. INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
INFO:LIT:395 - The above info message is repeated 270 more times for the INFO:LIT:395 - The above info message is repeated 268 more times for the
following (max. 5 shown): following (max. 5 shown):
tdc1_in_fpga_1_i, tdc1_in_fpga_1_i,
tdc1_in_fpga_2_i, tdc1_in_fpga_2_i,
......
hdl/syn/svec/with_wrabbit/wr_svec_tdc.par
View file @ 58de2f4a
This diff is collapsed.
hdl/syn/svec/with_wrabbit/wr_svec_tdc.twr
View file @ 58de2f4a
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.map
View file @ 58de2f4a
...@@ -11,7 +11,7 @@ Target Device : xc6slx150t ...@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg900 Target Package : fgg900
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 12:12:19 2014 Mapped Date : Mon Jun 23 17:22:57 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part. INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
...@@ -26,57 +26,57 @@ Updating timing models... ...@@ -26,57 +26,57 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 51 secs Total REAL time at the beginning of Placer: 52 secs
Total CPU time at the beginning of Placer: 48 secs Total CPU time at the beginning of Placer: 48 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:58a5c00) REAL time: 1 mins 1 secs Phase 1.1 Initial Placement Analysis (Checksum:727220ca) REAL time: 1 mins
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:58a5c00) REAL time: 1 mins 3 secs Phase 2.7 Design Feasibility Check (Checksum:727220ca) REAL time: 1 mins 2 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:4be425da) REAL time: 1 mins 3 secs Phase 3.31 Local Placement Optimization (Checksum:c940f3c7) REAL time: 1 mins 2 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a584c7a0) REAL time: 1 mins 21 secs (Checksum:a365d66e) REAL time: 1 mins 20 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a584c7a0) REAL time: 1 mins 21 secs Phase 5.36 Local Placement Optimization (Checksum:a365d66e) REAL time: 1 mins 20 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a584c7a0) REAL time: 1 mins 21 secs Phase 6.30 Global Clock Region Assignment (Checksum:a365d66e) REAL time: 1 mins 20 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a584c7a0) REAL time: 1 mins 22 secs Phase 7.3 Local Placement Optimization (Checksum:a365d66e) REAL time: 1 mins 21 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a584c7a0) REAL time: 1 mins 22 secs Phase 8.5 Local Placement Optimization (Checksum:a365d66e) REAL time: 1 mins 21 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
..................... .....................
......................................... .........................................................................
................................ ....................................................................................................................................................................
..................................................... .....................................................................................................
.......................... ................................................................
Phase 9.8 Global Placement (Checksum:ac8519a8) REAL time: 3 mins 5 secs Phase 9.8 Global Placement (Checksum:b067106b) REAL time: 3 mins 22 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ac8519a8) REAL time: 3 mins 6 secs Phase 10.5 Local Placement Optimization (Checksum:b067106b) REAL time: 3 mins 23 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:b020cb03) REAL time: 3 mins 56 secs Phase 11.18 Placement Optimization (Checksum:1bfa6c45) REAL time: 4 mins 15 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:b020cb03) REAL time: 3 mins 56 secs Phase 12.5 Local Placement Optimization (Checksum:1bfa6c45) REAL time: 4 mins 15 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:a3adcfe9) REAL time: 3 mins 57 secs Phase 13.34 Placement Validation (Checksum:a7b00f1c) REAL time: 4 mins 16 secs
Total REAL time to Placer completion: 5 mins 30 secs Total REAL time to Placer completion: 5 mins 51 secs
Total CPU time to Placer completion: 5 mins 25 secs Total CPU time to Placer completion: 5 mins 43 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net WARNING:PhysDesignRules:372 - Gated clock. Clock net
...@@ -97,19 +97,19 @@ WARNING:PhysDesignRules:367 - The signal ...@@ -97,19 +97,19 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
...@@ -132,14 +132,14 @@ Design Summary: ...@@ -132,14 +132,14 @@ Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 10 Number of warnings: 10
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 11,683 out of 184,304 6% Number of Slice Registers: 11,682 out of 184,304 6%
Number used as Flip Flops: 11,632 Number used as Flip Flops: 11,631
Number used as Latches: 4 Number used as Latches: 4
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 47 Number used as AND/OR logics: 47
Number of Slice LUTs: 16,200 out of 92,152 17% Number of Slice LUTs: 16,151 out of 92,152 17%
Number used as logic: 15,786 out of 92,152 17% Number used as logic: 15,779 out of 92,152 17%
Number using O6 output only: 11,163 Number using O6 output only: 11,156
Number using O5 output only: 843 Number using O5 output only: 843
Number using O5 and O6: 3,780 Number using O5 and O6: 3,780
Number used as ROM: 0 Number used as ROM: 0
...@@ -153,21 +153,21 @@ Slice Logic Utilization: ...@@ -153,21 +153,21 @@ Slice Logic Utilization:
Number using O6 output only: 25 Number using O6 output only: 25
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 38 Number using O5 and O6: 38
Number used exclusively as route-thrus: 327 Number used exclusively as route-thrus: 285
Number with same-slice register load: 220 Number with same-slice register load: 178
Number with same-slice carry load: 107 Number with same-slice carry load: 107
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 6,331 out of 23,038 27% Number of occupied Slices: 6,354 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7% Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,576 Number of LUT Flip Flop pairs used: 18,631
Number with an unused Flip Flop: 7,974 out of 18,576 42% Number with an unused Flip Flop: 7,987 out of 18,631 42%
Number with an unused LUT: 2,376 out of 18,576 12% Number with an unused LUT: 2,480 out of 18,631 13%
Number of fully used LUT-FF pairs: 8,226 out of 18,576 44% Number of fully used LUT-FF pairs: 8,164 out of 18,631 43%
Number of unique control sets: 502 Number of unique control sets: 502
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 1,223 out of 184,304 1% to control set restrictions: 1,224 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -220,8 +220,8 @@ Specific Feature Utilization: ...@@ -220,8 +220,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.79 Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 5 mins 46 secs Total REAL time to MAP completion: 6 mins 7 secs
Total CPU time to MAP completion: 5 mins 40 secs Total CPU time to MAP completion: 5 mins 59 secs
Mapping completed. Mapping completed.
See MAP report file "wr_svec_tdc_map.mrp" for details. See MAP report file "wr_svec_tdc_map.mrp" for details.
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.mrp
View file @ 58de2f4a
...@@ -11,21 +11,21 @@ Target Device : xc6slx150t ...@@ -11,21 +11,21 @@ Target Device : xc6slx150t
Target Package : fgg900 Target Package : fgg900
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 18 12:12:19 2014 Mapped Date : Mon Jun 23 17:22:57 2014
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 10 Number of warnings: 10
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 11,683 out of 184,304 6% Number of Slice Registers: 11,682 out of 184,304 6%
Number used as Flip Flops: 11,632 Number used as Flip Flops: 11,631
Number used as Latches: 4 Number used as Latches: 4
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 47 Number used as AND/OR logics: 47
Number of Slice LUTs: 16,200 out of 92,152 17% Number of Slice LUTs: 16,151 out of 92,152 17%
Number used as logic: 15,786 out of 92,152 17% Number used as logic: 15,779 out of 92,152 17%
Number using O6 output only: 11,163 Number using O6 output only: 11,156
Number using O5 output only: 843 Number using O5 output only: 843
Number using O5 and O6: 3,780 Number using O5 and O6: 3,780
Number used as ROM: 0 Number used as ROM: 0
...@@ -39,21 +39,21 @@ Slice Logic Utilization: ...@@ -39,21 +39,21 @@ Slice Logic Utilization:
Number using O6 output only: 25 Number using O6 output only: 25
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 38 Number using O5 and O6: 38
Number used exclusively as route-thrus: 327 Number used exclusively as route-thrus: 285
Number with same-slice register load: 220 Number with same-slice register load: 178
Number with same-slice carry load: 107 Number with same-slice carry load: 107
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 6,331 out of 23,038 27% Number of occupied Slices: 6,354 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7% Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,576 Number of LUT Flip Flop pairs used: 18,631
Number with an unused Flip Flop: 7,974 out of 18,576 42% Number with an unused Flip Flop: 7,987 out of 18,631 42%
Number with an unused LUT: 2,376 out of 18,576 12% Number with an unused LUT: 2,480 out of 18,631 13%
Number of fully used LUT-FF pairs: 8,226 out of 18,576 44% Number of fully used LUT-FF pairs: 8,164 out of 18,631 43%
Number of unique control sets: 502 Number of unique control sets: 502
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 1,223 out of 184,304 1% to control set restrictions: 1,224 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -106,8 +106,8 @@ Specific Feature Utilization: ...@@ -106,8 +106,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.79 Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 5 mins 46 secs Total REAL time to MAP completion: 6 mins 7 secs
Total CPU time to MAP completion: 5 mins 40 secs Total CPU time to MAP completion: 5 mins 59 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -151,19 +151,19 @@ WARNING:PhysDesignRules:367 - The signal ...@@ -151,19 +151,19 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design. not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
...@@ -183,7 +183,7 @@ Section 3 - Informational ...@@ -183,7 +183,7 @@ Section 3 - Informational
------------------------- -------------------------
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part. INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network VME_BBSY_n_i has no load. INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
INFO:LIT:395 - The above info message is repeated 273 more times for the INFO:LIT:395 - The above info message is repeated 271 more times for the
following (max. 5 shown): following (max. 5 shown):
tdc1_in_fpga_1_i, tdc1_in_fpga_1_i,
tdc1_in_fpga_2_i, tdc1_in_fpga_2_i,
......
hdl/top/spec/no_wrabbit/spec_tdc.vhd
View file @ 58de2f4a
...@@ -290,7 +290,7 @@ architecture rtl of spec_tdc is ...@@ -290,7 +290,7 @@ architecture rtl of spec_tdc is
-- SPEC VCXO clock -- SPEC VCXO clock
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic; signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
-- TDC core clock and reset -- TDC core clock and reset
signal clk_125m : std_logic; signal clk_125m, pll_status : std_logic;
signal rst_125m_n, rst_125m : std_logic; signal rst_125m_n, rst_125m : std_logic;
signal acam_refclk_r_edge_p : std_logic; signal acam_refclk_r_edge_p : std_logic;
-- DAC configuration through PCIe/VME -- DAC configuration through PCIe/VME
...@@ -356,13 +356,14 @@ begin ...@@ -356,13 +356,14 @@ begin
pll_sdi_o => pll_sdi, pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk, pll_sclk_o => pll_sclk,
tdc_125m_clk_o => clk_125m, tdc_125m_clk_o => clk_125m,
pll_status_o => led_green_o); pll_status_o => pll_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_n <= not rst_125m; rst_125m_n <= not rst_125m;
pll_dac_sync_o <= pll_dac_sync; pll_dac_sync_o <= pll_dac_sync;
pll_sdi_o <= pll_sdi; pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk; pll_sclk_o <= pll_sclk;
pll_cs_o <= pll_cs; pll_cs_o <= pll_cs;
led_green_o <= pll_status;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -640,7 +641,7 @@ begin ...@@ -640,7 +641,7 @@ begin
carrier_info_carrier_type_i => c_CARRIER_TYPE, carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i, carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0), carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => '0', carrier_info_stat_sys_pll_lck_i => pll_status,
carrier_info_stat_ddr3_cal_done_i => '0', carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'), carrier_info_stat_reserved_i => (others => '0'),
carrier_info_ctrl_led_green_o => open, carrier_info_ctrl_led_green_o => open,
......
hdl/top/spec/with_wrabbit/wr_spec_tdc.vhd
View file @ 58de2f4a
...@@ -25,7 +25,6 @@ ...@@ -25,7 +25,6 @@
-- the GN4124 core. | -- the GN4124 core. |
-- The carrier_info module provides general information on the SPEC PCB version, PLLs| -- The carrier_info module provides general information on the SPEC PCB version, PLLs|
-- locking state etc. | -- locking state etc. |
-- The 1-Wire core provides communication with the SPEC Thermometer&UniqueID chip. |
-- All the cores communicate with the GN4124 core through the SDB crossbar. The SDB | -- All the cores communicate with the GN4124 core through the SDB crossbar. The SDB |
-- crossbar is responsible for managing the acess to the GN4124 core. | -- crossbar is responsible for managing the acess to the GN4124 core. |
-- | -- |
...@@ -52,21 +51,16 @@ ...@@ -52,21 +51,16 @@
-- \/ | |____________________________| | | | | | | -- \/ | |____________________________| | | | | | |
-- ________ | 62.5MHz | | | | | | -- ________ | 62.5MHz | | | | | |
-- | | | ___________________ | | | | | | -- | | | ___________________ | | | | | |
-- | DAC |<->| | clks rsts manager | | | | | | | -- | DAC |<->| | clks rsts manager | | | | G | | |
-- | PLL | |___________________| | | | | | | -- | PLL | |___________________| | | | | | |
-- | | | ____________________________ _______ | | | | | | -- | | | ____________________________ _______ | S | | N | | |
-- | | | | | | clk | | | | | | | -- | | | | | | clk | | | | | | |
-- | ACAM |<->| | TDC mezzanine |-| cross |<--> | | | | | | -- | ACAM |<->| | TDC mezzanine |-| cross |<--> | | | 4 | | |
-- |________| | |--|____________________________| |_______| | | | G | | | -- |________| | |--|____________________________| |_______| | D | | | | |
-- TDC mezz | | 125MHz 62.5MHz | | | | | | -- TDC mezz | | 125MHz 62.5MHz | | | 1 | | |
-- | | ____________________________ | S | | N | | | -- | | ____________________________ | | | | | |
-- | |->| | | | | | | | -- | |->| | | B | | 2 | | |
-- | | Vector Interrupt Controller| <----------> | D | <--> | 4 | | | -- | | Vector Interrupt Controller| <----------> | | <--> | | | |
-- | |____________________________| | | | | | |
-- | 62.5MHz | B | | 1 | | |
-- | ____________________________ | | | | | |
-- | | | | | | 2 | | |
-- SPEC 1Wire <->| | 1-Wire | <----------> | | | | | |
-- | |____________________________| | | | 4 | | | -- | |____________________________| | | | 4 | | |
-- | 62.5MHz | | | | | | -- | 62.5MHz | | | | | |
-- | ____________________________ | | | | | | -- | ____________________________ | | | | | |
...@@ -294,12 +288,11 @@ architecture rtl of wr_spec_tdc is ...@@ -294,12 +288,11 @@ architecture rtl of wr_spec_tdc is
-- Note: All address in sdb and crossbar are BYTE addresses! -- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar -- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 5; constant c_NUM_WB_MASTERS : integer := 4;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- Carrier onewire interface constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- Info on SPEC control and status registers constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
constant c_WB_SLAVE_VIC : integer := 2; -- Interrupt controller constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
constant c_WB_SLAVE_TDC : integer := 3; -- TDC core configuration constant c_SLAVE_WRCORE : integer := 3; -- White Rabbit PTP core
constant c_SLAVE_WRCORE : integer := 4; -- White Rabbit PTP core
-- SDB header address -- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
...@@ -311,14 +304,13 @@ architecture rtl of wr_spec_tdc is ...@@ -311,14 +304,13 @@ architecture rtl of wr_spec_tdc is
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000"); constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00000000"); constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00000000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) := constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"), (0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"), 1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
2 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg 2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"), 3 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"), 4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
5 => f_sdb_embed_repo_url (c_SDB_REPO_URL), 5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -340,7 +332,8 @@ architecture rtl of wr_spec_tdc is ...@@ -340,7 +332,8 @@ architecture rtl of wr_spec_tdc is
attribute buffer_type of clk_125m_pllref : signal is "BUFG"; attribute buffer_type of clk_125m_pllref : signal is "BUFG";
-- TDC core clocks and resets -- TDC core clocks and resets
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic; signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
signal clk_62m5_sys, clk_125m_mezz : std_logic; signal clk_62m5_sys, sys_locked : std_logic;
signal clk_125m_mezz, pll_mezz_status : std_logic;
signal rst_125m_mezz_n, rst_125m_mezz : std_logic; signal rst_125m_mezz_n, rst_125m_mezz : std_logic;
signal acam_refclk_r_edge_p : std_logic; signal acam_refclk_r_edge_p : std_logic;
signal rst_sys, rst_sys_n : std_logic; signal rst_sys, rst_sys_n : std_logic;
...@@ -464,7 +457,7 @@ begin ...@@ -464,7 +457,7 @@ begin
CLKOUT3 => open, CLKOUT3 => open,
CLKOUT4 => open, CLKOUT4 => open,
CLKOUT5 => open, CLKOUT5 => open,
LOCKED => open, LOCKED => sys_locked,
RST => '0', RST => '0',
CLKFBIN => pllout_clk_fb_pllref, CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_20m_vcxo); CLKIN => clk_20m_vcxo);
...@@ -518,7 +511,7 @@ begin ...@@ -518,7 +511,7 @@ begin
pll_sdi_o => pll_sdi, pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk, pll_sclk_o => pll_sclk,
tdc_125m_clk_o => clk_125m_mezz, tdc_125m_clk_o => clk_125m_mezz,
pll_status_o => open); pll_status_o => pll_mezz_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_mezz_n <= not rst_125m_mezz; rst_125m_mezz_n <= not rst_125m_mezz;
pll_dac_sync_o <= pll_dac_sync; pll_dac_sync_o <= pll_dac_sync;
...@@ -1064,9 +1057,9 @@ begin ...@@ -1064,9 +1057,9 @@ begin
carrier_info_carrier_type_i => c_CARRIER_TYPE, carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i, carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0), carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => '0', carrier_info_stat_sys_pll_lck_i => pll_mezz_status,
carrier_info_stat_ddr3_cal_done_i => '0', carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'), carrier_info_stat_reserved_i => x"000000" & "000" & sys_locked,
carrier_info_ctrl_led_green_o => open, carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open, carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open, carrier_info_ctrl_dac_clr_n_o => open,
......
hdl/top/svec/no_wrabbit/svec_tdc.vhd
View file @ 58de2f4a
...@@ -97,13 +97,13 @@ ...@@ -97,13 +97,13 @@
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) | -- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 05/2014 | -- Date 05/2014 |
-- Version v2 | -- Version v5 |
-- Depends on | -- Depends on |
-- | -- |
---------------- | ---------------- |
-- Last changes | -- Last changes |
-- 08/2013 v1 EG design for SVEC; two cores; synchronizer between vme and the cores | -- 08/2013 v4 EG design for SVEC; two cores; synchronizer between vme and the cores |
-- 05/2014 v2 EG added White Rabbit | -- 05/2014 v5 EG added White Rabbit |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -351,7 +351,7 @@ architecture rtl of svec_tdc is ...@@ -351,7 +351,7 @@ architecture rtl of svec_tdc is
signal clk_62m5_sys, pllout_clk_sys : std_logic; signal clk_62m5_sys, pllout_clk_sys : std_logic;
signal pllout_clk_sys_fb, sys_locked : std_logic; signal pllout_clk_sys_fb, sys_locked : std_logic;
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1: tdc1_125m_clk -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1: tdc1_125m_clk
signal tdc1_125m_clk : std_logic; signal tdc1_125m_clk, tdc1_pll_status : std_logic;
signal tdc1_acam_refclk_r_edge_p : std_logic; signal tdc1_acam_refclk_r_edge_p : std_logic;
signal tdc1_send_dac_word_p : std_logic; signal tdc1_send_dac_word_p : std_logic;
signal tdc1_dac_word : std_logic_vector(23 downto 0); signal tdc1_dac_word : std_logic_vector(23 downto 0);
...@@ -360,7 +360,7 @@ architecture rtl of svec_tdc is ...@@ -360,7 +360,7 @@ architecture rtl of svec_tdc is
signal tdc1_irq_acam_err_p : std_logic; signal tdc1_irq_acam_err_p : std_logic;
signal tdc1_irq_tstamp_p, tdc1_irq_time_p : std_logic; signal tdc1_irq_tstamp_p, tdc1_irq_time_p : std_logic;
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC2: tdc2_125m_clk -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC2: tdc2_125m_clk
signal tdc2_125m_clk : std_logic; signal tdc2_125m_clk, tdc2_pll_status : std_logic;
signal tdc2_acam_refclk_r_edge_p : std_logic; signal tdc2_acam_refclk_r_edge_p : std_logic;
signal tdc2_send_dac_word_p : std_logic; signal tdc2_send_dac_word_p : std_logic;
signal tdc2_dac_word : std_logic_vector(23 downto 0); signal tdc2_dac_word : std_logic_vector(23 downto 0);
...@@ -542,7 +542,7 @@ begin ...@@ -542,7 +542,7 @@ begin
pll_sdi_o => tdc1_pll_sdi_o, pll_sdi_o => tdc1_pll_sdi_o,
pll_sclk_o => tdc1_pll_sclk_o, pll_sclk_o => tdc1_pll_sclk_o,
tdc_125m_clk_o => tdc1_125m_clk, tdc_125m_clk_o => tdc1_125m_clk,
pll_status_o => open); pll_status_o => tdc1_pll_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc1_general_rst_n <= not tdc1_general_rst; tdc1_general_rst_n <= not tdc1_general_rst;
tdc1_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys; tdc1_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys;
...@@ -574,7 +574,7 @@ begin ...@@ -574,7 +574,7 @@ begin
pll_sdi_o => tdc2_pll_sdi_o, pll_sdi_o => tdc2_pll_sdi_o,
pll_sclk_o => tdc2_pll_sclk_o, pll_sclk_o => tdc2_pll_sclk_o,
tdc_125m_clk_o => tdc2_125m_clk, tdc_125m_clk_o => tdc2_125m_clk,
pll_status_o => open); pll_status_o => tdc2_pll_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc2_general_rst_n <= not tdc2_general_rst; tdc2_general_rst_n <= not tdc2_general_rst;
tdc2_soft_rst_n <= carrier_info_fmc_rst(1) and rst_n_sys; tdc2_soft_rst_n <= carrier_info_fmc_rst(1) and rst_n_sys;
...@@ -927,11 +927,11 @@ begin ...@@ -927,11 +927,11 @@ begin
carrier_info_carrier_pcb_rev_i => pcb_ver_i, carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'), carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE, carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => '0', -- put tdc1_prsnt_m2c_n_i carrier_info_stat_fmc_pres_i => tdc1_prsntm2c_n_i,
carrier_info_stat_p2l_pll_lck_i => '0', carrier_info_stat_p2l_pll_lck_i => '0',
carrier_info_stat_sys_pll_lck_i => sys_locked, carrier_info_stat_sys_pll_lck_i => sys_locked,
carrier_info_stat_ddr3_cal_done_i => '0', carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'), carrier_info_stat_reserved_i => x"000000" & "000" & tdc2_prsntm2c_n_i, -- & tdc2_pll_status & tdc1_pll_status & tdc2_prsntm2c_n_i,
carrier_info_ctrl_led_green_o => open, carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open, carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open, carrier_info_ctrl_dac_clr_n_o => open,
......
hdl/top/svec/with_wrabbit/wr_svec_tdc.vhd
View file @ 58de2f4a
...@@ -22,7 +22,6 @@ ...@@ -22,7 +22,6 @@
-- o The VIC is managing the interrupts coming from both TDC EIC cores | -- o The VIC is managing the interrupts coming from both TDC EIC cores |
-- o The carrier_info module provides general information on the SVEC PCB version, | -- o The carrier_info module provides general information on the SVEC PCB version, |
-- PLLs locking state etc | -- PLLs locking state etc |
-- o The 1-Wire core provides communication with the SVEC Thermometer&UniqueID chip|
-- All these cores communicate with the VME core through the WISHBONE. | -- All these cores communicate with the VME core through the WISHBONE. |
-- The SDB crossbar is mapping the different slaves into the WISHBONE address space. | -- The SDB crossbar is mapping the different slaves into the WISHBONE address space. |
-- | -- |
...@@ -78,11 +77,6 @@ ...@@ -78,11 +77,6 @@
-- | | VIC | ---- | B | | E | | | -- | | VIC | ---- | B | | E | | |
-- | |____________________________| | | | | | | -- | |____________________________| | | | | | |
-- | 62.5MHz | | | | | | -- | 62.5MHz | | | | | |
-- | ____________________________ | | | | | |
-- | | | | | | | | |
-- SVEC 1W chip | | 1-Wire | ---- | | | | | |
-- | |____________________________| | | | | | |
-- | 62.5MHz / | | | | | |
-- | ____________________________ / | | | | | | -- | ____________________________ / | | | | | |
-- | | | / | | | | | | -- | | | / | | | | | |
-- | | carrier_info | / | | | | | | -- | | carrier_info | / | | | | | |
...@@ -337,30 +331,28 @@ architecture rtl of wr_svec_tdc is ...@@ -337,30 +331,28 @@ architecture rtl of wr_svec_tdc is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Constants regarding the SDB crossbar -- Constants regarding the SDB crossbar
constant c_NUM_WB_SLAVES : integer := 1; constant c_NUM_WB_SLAVES : integer := 1;
constant c_NUM_WB_MASTERS : integer := 6; constant c_NUM_WB_MASTERS : integer := 5;
constant c_MASTER_VME : integer := 0; constant c_MASTER_VME : integer := 0;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant c_SLAVE_SVEC_1W : integer := 0; -- SVEC 1wire interface constant c_SLAVE_SVEC_INFO : integer := 0; -- SVEC carrier info
constant c_SLAVE_SVEC_INFO : integer := 1; -- SVEC carrier info constant c_SLAVE_VIC : integer := 1; -- Vector Interrupt controller
constant c_SLAVE_VIC : integer := 2; -- Vector Interrupt controller constant c_SLAVE_TDC0 : integer := 2; -- TDC mezzanine #1
constant c_SLAVE_TDC0 : integer := 3; -- TDC mezzanine #1 constant c_SLAVE_TDC1 : integer := 3; -- TDC mezzanine #2
constant c_SLAVE_TDC1 : integer := 4; -- TDC mezzanine #2 constant c_SLAVE_WRCORE : integer := 4; -- White Rabbit PTP core
constant c_SLAVE_WRCORE : integer := 5; -- White Rabbit PTP core
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000"); constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_FMC_TDC2_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000"); constant c_FMC_TDC2_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000"); constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(7 downto 0) := constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"), (0 => f_sdb_embed_device (c_SVEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_SVEC_INFO_SDB_DEVICE, x"00020000"), 1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"),
2 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), 2 => f_sdb_embed_bridge (c_FMC_TDC1_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_FMC_TDC1_SDB_BRIDGE, x"00040000"), 3 => f_sdb_embed_bridge (c_FMC_TDC2_SDB_BRIDGE, x"00060000"),
4 => f_sdb_embed_bridge (c_FMC_TDC2_SDB_BRIDGE, x"00060000"), 4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
5 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"), 5 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
6 => f_sdb_embed_repo_url (c_SDB_REPO_URL), 6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
7 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -383,7 +375,7 @@ architecture rtl of wr_svec_tdc is ...@@ -383,7 +375,7 @@ architecture rtl of wr_svec_tdc is
signal clk_62m5_sys, pllout_clk_sys : std_logic; signal clk_62m5_sys, pllout_clk_sys : std_logic;
signal pllout_clk_sys_fb, sys_locked : std_logic; signal pllout_clk_sys_fb, sys_locked : std_logic;
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1: tdc1_125m_clk -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1: tdc1_125m_clk
signal tdc1_125m_clk : std_logic; signal tdc1_125m_clk, tdc1_pll_status : std_logic;
signal tdc1_acam_refclk_r_edge_p : std_logic; signal tdc1_acam_refclk_r_edge_p : std_logic;
signal tdc1_send_dac_word_p : std_logic; signal tdc1_send_dac_word_p : std_logic;
signal tdc1_dac_word : std_logic_vector(23 downto 0); signal tdc1_dac_word : std_logic_vector(23 downto 0);
...@@ -392,7 +384,7 @@ architecture rtl of wr_svec_tdc is ...@@ -392,7 +384,7 @@ architecture rtl of wr_svec_tdc is
signal tdc1_irq_acam_err_p : std_logic; signal tdc1_irq_acam_err_p : std_logic;
signal tdc1_irq_tstamp_p, tdc1_irq_time_p : std_logic; signal tdc1_irq_tstamp_p, tdc1_irq_time_p : std_logic;
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC2: tdc2_125m_clk -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC2: tdc2_125m_clk
signal tdc2_125m_clk : std_logic; signal tdc2_125m_clk, tdc2_pll_status : std_logic;
signal tdc2_acam_refclk_r_edge_p : std_logic; signal tdc2_acam_refclk_r_edge_p : std_logic;
signal tdc2_send_dac_word_p : std_logic; signal tdc2_send_dac_word_p : std_logic;
signal tdc2_dac_word : std_logic_vector(23 downto 0); signal tdc2_dac_word : std_logic_vector(23 downto 0);
...@@ -608,7 +600,7 @@ begin ...@@ -608,7 +600,7 @@ begin
pll_sdi_o => tdc1_pll_sdi_o, pll_sdi_o => tdc1_pll_sdi_o,
pll_sclk_o => tdc1_pll_sclk_o, pll_sclk_o => tdc1_pll_sclk_o,
tdc_125m_clk_o => tdc1_125m_clk, tdc_125m_clk_o => tdc1_125m_clk,
pll_status_o => open); pll_status_o => tdc1_pll_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc1_general_rst_n <= not tdc1_general_rst; tdc1_general_rst_n <= not tdc1_general_rst;
tdc1_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys; tdc1_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys;
...@@ -640,7 +632,7 @@ begin ...@@ -640,7 +632,7 @@ begin
pll_sdi_o => tdc2_pll_sdi_o, pll_sdi_o => tdc2_pll_sdi_o,
pll_sclk_o => tdc2_pll_sclk_o, pll_sclk_o => tdc2_pll_sclk_o,
tdc_125m_clk_o => tdc2_125m_clk, tdc_125m_clk_o => tdc2_125m_clk,
pll_status_o => open); pll_status_o => tdc2_pll_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc2_general_rst_n <= not tdc2_general_rst; tdc2_general_rst_n <= not tdc2_general_rst;
tdc2_soft_rst_n <= carrier_info_fmc_rst(1) and rst_n_sys; tdc2_soft_rst_n <= carrier_info_fmc_rst(1) and rst_n_sys;
...@@ -1236,11 +1228,11 @@ begin ...@@ -1236,11 +1228,11 @@ begin
carrier_info_carrier_pcb_rev_i => pcb_ver_i, carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'), carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE, carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => '0', -- put tdc1_prsnt_m2c_n_i carrier_info_stat_fmc_pres_i => tdc1_prsntm2c_n_i,
carrier_info_stat_p2l_pll_lck_i => '0', carrier_info_stat_p2l_pll_lck_i => '0',
carrier_info_stat_sys_pll_lck_i => sys_locked, carrier_info_stat_sys_pll_lck_i => sys_locked,
carrier_info_stat_ddr3_cal_done_i => '0', carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'), carrier_info_stat_reserved_i => x"000000" & "000" & tdc2_prsntm2c_n_i, --& tdc2_pll_status & tdc1_pll_status & tdc2_prsntm2c_n_i,
carrier_info_ctrl_led_green_o => open, carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open, carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open, carrier_info_ctrl_dac_clr_n_o => open,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment