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FMC TDC 1ns 5cha
Commit 52491468 authored by egousiou's avatar egousiou
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- changed IOBs settings (map -pr) on svec tdc; now no extra cycle needed in the… 

- changed IOBs settings (map -pr) on svec tdc; now no extra cycle needed in the acam_databus_interface.vhd for the ef, rd_n communication with the acam.
- added comments and architecture drawings on top of the modules 

git-svn-id: http://svn.ohwr.org/fmc-tdc@114 85dfdc96-de2c-444c-878d-45b388be74a9
parent 95b4c5fa
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hdl/svec/hdl/rtl/acam_databus_interface.vhd
View file @ 52491468
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hdl/svec/hdl/rtl/acam_timecontrol_interface.vhd
View file @ 52491468
......@@ -12,7 +12,7 @@
---------------------------------------------------------------------------------------------------
-- File acam_timecontrol_interface.vhd |
-- |
-- Description interface with the acam chip pins for control and timing |
-- Description interface with the ACAM chip pins for control and timing |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
......@@ -72,11 +72,10 @@ entity acam_timecontrol_interface is
-- reg 11 is set to report for any HitFIFOs full flags
int_flag_i : in std_logic; -- ACAM interrupt flag, active HIGH; through ACAM config
-- reg 12 it is set to the MSB of Start#
-- Signals from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- signal from PCIe to start following the ACAM chip
activate_acq_p_i : in std_logic; -- signal from PCIe/VME to start following the ACAM chip
-- for tstamps aquisition
window_delay_i : in std_logic_vector(31 downto 0); -- eva: don t know yet:s
window_delay_i : in std_logic_vector(31 downto 0); -- eva: not needed
-- OUTPUTS
......@@ -198,7 +197,6 @@ begin
end process;
-- Synchronization of the activate_acq_p with the acam_refclk_p_i
ready_to_trigger: process (clk_i)
begin
......@@ -217,7 +215,6 @@ begin
end process;
actual_trigger_received: process (clk_i) -- signal needed to exclude the generation of
begin -- the start_from_fpga_o after a general rst_i
if rising_edge (clk_i) then
......@@ -235,7 +232,6 @@ begin
end process;
inputs_synchronizer: process (clk_i)
begin
if rising_edge (clk_i) then
......
hdl/svec/hdl/rtl/circular_buffer.vhd
View file @ 52491468
......@@ -17,9 +17,9 @@
-- o The data_formatting unit is writing 128-bit long timestamps, using a WISHBONE |
-- classic interface. The unit implements a WISHBONE classic slave. |
-- As figure 1 indicates, from this side the memory is of size: 255 * 128. |
-- o The GNUM core is reading 32-bit words. Readings take place using a pipelined |
-- WISHBONE interface, allowing for Direct Memory Access from the PCI-e. |
-- The unit implements a WISHBONE pipelined slave. |
-- o The GNUM/VME core is reading 32-bit words. Readings take place using pipelined |
-- WISHBONE interface. For the PCi-e interface, Direct Memory Access can take |
-- place on this side. The unit implements the WISHBONE pipelined slave. |
-- As figure 1 indicates, from this side the memory is of size: 1024 * 32. |
-- |
-- Note also that in principle the data_formatting unit is only writing in the RAM |
......@@ -27,7 +27,7 @@
-- |
-- |
-- RAM as seen from the RAM as seen from the |
-- data_formatting unit GNUM core |
-- data_formatting unit GNUM/VME core |
-- ____________________________________________________________ _______________ |
-- 0 | 128 bits | 0 | 32 bits | |
-- |____________________________________________________________| |_______________| |
......@@ -105,33 +105,33 @@ entity circular_buffer is
port
-- INPUTS
-- Signal from the clk_rst_manager
(clk_i : in std_logic; -- 125 MHz clock; same for both ports
(clk_i : in std_logic; -- 125 MHz clock; same for both ports
-- Signals from the data_formatting unit (WISHBONE classic): timestamps writing
tstamp_wr_rst_i : in std_logic; -- timestamp writing WISHBONE reset
tstamp_wr_stb_i : in std_logic; -- timestamp writing WISHBONE strobe
tstamp_wr_cyc_i : in std_logic; -- timestamp writing WISHBONE cycle
tstamp_wr_we_i : in std_logic; -- timestamp writing WISHBONE write enable
tstamp_wr_adr_i : in std_logic_vector(7 downto 0); -- adr 8 bits long 2^8 = 255
tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- timestamp 128 bits long
-- Signals from the GNUM core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_rst_i : in std_logic; -- timestamp reading WISHBONE reset
tdc_mem_wb_stb_i : in std_logic; -- timestamp reading WISHBONE strobe
tdc_mem_wb_cyc_i : in std_logic; -- timestamp reading WISHBONE cycle
tdc_mem_wb_we_i : in std_logic; -- timestamp reading WISHBONE write enable; not used
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0); -- adr 10 bits long 2^10 = 1024
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0); -- not used
tstamp_wr_rst_i : in std_logic; -- timestamp writing WISHBONE reset
tstamp_wr_stb_i : in std_logic; -- timestamp writing WISHBONE strobe
tstamp_wr_cyc_i : in std_logic; -- timestamp writing WISHBONE cycle
tstamp_wr_we_i : in std_logic; -- timestamp writing WISHBONE write enable
tstamp_wr_adr_i : in std_logic_vector(7 downto 0); -- adr 8 bits long 2^8 = 255
tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- timestamp 128 bits long
-- Signals from the GNUM/VME core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_rst_i : in std_logic; -- timestamp reading WISHBONE reset
tdc_mem_wb_stb_i : in std_logic; -- timestamp reading WISHBONE strobe
tdc_mem_wb_cyc_i : in std_logic; -- timestamp reading WISHBONE cycle
tdc_mem_wb_we_i : in std_logic; -- timestamp reading WISHBONE write enable; not used
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0); -- adr 10 bits long 2^10 = 1024
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0); -- not used
-- OUTPUTS
-- Signals to the data_formatting unit (WISHBONE classic): timestamps writing
tstamp_wr_ack_p_o : out std_logic; -- timestamp writing WISHBONE classic acknowledge
tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- not used
tstamp_wr_ack_p_o : out std_logic; -- timestamp writing WISHBONE classic acknowledge
tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- not used
-- Signals to the GNUM core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pepelined acknowledge
-- Signals to the GNUM/VME core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pepelined acknowledge
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- 32 bit words
tdc_mem_wb_stall_o : out std_logic);-- timestamp reading WISHBONE pipelined stall
tdc_mem_wb_stall_o : out std_logic); -- timestamp reading WISHBONE pipelined stall
end circular_buffer;
......@@ -159,7 +159,7 @@ begin
begin
if rising_edge (clk_i) then
if tstamp_wr_rst_i ='1' then
--tstamp_wr_ack_p <= '0';
tstamp_wr_ack_p <= '0';
elsif tstamp_wr_stb_i = '1' and tstamp_wr_cyc_i = '1' and tstamp_wr_ack_p = '0' then
tstamp_wr_ack_p <= '1'; -- a new 1 clk-wide ack is given for each stb
......@@ -173,7 +173,6 @@ begin
tstamp_wr_ack_p_o <= tstamp_wr_ack_p;
---------------------------------------------------------------------------------------------------
-- TIMESTAMP READINGS WISHBONE PIPELINE ACK --
---------------------------------------------------------------------------------------------------
......@@ -285,38 +284,19 @@ begin
-- Port B: attached to the GNUM/VME_core unit
clkb => clk_i,
addrb => tdc_mem_wb_adr_i(9 downto 0), -- 2^10 = 1024 addresses
dinb => tdc_mem_wb_dat_i, -- not used
addrb => tdc_mem_wb_adr_i(9 downto 0),-- 2^10 = 1024 addresses
dinb => tdc_mem_wb_dat_i, -- not used
enb => tdc_mem_wb_cyc_i,
web => tstamp_rd_we, -- not used
web => tstamp_rd_we, -- not used
--------------------------------------------------
doutb => tdc_mem_wb_dat_o); -- 32-bit long words
doutb => tdc_mem_wb_dat_o); -- 32-bit long words
--------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tstamp_wr_we(0) <= tstamp_wr_we_i;
tstamp_rd_we(0) <= tdc_mem_wb_we_i;
---------------------------------------------------------------------------------------------------
-- Dummy reading --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- dummy0_ack_generator: process (clk_i)
-- begin
-- if rising_edge (clk_i) then
-- if tdc_mem_wb_rst_i ='1' then
-- tdc_mem_wb_ack_o <= '0';
-- else
-- tdc_mem_wb_ack_o <= tdc_mem_wb_stb_i and tdc_mem_wb_cyc_i;
-- end if;
-- end if;
-- end process;
-- tdc_mem_wb_stall_o <= '0';
end architecture rtl;
--=================================================================================================
-- architecture end
......
hdl/svec/hdl/rtl/clks_rsts_manager.vhd
View file @ 52491468
......@@ -12,7 +12,7 @@
---------------------------------------------------------------------------------------------------
-- File clks_rsts_manager.vhd |
-- |
-- Description Independent block that uses the clk_20m_vcxo_i_i to parameterize the TDC mezzanine |
-- Description Independent block that uses the clk_20m_vcxo_i to parameterize the TDC mezzanine |
-- PLL and DAC that will be used by all the other blocks. |
-- Includes input clk buffers for Xilinx Spartan6. |
-- |
......@@ -72,42 +72,43 @@ entity clks_rsts_manager is
port
-- INPUTS
-- Clock signal from carrier board
(clk_20m_vcxo_i : in std_logic; -- 20 MHz OSC on carrier board
(clk_20m_vcxo_i : in std_logic; -- 20 MHz OSC on carrier board
-- Clock signals from the TDC mezzanine PLL
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock generated by the mezzanine PLL, same as ACAM's input clock
acam_refclk_n_i : in std_logic;
tdc_125m_clk_p_i : in std_logic; -- 125 MHz clock generated by the mezzanine PLL, clock of all other TDC core logic
tdc_125m_clk_n_i : in std_logic;
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock generated by
acam_refclk_n_i : in std_logic; -- the mezzanine PLL, same as ACAM's input clock
tdc_125m_clk_p_i : in std_logic; -- 125 MHz clock generated by the mezzanine PLL,
tdc_125m_clk_n_i : in std_logic; -- clock of all other TDC core logic
-- Other signals from the TDC mezzanine PLL
pll_status_i : in std_logic; -- PLL lock detect
pll_sdo_i : in std_logic; -- not used
pll_status_i : in std_logic; -- PLL lock detect
pll_sdo_i : in std_logic; -- not used
-- Reset signal from the PCIe/ VME interface
rst_n_i : in std_logic; -- GNUM/VME interface reset
-- Reset signal from the PCIe/VME interface
rst_n_i : in std_logic; -- GNUM/VME interface reset
-- Signals from the reg_ctrl unit for the reconfiguration of the DAC
send_dac_word_p_i : in std_logic; -- pulse upon VME request for a DAC reconfiguration
send_dac_word_p_i : in std_logic; -- pulse upon VME request for a DAC reconfiguration
dac_word_i : in std_logic_vector(23 downto 0); -- DAC Vout = Vref (dac_word/65536)
-- OUTPUTS
-- Signals to the rest of the modules of the TDC core
tdc_125m_clk_o : out std_logic; -- 125 MHZ clock
internal_rst_o : out std_logic; -- global reset, synched to tdc_125m_clk_o, asserted until the 125 MHZ clock from the PLL is available
tdc_125m_clk_o : out std_logic; -- 125 MHZ clock
internal_rst_o : out std_logic; -- global reset, synched to tdc_125m_clk_o,
-- /!\ asserted until the 125 MHZ clock from the PLL becomes available
-- Signals to the SPI interface for the PLL and DAC
pll_cs_n_o : out std_logic; -- SPI PLL chip select
pll_dac_sync_n_o : out std_logic; -- SPI DAC chip select
pll_sdi_o : out std_logic; -- SPI data
pll_sclk_o : out std_logic; -- SPI clock
pll_cs_n_o : out std_logic; -- SPI PLL chip select
pll_dac_sync_n_o : out std_logic; -- SPI DAC chip select
pll_sdi_o : out std_logic; -- SPI data
pll_sclk_o : out std_logic; -- SPI clock
-- Signal to the one_hz_gen and acam_timecontrol_interface units
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk rising edge
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk rising edge
-- Signal to the leds_manager unit
pll_status_o : out std_logic);-- PLL lock detect synched with 20 MHz clock
pll_status_o : out std_logic); -- PLL lock detect synched with 20 MHz clock
end clks_rsts_manager;
......@@ -260,12 +261,10 @@ begin
port map
(O => tdc_clk,
I => tdc_clk_buf);
-- -- -- -- -- -- -- --
tdc_125m_clk_o <= tdc_clk;
---------------------------------------------------------------------------------------------------
-- Global Internal Reset --
---------------------------------------------------------------------------------------------------
......@@ -287,7 +286,6 @@ begin
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Synchronous process pll_status_synchronizer: Synchronization of the pll_status_i input to the
-- clk_20m_vcxo_i, using a set of 2 registers.
......@@ -316,7 +314,7 @@ begin
if rst_in_synch(1) = '1' then
rst <= '1';
else
if pll_status_synch(1) = '1' then --pll_status_i = '1' then
if pll_status_synch(1) = '1' then
if rst_cnt = "11111111" then
rst <= '0';
else
......@@ -359,12 +357,6 @@ begin
I => acam_refclk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => acam_refclk_n_i);-- Diff_n buffer input (connect directly to top-level port)
--acam_refclk31M25_gbuf : BUFG
--port map
--(O => acam_refclk,
--I => );
---------------------------------------------------------------------------------------------------
acam_refclk_synchronizer: process (tdc_clk)
begin
......
hdl/svec/hdl/rtl/data_engine.vhd
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hdl/svec/hdl/rtl/data_formatting.vhd
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......@@ -12,15 +12,18 @@
---------------------------------------------------------------------------------------------------
-- File data_formatting.vhd |
-- |
-- Description timestamp data formatting. |
-- formats the timestamp coming from the ACAM plus the coarse timing |
-- plus the UTC time and writes it to the circular buffer |
-- Description Timestamp data formatting. |
-- Formats in a 128-bit word the |
-- o fine timestamps coming directly from the ACAM |
-- o plus the coarse timing internally measured in the core |
-- o plus the UTC time internally kept in the core |
-- and writes the word to the circular buffer |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2013 |
-- Version v2 |
-- Version v2.1 |
-- Depends on |
-- |
---------------- |
......@@ -31,6 +34,8 @@
-- second; fixed bug on rollover that is a bit delayed wrt ACAM IrFlag |
-- 07/2013 v2 EG Cleaner writing with adition of intermediate DFF on the acam_tstamp |
-- calculations |
-- 09/2013 v2.1 EG added wr_index clearing upon dacapo_c_rst_p_i pulse; before only the |
-- dacapo_counter was being reset with the dacapo_c_rst_p_i |
-- |
---------------------------------------------------------------------------------------------------
......@@ -84,7 +89,7 @@ entity data_formatting is
-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
-- Signals from the reg_ctrl unit
dacapo_c_rst_p_i : in std_logic; -- instruction from PCIe to clear dacapo flag
dacapo_c_rst_p_i : in std_logic; -- instruction from PCIe/VME to clear dacapo flag
-- Signals from the one_hz_gen unit
local_utc_i : in std_logic_vector(31 downto 0); -- local UTC time
......@@ -115,7 +120,7 @@ entity data_formatting is
-- Signal to the reg_ctrl unit
wr_index_o : out std_logic_vector(31 downto 0)); -- index of last byte written
-- note that the index is provided
-- #bytes, as the PCIe expects
-- #bytes, as the PCIe/VME expects
-- (not in #128-bits-words)
end data_formatting;
......@@ -145,12 +150,11 @@ architecture rtl of data_formatting is
signal dacapo_counter : unsigned(19 downto 0);
signal wr_index : unsigned(7 downto 0);
-- coarse time calculations
signal belongs_to_previous_sec, tstamp_on_first_retrig_case1: std_logic;
signal tstamp_on_first_retrig_case1 : std_logic;
signal tstamp_on_first_retrig_case2 : std_logic;
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
signal un_previous_roll_over_nb : unsigned(31 downto 0);
signal un_current_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_current_retrig_nb_offset, un_current_roll_over_nb : unsigned(31 downto 0);
signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time :unsigned(31 downto 0);
......@@ -209,7 +213,7 @@ begin
tstamp_wr_wb_adr: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' then
if rst_i ='1' or dacapo_c_rst_p_i = '1' then
wr_index <= (others => '0');
elsif tstamp_wr_cyc = '1' and tstamp_wr_stb = '1' and tstamp_wr_we = '1' and tstamp_wr_wb_ack_i = '1' then
......@@ -235,7 +239,7 @@ begin
-- Da Capo flag --
---------------------------------------------------------------------------------------------------
-- dacapo_counter_update: the Da Capo counter indicates the number of times the circular buffer
-- has been written completely; it can be cleared by the PCIe host.
-- has been written completely; it can be cleared by the PCIe/VME host.
dacapo_counter_update: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -279,7 +283,7 @@ begin
-- [95:64] Local UTC time coming from the one_hz_generator;
-- each bit represents 1s
-- [127:96] Metadata for each timestamp: "00..00" & 0 & ef & Slope & Channel
-- [127:96] Metadata for each timestamp: Slope(rising or falling tstamp), Channel
tstamp_formatting: process (clk_i) -- ACAM data handling DFF #2 (DFF #1 refers to the registering of the acam_tstamp1/2_ok_p)
begin
......@@ -346,7 +350,6 @@ begin
un_acam_fine_time <= unsigned(fine_time);
acam_start_nb_32 <= x"000000" & acam_start_nb;
un_acam_start_nb <= unsigned(acam_start_nb_32);
un_current_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
un_current_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
un_current_roll_over_nb <= unsigned(roll_over_nb_i);
un_current_retrig_from_roll_over <= shift_left(un_current_roll_over_nb-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192
......@@ -414,8 +417,6 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- the number of internal start retriggers actually occurred is calculated by subtracting the offset number
-- already present when the one_hz_pulse arrives, and adding the start nb provided by the ACAM.
......@@ -438,9 +439,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- metadata: information about the timestamp
metadata <= acam_start_nb & retrig_nb_offset_i(15 downto 0) & -- for debugging (24 MSbits)
belongs_to_previous_sec & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
acam_slope & "0" & acam_channel; -- 5 LSbits
metadata <= acam_start_nb & retrig_nb_offset_i(15 downto 0) & -- for debugging (24 MSbits)
acam_fifo_ef & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
acam_slope & "0" & acam_channel; -- 5 LSbits
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
full_timestamp(31 downto 0) <= fine_time;
......
hdl/svec/hdl/rtl/decr_counter.vhd
View file @ 52491468
......@@ -7,15 +7,15 @@
---------------------------------------------------------------------------------------------------
-- |
-- decr_counter |
-- decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File decr_counter.vhd |
-- |
-- Description Stop counter. Configurable counter_top_i and width. |
-- Current count counter and done signal available. |
-- Done signal asserted simultaneous to counter=0. |
-- Countdown is launched each time counter_load_i is asserted for one clock tick. |
-- Description Stop counter. Configurable "counter_top_i" and "width". |
-- "Current count value" and "counting done" signals available. |
-- "Counter done" signal asserted simultaneous to "current count value = 0". |
-- Countdown is launched each time "counter_load_i" is asserted for one clock tick. |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
......@@ -63,7 +63,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
entity decr_counter is
generic
(width : integer := 32); -- default size
(width : integer := 32); -- default size
port
-- INPUTS
-- Signals from the clk_rst_manager
......@@ -71,14 +71,14 @@ entity decr_counter is
rst_i : in std_logic;
-- Signals from any unit
counter_load_i : in std_logic; -- loads counter with counter_top_i value
counter_load_i : in std_logic; -- loads counter with counter_top_i value
counter_top_i : in std_logic_vector(width-1 downto 0); -- counter start value
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic); -- counter empty indication
counter_is_zero_o : out std_logic); -- counter empty indication
end decr_counter;
......@@ -126,9 +126,11 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= std_logic_vector(counter);
one <= zeroes + "1";
end architecture rtl;
--=================================================================================================
-- architecture end
......
hdl/svec/hdl/rtl/fmc_tdc_core.vhd
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hdl/svec/hdl/rtl/fmc_tdc_mezzanine.vhd
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hdl/svec/hdl/rtl/free_counter.vhd
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......@@ -12,9 +12,9 @@
---------------------------------------------------------------------------------------------------
-- File free_counter.vhd |
-- |
-- Description Free running counter. Configurable counter_top_i and width. |
-- Current count counter and done signal available. |
-- Done signal asserted simultaneous to counter=0. |
-- Description Free running counter. Configurable "counter_top_i" and "width". |
-- "Current count value" and "counting done" signal available. |
-- "Counting done" signal asserted simultaneous to "current count value = 0". |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
......@@ -61,7 +61,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
entity free_counter is
generic
(width : integer := 32); -- default size
(width : integer := 32); -- default size
port
-- INPUTS
-- Signals from the clk_rst_manager
......@@ -69,14 +69,14 @@ entity free_counter is
rst_i : in std_logic;
-- Signals from any unit
counter_en_i : in std_logic; -- enables counting
counter_en_i : in std_logic; -- enables counting
counter_top_i : in std_logic_vector(width-1 downto 0); -- start value;
-- when zero is reached counter reloads
-- start value and restarts counting
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic); -- empty counter indication
counter_is_zero_o : out std_logic); -- empty counter indication
end free_counter;
......@@ -89,6 +89,7 @@ architecture rtl of free_counter is
constant zeroes : unsigned(width-1 downto 0):=(others=>'0');
signal counter : unsigned(width-1 downto 0):=(others=>'0'); -- init to avoid sim warnings
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -118,8 +119,10 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= std_logic_vector(counter);
end architecture rtl;
--=================================================================================================
-- architecture end
......
hdl/svec/hdl/rtl/incr_counter.vhd
View file @ 52491468
......@@ -12,9 +12,9 @@
---------------------------------------------------------------------------------------------------
-- File incr_counter.vhd |
-- |
-- Description Stop counter. Configurable counter_top_i and width. |
-- Current count value and done signal available. |
-- Done signal asserted simultaneous to value = counter_top_i. |
-- Description Stop counter. Configurable "counter_top_i" and "width". |
-- "Current count value" and "counting done" signals available. |
-- "Counting done" signal asserted simultaneous to"current count value=counter_top_i"|
-- Needs a rst_i to restart. |
-- |
-- |
......@@ -62,7 +62,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
entity incr_counter is
generic
(width : integer := 32); -- default size
(width : integer := 32); -- default size
port
-- INPUTS
-- Signals from the clk_rst_manager
......@@ -72,12 +72,12 @@ entity incr_counter is
-- Signals from any unit
counter_top_i : in std_logic_vector(width-1 downto 0); -- max value to be counted; when reached
-- counter stays at it, until a reset
counter_incr_en_i : in std_logic; -- enables counting
counter_incr_en_i : in std_logic; -- enables counting
-- OUTPUTS
-- Signals to any unit
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_full_o : out std_logic); -- counter reahed counter_top_i value
counter_is_full_o : out std_logic); -- counter reahed counter_top_i value
end incr_counter;
......@@ -120,6 +120,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= std_logic_vector(counter);
......
hdl/svec/hdl/rtl/irq_generator.vhd
View file @ 52491468
......@@ -13,22 +13,24 @@
-- File irq_generator.vhd |
-- |
-- Description Interrupts generator: the unit generates three interrups: |
-- |
-- o irq_tstamp_p_o is a 1-clk_i-long pulse generated when the amount of timestamps|
-- written in the circular_buffer, since the last interrupt or since the |
-- aquisition startup, exceeds the PCIe/VME settable threshold |
-- irq_tstamp_threshold_o |
-- written in the circular_buffer, since the last interrupt or since the startup |
-- of the aquisition,exceeds the PCIe/VME settable threshold irq_tstamp_threshold|
-- |
-- o irq_time_p_o is a 1-clk_i-long pulse generated when some timestamps have been |
-- written in the circular_buffer (>0) and the amount of time passed since the |
-- last interrupt or since the aquisition startup, exceeds the PCIe/VME settable |
-- threshold irq_time_threshold_o |
-- written in the circular_buffer (>=1 timestamp) and the amount of time passed |
-- since the last interrupt or since the aquisition startup, exceeds the PCIe/VME|
-- settable threshold irq_time_threshold |
-- |
-- o irq_acam_err_p_o is a 1-clk_i-long pulse generated when the ACAM Hit FIFOS are|
-- full (according to ACAM configuration register 11) |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 05/2012 |
-- Version v0.1 |
-- Date 08/2013 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
......@@ -37,6 +39,7 @@
-- 04/2013 v0.2 EG line 170 added "irq_time_threshold_i > 0"; if the user doesn t want the |
-- time interrupts he sets the irq_time_threshold reg to zero; same goes |
-- for number-of-tstamps interrupts, users sets to zero to disable them |
-- 08/2013 v1 EG time irq concept in milliseconds rather than seconds |
-- |
---------------------------------------------------------------------------------------------------
......@@ -76,32 +79,32 @@ entity irq_generator is
port
-- INPUTS
-- Signal from the clks_rsts_manager
(clk_i : in std_logic; -- 125 MHz clk
rst_i : in std_logic; -- global reset, synched to clk_i
(clk_i : in std_logic; -- 125 MHz clk
rst_i : in std_logic; -- global reset, synched to clk_i
irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0); -- PCIe/VME settable threshold
irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0); -- PCIe/VME settable threshold
-- Signal from the acam_timecontrol_interface
acam_errflag_r_edge_p_i : in std_logic; -- ACAM ErrFlag rising edge; through the ACAM config reg 11
-- the ERRflag is configured to follow the full flags of the
-- Hit FIFOs; this would translate to data loss
acam_errflag_r_edge_p_i : in std_logic; -- ACAM ErrFlag rising edge; through the ACAM config reg 11
-- the ERRflag is configured to follow the full flags of the
-- Hit FIFOs; this would translate to data loss
-- Signal from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- activates tstamps aquisition from ACAM
deactivate_acq_p_i : in std_logic; -- deactivates tstamps aquisition
activate_acq_p_i : in std_logic; -- activates tstamps aquisition from ACAM
deactivate_acq_p_i : in std_logic; -- deactivates tstamps aquisition
-- Signals from the data_formatting unit
tstamp_wr_p_i : in std_logic; -- pulse upon storage of a new timestamp
tstamp_wr_p_i : in std_logic; -- pulse upon storage of a new timestamp
-- Signal from the one_hz_gen unit (currently not used)
one_hz_p_i : in std_logic; -- pulse upon new second arrival
one_hz_p_i : in std_logic; -- pulse upon new second arrival
-- OUTPUTS
-- Signals to the wb_irq_controller
irq_tstamp_p_o : out std_logic; -- active if amount of tstamps > tstamps_threshold
irq_time_p_o : out std_logic; -- active if amount of tstamps < tstamps_threshold but time > time_threshold
irq_acam_err_p_o : out std_logic); -- active if ACAM err_flag_i is active
irq_tstamp_p_o : out std_logic; -- active if amount of tstamps > tstamps_threshold
irq_time_p_o : out std_logic; -- active if amount of tstamps < tstamps_threshold but time > time_threshold
irq_acam_err_p_o : out std_logic); -- active if ACAM err_flag_i is active
end irq_generator;
......@@ -233,7 +236,6 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- TIMESTAMPS COUNTER --
---------------------------------------------------------------------------------------------------
......@@ -254,7 +256,6 @@ begin
tstamps_c_incr_en <= tstamps_c_en and tstamp_wr_p_i;
---------------------------------------------------------------------------------------------------
-- TIME COUNTER --
---------------------------------------------------------------------------------------------------
......
hdl/svec/hdl/rtl/leds_manager.vhd
View file @ 52491468
......@@ -30,7 +30,7 @@
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Date 05/2012 |
-- Version v0.3 |
-- Version v0.1 |
-- Depends on |
-- |
---------------- |
......@@ -72,33 +72,33 @@ use work.tdc_core_pkg.all; -- definitions of types, constants, entities
entity leds_manager is
generic
(g_width : integer := 32;
(g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
-- INPUTS
-- Signals from the clks_rsts_manager
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- core internal reset, synched with 125 MHz clk
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- core internal reset, synched with 125 MHz clk
-- Signal from the one_hz_generator unit
one_hz_p_i : in std_logic;
-- Signal from the reg_ctrl unit
acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0); -- enable for the ACAM channels;
-- activation comes through dedicated reg c_ACAM_INPUTS_EN_ADR
-- activation comes through dedicated reg c_ACAM_INPUTS_EN_ADR
-- Signal for debugging (not used)
fordebug_i : in std_logic_vector(5 downto 0);
-- Signal for debugging
fordebug_i : in std_logic_vector(5 downto 0); -- for debugging, currently not used
-- OUTPUTS
-- Signals to the LEDs on the TDC front panel
tdc_led_status_o : out std_logic; -- TDC LED 1: division of 125 MHz
tdc_led_trig1_o : out std_logic; -- TDC LED 2: Channel 1 input enable
tdc_led_trig2_o : out std_logic; -- TDC LED 3: Channel 2 input enable
tdc_led_trig3_o : out std_logic; -- TDC LED 4: Channel 3 input enable
tdc_led_trig4_o : out std_logic; -- TDC LED 5: Channel 4 input enable
tdc_led_trig5_o : out std_logic);-- TDC LED 6: Channel 5 input enable
tdc_led_status_o : out std_logic; -- TDC LED 1: division of 125 MHz
tdc_led_trig1_o : out std_logic; -- TDC LED 2: Channel 1 termination enable
tdc_led_trig2_o : out std_logic; -- TDC LED 3: Channel 2 termination enable
tdc_led_trig3_o : out std_logic; -- TDC LED 4: Channel 3 termination enable
tdc_led_trig4_o : out std_logic; -- TDC LED 5: Channel 4 termination enable
tdc_led_trig5_o : out std_logic); -- TDC LED 6: Channel 5 termination enable
end leds_manager;
......
hdl/svec/hdl/rtl/one_hz_gen.vhd
View file @ 52491468
......@@ -12,8 +12,8 @@
---------------------------------------------------------------------------------------------------
-- File one_hz_gen.vhd |
-- |
-- Description Generates one pulse every second synchronously with the acam reference clock. |
-- The phase with the reference clock can be adjusted. still don t know why?? |
-- Description Generates one pulse every second synchronously with the ACAM reference clock. |
-- The phase with the reference clock can be adjusted (eva: think that is not needed)|
-- It also keeps track of the UTC time based on the local clock. |
-- |
-- |
......@@ -74,7 +74,7 @@ entity one_hz_gen is
-- Signals from the reg_ctrl unit
load_utc_p_i : in std_logic; -- enables loading of the local UTC time with starting_utc_i value
starting_utc_i : in std_logic_vector(g_width-1 downto 0); -- value coming from the PCIe
starting_utc_i : in std_logic_vector(g_width-1 downto 0); -- value coming from the PCIe/VME
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
-- with respect to reference clock
......@@ -92,7 +92,7 @@ end one_hz_gen;
--=================================================================================================
architecture rtl of one_hz_gen is
constant constant_delay : unsigned(g_width-1 downto 0) := x"00000004"; --maybe put in package--maybe not needed
constant constant_delay : unsigned(g_width-1 downto 0) := x"00000004";
signal local_utc : unsigned(g_width-1 downto 0);
signal one_hz_p_pre : std_logic;
signal one_hz_p_post : std_logic;
......@@ -142,14 +142,13 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- Load UTC time --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- utc_counter: generation of a 1 clk-long pulse every second
utc_counter: process (clk_i)--maybe use an already existing counter???
utc_counter: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' then
......@@ -164,13 +163,12 @@ begin
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
local_utc_o <= std_logic_vector(local_utc);
---------------------------------------------------------------------------------------------------
-- Delays?? --
-- Delays --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
pulse_delayer_counter: decr_counter -- delays the one_hz_p_pre pulse for total_delay clk_i ticks
......@@ -186,10 +184,9 @@ begin
counter_o => open);
-------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
one_hz_p_o <= one_hz_p_post;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
one_hz_p_o <= one_hz_p_post;
end architecture rtl;
......
hdl/svec/hdl/rtl/reg_ctrl.vhd
View file @ 52491468
This diff is collapsed.
hdl/svec/hdl/rtl/sdb_meta_pkg.vhd deleted 100644 → 0
View file @ 95b4c5fa
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- sdb_meta_pkg |
-- |
---------------------------------------------------------------------------------------------------
-- File sdb_meta_pkg.vhd |
-- |
-- Description Sdb meta-information for the FMC TDC design for SPEC. |
-- |
-- Authors Matthieu Cattin (matthieu.cattin@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2013 |
-- Version v1 |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_SDB_REPO_URL : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "http://svn.ohwr.org/fmc-tdc/hdl/spec/ ");
-- Synthesis informations
constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "svec_top_fmc_tdc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => x"00000000",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "SynpliDP",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00201206",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130629",
-- Synthesised by (string, 15 char)
syn_username => "egousiou ");
-- Integration record
constant c_SDB_INTEGRATION : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130629", -- yyyymmdd
name => "spec_fmctdc1ns5cha "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
\ No newline at end of file
hdl/svec/hdl/rtl/start_retrig_ctrl.vhd
View file @ 52491468
......@@ -25,29 +25,29 @@
-- |
-- [63:32] Coarse time within the current second; each bit represents 8 ns |
-- |
-- [31:0] Fine time to be added to the Coarse time: provided directly by Acam; |
-- [31:0] Fine time to be added to the Coarse time: provided directly by ACAM; |
-- each bit represents 81.03 ps |
-- |
-- In I-Mode the Acam chip provides unlimited measuring range with internal start |
-- retriggers. Acam is programmed to retrigger every (16*acam_clk_period) = |
-- (64*clk_i_period) = 512 ns; the StartTimer in Acam Reg 4 is set to 15. It counts |
-- In I-Mode the ACAM chip provides unlimited measuring range with internal start |
-- retriggers. ACAM is programmed to retrigger every (16*acam_clk_period) = |
-- (64*clk_i_period) = 512 ns; the StartTimer in ACAM Reg 4 is set to 15. It counts |
-- the number of retriggers after a Start pulse and upon the arrival of a Stop pulse |
-- and it sends this number in the "Start#" field of the timestamp. |
-- Unfortunately Acam's counter of the retriggers has only 8 bits and can count up |
-- Unfortunately ACAM's counter of the retriggers has only 8 bits and can count up |
-- to 256 retriggers. Within one second (our UTC time) there can be up to |
-- 1,953,125 retriggers, which is >> 256 and actually corresponds to 7629 overflows |
-- of the Acam counter. Therefore there is the need to follow Acam and keep track of |
-- the overflows. The Acam Interrupt flag (IrFlag pin 59) has been set to follow the |
-- highest bit of the Start# (through the Acam Reg 12 bit 26) and like this we |
-- manage to count retriggers synchronously to Acam itself. |
-- of the ACAM counter. Therefore there is the need to follow ACAM and keep track of |
-- the overflows. The ACAM Interrupt flag (IrFlag pin 59) has been set to follow the |
-- highest bit of the Start# (through the ACAM Reg 12 bit 26) and like this we |
-- manage to count retriggers synchronously to ACAM itself. |
-- For simplification, in the following figure we assume that two Stop signals arrive|
-- after less than 256 Acam internal retriggers. Therefore in the timestamps that |
-- Acam will give the Start# field will represent the exact amount of retriggers |
-- after less than 256 ACAM internal retriggers. Therefore in the timestamps that |
-- ACAM will give the Start# field will represent the exact amount of retriggers |
-- after the Start pulse. |
-- Note that the interval between this external Start pulse and the first internal |
-- retrigger may vary; it is measured by the Acam chip and stored as Start01 in Acam |
-- Reg 10. Moreover, there is the StartOff1 offset added to each Hit time by Acam |
-- (this does not appear in this figure) made available in Acam Reg 5. |
-- retrigger may vary; it is measured by the ACAM chip and stored as Start01 in ACAM |
-- Reg 10. Moreover, there is the StartOff1 offset added to each Hit time by ACAM |
-- (this does not appear in this figure) made available in ACAM Reg 5. |
-- However, in this TDC core application we are only interested in time differences |
-- between Stop pulses (ex. Stop2 - Stop1) and not in the precise arrival time of a |
-- Stop pulse. Since now both Start01 and StartOff1 are stable numbers affecting |
......@@ -57,21 +57,21 @@
-- Start ____|-|__________________________________________________________________________ |
-- Retriggers ________________|-|________________|-|________________|-|________________|-|_____ |
-- Stop1 _________________________________________________|-|_____________________________ |
-- Hit1 <------------->
-- Hit1 <-------------> |
-- Stop2 _____________________________________________________________________________|-|_ |
-- Hit2 <--> |
-- Start01 <----------> |
-- |
-- Coming back now to our timestamp format {UTC second, Coarse time, Fine time}, we |
-- have to somehow assosiate ACAM retriggers to the UTC time. Actually, Acam has no |
-- have to somehow assosiate ACAM retriggers to the UTC time. Actually, ACAM has no |
-- knowledge of the UTC time and the arrival of a new second happens completely |
-- independently. As the following figure shows the final timestamp of a Stop pulse |
-- is defined by the current UTC time plus the amount of time between that UTC and |
-- the Stop pulse: (2)+(3). Part (3) is provided exclusively by the Acam chip in the |
-- the Stop pulse: (2)+(3). Part (3) is provided exclusively by the ACAM chip in the |
-- Start# and Hit time fields of the timestamp. The sum of (1)+(2) is multiples of |
-- 256 Acam retriggers and can be defined by following the Acam output IrFlag. |
-- Now Part (1), is the one that associates the arrival of a UTC second with the Acam|
-- time counting and is defined in this unit by following the Acam retriggers. |
-- 256 ACAM retriggers and can be defined by following the ACAM output IrFlag. |
-- Now Part (1), is the one that associates the arrival of a UTC second with the ACAM|
-- time counting and is defined in this unit by following the ACAM retriggers. |
-- |
-- IrFlag ______________|--------------|______________|-------------|... _____________|--- |
-- ___________________________ ___________________________ _____________ |
......@@ -141,14 +141,11 @@ entity start_retrig_ctrl is
-- Signal from the clk_rst_manager
(clk_i : in std_logic;
rst_i : in std_logic;
-- Signal from the acam_timecontrol_interface
acam_intflag_f_edge_p_i : in std_logic;
-- Signal from the one_hz_generator unit
one_hz_p_i : in std_logic;
-- OUTPUTS
-- Signals to the data_formatting unit
roll_over_incr_recent_o : out std_logic;
......@@ -233,7 +230,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- These two counters keep a track of the current internal start retrigger
-- of the Acam in parallel with the Acam itself. Counting up to c_ACAM_RETRIG_PERIOD = 64
-- of the ACAM in parallel with the ACAM itself. Counting up to c_ACAM_RETRIG_PERIOD = 64
retrig_period_counter: free_counter -- retrigger periods
generic map
......@@ -263,7 +260,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- This counter keeps track of the number of overflows of the Acam counter within one second
-- This counter keeps track of the number of overflows of the ACAM counter within one second
roll_over_counter: incr_counter
generic map
(width => g_width)
......@@ -294,9 +291,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- outputs
roll_over_incr_recent_o <= '1' when unsigned(current_retrig_nb) < 64 else '0';
clk_i_cycles_offset_o <= clk_i_cycles_offset;
......
hdl/svec/hdl/rtl/tdc_core_pkg.vhd
View file @ 52491468
......@@ -561,9 +561,9 @@ package tdc_core_pkg is
clk_i : in std_logic;
rst_i : in std_logic;
acam_ef1_i : in std_logic;
acam_ef1_synch1_i : in std_logic;
acam_ef1_meta_i : in std_logic;
acam_ef2_i : in std_logic;
acam_ef2_synch1_i : in std_logic;
acam_ef2_meta_i : in std_logic;
activate_acq_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
acam_wr_config_p_i : in std_logic;
......@@ -836,9 +836,9 @@ package tdc_core_pkg is
wr_n_o : out std_logic;
ack_o : out std_logic;
ef1_o : out std_logic;
ef1_synch1_o : out std_logic;
ef1_meta_o : out std_logic;
ef2_o : out std_logic;
ef2_synch1_o : out std_logic;
ef2_meta_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
......@@ -873,7 +873,7 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component blk_mem_circ_buff_v6_4
port
(clka : in std_logic;
(clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(127 downto 0);
ena : in std_logic;
......
hdl/svec/hdl/rtl/top_tdc.vhd deleted 100644 → 0
View file @ 95b4c5fa
This diff is collapsed.
hdl/svec/hdl/rtl/xvme64x_core.vhd deleted 100644 → 0
View file @ 95b4c5fa
library ieee;
use ieee.STD_LOGIC_1164.all;
use WORK.wishbone_pkg.all;
use work.vme64x_pack.all;
entity xvme64x_core is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic
);
end xvme64x_core;
architecture wrapper of xvme64x_core is
component VME64xCore_Top
generic (
g_wb_data_width : integer := 32;
g_wb_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_wb_addr_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack_o : out std_logic;
IRQ_i : in std_logic;
debug : out std_logic_vector(7 downto 0));
end component;
signal rst_in, rst_out : std_logic;
signal dat_out, dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(63 downto 0);
begin -- wrapper
U_Wrapped_VME : VME64xCore_Top
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_i => VME_LWORD_n_b_i,
VME_LWORD_n_o => VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b_i,
VME_ADDR_o => VME_ADDR_b_o,
VME_DATA_i => VME_DATA_b_i,
VME_DATA_o => VME_DATA_b_o,
VME_IRQ_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
DAT_i => dat_in,
DAT_o => dat_out,
ADR_o => adr_out,
CYC_o => master_o.cyc,
ERR_i => master_i.err,
RTY_i => master_i.rty,
SEL_o => open,
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
IRQ_i => irq_i,
INT_ack_o => irq_ack_o
);
master_o.dat <= dat_out(31 downto 0);
master_o.sel <= (others => '1');
master_o.adr <= adr_out(29 downto 0) & "00"; -- word address to byte address
dat_in <= master_i.dat;
-- VME_IRQ_n_o <= (others => '0');
end wrapper;
hdl/svec/hdl/syn/svec/svec-tdc-fmc.xise
View file @ 52491468
......@@ -91,10 +91,11 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
......@@ -197,7 +198,7 @@
<property xil_pn:name="Output File Name" xil_pn:value="top_tdc" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -206,7 +207,7 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_tdc_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_tdc_timesim.v" xil_pn:valueState="default"/>
......@@ -217,6 +218,7 @@
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......
hdl/svec/hdl/syn/svec/top_tdc.twr 0 → 100644
View file @ 52491468
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hdl/svec/hdl/top/svec/top_tdc.vhd
View file @ 52491468
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hdl/svec/ucf/svec_tdc.ucf deleted 100644 → 0
View file @ 95b4c5fa
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