Commit 4c7db064 authored by Dimitris Lampridis's avatar Dimitris Lampridis

Merge branch '33-make-a-8-0-1-release' into 'master'

Resolve "Make a 8.0.1 release"

Closes #8 and #33

See merge request be-cem-edl/fec/hardware-modules/fmc-tdc-1ns-5cha!17
parents 3151ff60 ee015a51
......@@ -6,6 +6,33 @@
Changelog
=========
8.0.1 - 2022-12-20
==================
Added
-----
- hdl: bitstreams now published under https://be-cem-edl.web.cern.ch/
- doc: now published under https://be-cem-edl.web.cern.ch/
- sw: support for newer Linux kernels
- tst: timestamp validation
Removed
-------
- sw: ZIO dependency
Changed
-------
- bld: many improvements to CI
- bld: build system cleanup
- hdl: update to latest releases of all dependencies
- hdl: introduced FMC presence status to direct readout interface
- tst: improved performance
Fixed
-----
- hdl: fixed wrong reset logic
- sw: fixes from cppcheck and flawfinder report
8.0.0 - 2022-07-06
==================
Added
......
......@@ -8,7 +8,7 @@
# You can set these variables from the command line, and also
# from the environment for the first two.
SPHINXOPTS = -Drelease=$(shell git describe) -Dversion=$(shell git describe | cut -d "-" -f 1 | tr -d "v")
SPHINXOPTS =
SPHINXBUILD ?= sphinx-build
SOURCEDIR = .
BUILDDIR = _build
......
......@@ -26,6 +26,11 @@ project = 'FMC-TDC 1ns 5cha'
copyright = u'2022, CERN, documentation released under CC-BY-SA-4.0'
author = 'Federico Vaga <federico.vaga@cern.ch>'
import re
release = os.popen('git describe --tags').read().strip()
version = re.sub('^v', '', release.split('-')[0])
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
#
......@@ -109,3 +114,6 @@ breathe_projects_source = {
}
breathe_default_project = "fmctdc-lib"
# Will be appended to every rst source file in order to provide a reference to the latest version
rst_epilog = '.. |latest_release| replace:: %s' % version
This diff is collapsed.
\subsection{GN4124 DMA enhanced interrupt controller}
\label{subsec:wbgen:dma_eic}
Enhanced interrrupt controller for GN4124 DMA.
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x20& REG & Interrupt disable register & dma\_eic\_eic\_idr & EIC\_IDR\\
0x24& REG & Interrupt enable register & dma\_eic\_eic\_ier & EIC\_IER\\
0x28& REG & Interrupt mask register & dma\_eic\_eic\_imr & EIC\_IMR\\
0x2c& REG & Interrupt status register & dma\_eic\_eic\_isr & EIC\_ISR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{Interrupt disable register}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dma\_eic\_eic\_idr\\
{\bf HW address:} & 0x8\\
{\bf SW prefix:} & EIC\_IDR\\
{\bf SW offset:} & 0x20\\
\end{tabular}
\vspace{12pt}
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_ERROR} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_DONE}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DMA\_DONE
} [\emph{write-only}]: DMA done interrupt
\\
write 1: disable interrupt 'DMA done interrupt'\\write 0: no effect
\end{small}
\item \begin{small}
{\bf
DMA\_ERROR
} [\emph{write-only}]: DMA error interrupt
\\
write 1: disable interrupt 'DMA error interrupt'\\write 0: no effect
\end{small}
\end{itemize}
\paragraph*{Interrupt enable register}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dma\_eic\_eic\_ier\\
{\bf HW address:} & 0x9\\
{\bf SW prefix:} & EIC\_IER\\
{\bf SW offset:} & 0x24\\
\end{tabular}
\vspace{12pt}
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_ERROR} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_DONE}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DMA\_DONE
} [\emph{write-only}]: DMA done interrupt
\\
write 1: enable interrupt 'DMA done interrupt'\\write 0: no effect
\end{small}
\item \begin{small}
{\bf
DMA\_ERROR
} [\emph{write-only}]: DMA error interrupt
\\
write 1: enable interrupt 'DMA error interrupt'\\write 0: no effect
\end{small}
\end{itemize}
\paragraph*{Interrupt mask register}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dma\_eic\_eic\_imr\\
{\bf HW address:} & 0xa\\
{\bf SW prefix:} & EIC\_IMR\\
{\bf SW offset:} & 0x28\\
\end{tabular}
\vspace{12pt}
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_ERROR} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_DONE}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DMA\_DONE
} [\emph{read-only}]: DMA done interrupt
\\
read 1: interrupt 'DMA done interrupt' is enabled\\read 0: interrupt 'DMA done interrupt' is disabled
\end{small}
\item \begin{small}
{\bf
DMA\_ERROR
} [\emph{read-only}]: DMA error interrupt
\\
read 1: interrupt 'DMA error interrupt' is enabled\\read 0: interrupt 'DMA error interrupt' is disabled
\end{small}
\end{itemize}
\paragraph*{Interrupt status register}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dma\_eic\_eic\_isr\\
{\bf HW address:} & 0xb\\
{\bf SW prefix:} & EIC\_ISR\\
{\bf SW offset:} & 0x2c\\
\end{tabular}
\vspace{12pt}
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_ERROR} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}DMA\_DONE}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DMA\_DONE
} [\emph{read/write}]: DMA done interrupt
\\
read 1: interrupt 'DMA done interrupt' is pending\\read 0: interrupt not pending\\write 1: clear interrupt 'DMA done interrupt'\\write 0: no effect
\end{small}
\item \begin{small}
{\bf
DMA\_ERROR
} [\emph{read/write}]: DMA error interrupt
\\
read 1: interrupt 'DMA error interrupt' is pending\\read 0: interrupt not pending\\write 1: clear interrupt 'DMA error interrupt'\\write 0: no effect
\end{small}
\end{itemize}
\subsubsection{Interrupts}
\paragraph*{DMA done interrupt}\mbox{}\\\vskip 6pt
\begin{small}
\begin{tabular}{l l }
{\bf HW prefix:} & dma\_eic\_dma\_done\\
{\bf C prefix:} & DMA\_DONE\\
{\bf Trigger:} & rising edge\\
\end{tabular}
\end{small}
\vspace{12pt}
DMA done interrupt line (rising edge sensitive).
\paragraph*{DMA error interrupt}\mbox{}\\\vskip 6pt
\begin{small}
\begin{tabular}{l l }
{\bf HW prefix:} & dma\_eic\_dma\_error\\
{\bf C prefix:} & DMA\_ERROR\\
{\bf Trigger:} & rising edge\\
\end{tabular}
\end{small}
\vspace{12pt}
DMA error interrupt line (rising edge sensitive).
This diff is collapsed.
\subsection{TDC Direct Readout WB Slave}
\label{subsec:wbgen:dr}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & Channel Enable Register & dr\_chan\_enable & CHAN\_ENABLE\\
0x4& REG & Dead Time Register & dr\_dead\_time & DEAD\_TIME\\
0x8& FIFOREG & FIFO 'Readout FIFO' data output register 0 & dr\_fifo\_r0 & FIFO\_R0\\
0xc& FIFOREG & FIFO 'Readout FIFO' data output register 1 & dr\_fifo\_r1 & FIFO\_R1\\
0x10& FIFOREG & FIFO 'Readout FIFO' data output register 2 & dr\_fifo\_r2 & FIFO\_R2\\
0x14& REG & FIFO 'Readout FIFO' control/status register & dr\_fifo\_csr & FIFO\_CSR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{Channel Enable Register}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dr\_chan\_enable\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & CHAN\_ENABLE\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{5}{|c|}{\cellcolor{RoyalPurple!25}CHAN\_ENABLE[4:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHAN\_ENABLE
} [\emph{read/write}]: Channel enable
\end{small}
\end{itemize}
\paragraph*{Dead Time Register}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dr\_dead\_time\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & DEAD\_TIME\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DEAD\_TIME[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DEAD\_TIME[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}DEAD\_TIME[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DEAD\_TIME
} [\emph{read/write}]: Dead time (8ns ticks)
\end{small}
\end{itemize}
\paragraph*{FIFO 'Readout FIFO' data output register 0}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dr\_fifo\_r0\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & FIFO\_R0\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SECONDS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SECONDS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SECONDS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SECONDS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
SECONDS
} [\emph{read-only}]: Seconds
\end{small}
\end{itemize}
\paragraph*{FIFO 'Readout FIFO' data output register 1}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dr\_fifo\_r1\\
{\bf HW address:} & 0x3\\
{\bf SW prefix:} & FIFO\_R1\\
{\bf SW offset:} & 0xc\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CYCLES[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CYCLES[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CYCLES[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}CYCLES[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CYCLES
} [\emph{read-only}]: Cycles
\end{small}
\end{itemize}
\paragraph*{FIFO 'Readout FIFO' data output register 2}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dr\_fifo\_r2\\
{\bf HW address:} & 0x4\\
{\bf SW prefix:} & FIFO\_R2\\
{\bf SW offset:} & 0x10\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{4}{|c|}{\cellcolor{RoyalPurple!25}CHANNEL[3:0]} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}EDGE} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}BINS[17:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BINS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BINS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BINS
} [\emph{read-only}]: Bins
\end{small}
\item \begin{small}
{\bf
EDGE
} [\emph{read-only}]: Edge
\end{small}
\item \begin{small}
{\bf
CHANNEL
} [\emph{read-only}]: Channel
\end{small}
\end{itemize}
\paragraph*{FIFO 'Readout FIFO' control/status register}\mbox{}\\\vskip 6pt
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & dr\_fifo\_csr\\
{\bf HW address:} & 0x5\\
{\bf SW prefix:} & FIFO\_CSR\\
{\bf SW offset:} & 0x14\\
\end{tabular}
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}FULL}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}USEDW[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: FIFO full flag
\\
1: FIFO 'Readout FIFO' is full\\0: FIFO is not full
\end{small}
\item \begin{small}
{\bf
EMPTY
} [\emph{read-only}]: FIFO empty flag
\\
1: FIFO 'Readout FIFO' is empty\\0: FIFO is not empty
\end{small}
\item \begin{small}
{\bf
USEDW
} [\emph{read-only}]: FIFO counter
\\
Number of data records currently being stored in FIFO 'Readout FIFO'
\end{small}
\end{itemize}
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<h1 class="heading">fmc_tdc_mezzanine_mmap</h1>
<h3>FMC-TDC-1NS-5CH mezzanine memory map</h3>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x1000-0x1fff</td>
<td>SUBMAP</td>
<td><A href="#one-wire">one-wire</a></td>
<td class="td_code">one-wire</td>
<td class="td_code">one-wire</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x2000-0x2fff</td>
<td>SUBMAP</td>
<td><A href="#core">core</a></td>
<td class="td_code">core</td>
<td class="td_code">core</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x3000-0x3fff</td>
<td>SUBMAP</td>
<td><A href="#eic">eic</a></td>
<td class="td_code">eic</td>
<td class="td_code">eic</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x4000-0x4fff</td>
<td>SUBMAP</td>
<td><A href="#i2c">i2c</a></td>
<td class="td_code">i2c</td>
<td class="td_code">i2c</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x5000-0x5fff</td>
<td>SUBMAP</td>
<td><A href="#mem">mem</a></td>
<td class="td_code">mem</td>
<td class="td_code">mem</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x6000-0x6fff</td>
<td>SUBMAP</td>