Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC TDC 1ns 5cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC TDC 1ns 5cha
Commits
389734e7
Commit
389734e7
authored
Mar 26, 2015
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
testbench: sample top level testbench for SVEC
parent
b358b1ed
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
10 changed files
with
2016 additions
and
121 deletions
+2016
-121
cpu_csr_driver.svh
hdl/testbench/include/cpu_csr_driver.svh
+173
-0
mqueue_host.svh
hdl/testbench/include/mqueue_host.svh
+251
-0
vhd_wishbone_master.svh
hdl/testbench/include/vhd_wishbone_master.svh
+59
-0
sn74vmeh22501.v
hdl/testbench/include/vme64x_bfm/components/sn74vmeh22501.v
+41
-0
svec_vme_buffers.svh
hdl/testbench/include/vme64x_bfm/svec_vme_buffers.svh
+193
-0
vme64x_bfm.svh
hdl/testbench/include/vme64x_bfm/vme64x_bfm.svh
+463
-0
Manifest.py
hdl/testbench/svec/Manifest.py
+2
-2
main.sv
hdl/testbench/svec/main.sv
+122
-58
run.do
hdl/testbench/svec/run.do
+3
-3
wave.do
hdl/testbench/svec/wave.do
+709
-58
No files found.
hdl/testbench/include/cpu_csr_driver.svh
0 → 100644
View file @
389734e7
`include
"wrn_cpu_csr_regs.vh"
typedef
class
NodeCPUDbgQueue
;
class
NodeCPUControl
;
protected
CBusAccessor
bus
;
protected
uint32_t
base
;
protected
uint32_t
core_count
,
app_id
;
// NodeCPUDbgQueue dbgq [$];
NodeCPUDbgQueue
dbgq
[$]
;
function
new
(
CBusAccessor
bus_
,
input
uint32_t
base_
)
;
base
=
base_
;
bus
=
bus_
;
endfunction
// new
task
writel
(
uint32_t
r
,
uint32_t
v
)
;
bus
.
write
(
base
+
r
,
v
)
;
endtask
// _write
task
readl
(
uint32_t
r
,
ref
uint32_t
v
)
;
uint64_t
tmp
;
bus
.
read
(
base
+
r
,
tmp
)
;
v
=
tmp
;
endtask
// readl
task
init
()
;
int
i
;
readl
(
`ADDR_WRN_CPU_CSR_APP_ID
,
app_id
)
;
readl
(
`ADDR_WRN_CPU_CSR_CORE_COUNT
,
core_count
)
;
core_count
&=
'hf
;
for
(
i
=
0
;
i
<
core_count
;
i
++
)
begin
NodeCPUDbgQueue
q
=
new
(
this
,
i
)
;
dbgq
.
push_back
(
q
)
;
end
$
display
(
"App ID: %x"
,
app_id
)
;
$
display
(
"Core count: %d"
,
core_count
)
;
for
(
i
=
0
;
i
<
core_count
;
i
++
)
begin
uint32_t
memsize
;
writel
(
`ADDR_WRN_CPU_CSR_CORE_SEL
,
i
)
;
readl
(
`ADDR_WRN_CPU_CSR_CORE_MEMSIZE
,
memsize
)
;
$
display
(
"Core %d: %d kB private memory"
,
i
,
memsize
/
1024
)
;
end
endtask
// init
task
reset_core
(
int
core
,
int
reset
)
;
uint32_t
rstr
;
readl
(
`ADDR_WRN_CPU_CSR_RESET
,
rstr
)
;
if
(
reset
)
rstr
|=
(
1
<<
core
)
;
else
rstr
&=
~
(
1
<<
core
)
;
writel
(
`ADDR_WRN_CPU_CSR_RESET
,
rstr
)
;
endtask
// enable_cpu
task
debug_int_enable
(
int
core
,
int
enable
)
;
uint32_t
imsk
;
readl
(
`ADDR_WRN_CPU_CSR_DBG_IMSK
,
imsk
)
;
if
(
enable
)
imsk
|=
(
1
<<
core
)
;
else
imsk
&=
~
(
1
<<
core
)
;
writel
(
`ADDR_WRN_CPU_CSR_DBG_IMSK
,
imsk
)
;
endtask
// debug_int_enable
task
load_firmware
(
int
core
,
string
filename
)
;
integer
f
=
$
fopen
(
filename
,
"r"
)
;
uint32_t
q
[$]
;
int
n
,
i
;
reset_core
(
core
,
1
)
;
writel
(
`ADDR_WRN_CPU_CSR_CORE_SEL
,
core
)
;
while
(
!
$
feof
(
f
))
begin
int
addr
,
data
;
string
cmd
;
$
fscanf
(
f
,
"%s %08x %08x"
,
cmd
,
addr
,
data
)
;
if
(
cmd
==
"write"
)
begin
writel
(
`ADDR_WRN_CPU_CSR_UADDR
,
addr
)
;
writel
(
`ADDR_WRN_CPU_CSR_UDATA
,
data
)
;
q
.
push_back
(
data
)
;
n
++;
end
end
for
(
i
=
0
;
i
<
n
;
i
++
)
begin
uint32_t
rv
;
writel
(
`ADDR_WRN_CPU_CSR_UADDR
,
i
)
;
readl
(
`ADDR_WRN_CPU_CSR_UDATA
,
rv
)
;
$
display
(
"readback: addr %x d %x"
,
i
,
rv
)
;
if
(
rv
!=
q
[
i
])
$
display
(
"verification error
\n
"
)
;
end
endtask
task
update
()
;
int
i
;
for
(
i
=
0
;
i
<
core_count
;
i
++
)
dbgq
[
i
]
.
update
()
;
endtask
// update
endclass
class
NodeCPUDbgQueue
;
protected
NodeCPUControl
cctl
;
protected
int
core_id
;
int
queue
[$]
;
function
new
(
NodeCPUControl
cctl_
,
int
core_id_
)
;
cctl
=
cctl_
;
core_id
=
core_id_
;
endfunction
// new
task
update
()
;
uint32_t
rval
;
forever
begin
cctl
.
readl
(
`ADDR_WRN_CPU_CSR_DBG_POLL
,
rval
)
;
if
(
!
(
rval
&
(
1
<<
core_id
)))
break
;
cctl
.
writel
(
`ADDR_WRN_CPU_CSR_CORE_SEL
,
core_id
)
;
cctl
.
readl
(
`ADDR_WRN_CPU_CSR_DBG_MSG
,
rval
)
;
queue
.
push_back
(
rval
)
;
$
display
(
"dbg rx '%c'"
,
rval
)
;
end
endtask
// update
endclass
// NodeCPUDbgQueue
hdl/testbench/include/mqueue_host.svh
0 → 100644
View file @
389734e7
`define
MQUEUE_BASE_IN
(
x
)
(
'h4000
+
(
x
)
*
'h400
)
`define
MQUEUE_BASE_OUT
(
x
)
('
h8000
+
(
x
)
*
'
h400
)
`define
MQUEUE_CMD_CLAIM
(
1
<<
24
)
`define
MQUEUE_CMD_PURGE
(
1
<<
25
)
`define
MQUEUE_CMD_READY
(
1
<<
26
)
`define
MQUEUE_CMD_DISCARD
(
1
<<
27
)
`define
MQUEUE_SLOT_COMMAND 0
`define
MQUEUE_SLOT_STATUS 4
`define
MQUEUE_GCR_INCOMING_STATUS_MASK
(
32
'
h0000ffff
)
`define
MQUEUE_GCR_SLOT_COUNT 0
`define
MQUEUE_GCR_SLOT_STATUS 4
`define
MQUEUE_GCR_IRQ_MASK 8
`define
MQUEUE_GCR_IRQ_COALESCE 12
class
MQueueCB
;
protected
CBusAccessor
bus
;
protected
uint32_t
base
;
function
new
(
CBusAccessor
bus_
,
input
uint32_t
base_
)
;
base
=
base_
;
bus
=
bus_
;
endfunction
// new
task
outgoing_write
(
int
slot
,
uint32_t
r
,
uint32_t
v
)
;
bus
.
write
(
base
+
`MQUEUE_BASE_OUT
(
slot
)
+
r
,
v
)
;
endtask
// slot_write
task
send
(
int
slot
,
uint32_t
data
[]
)
;
int
i
;
outgoing_write
(
slot
,
`MQUEUE_SLOT_COMMAND
,
`MQUEUE_CMD_CLAIM
)
;
for
(
i
=
0
;
i
<
data
.
size
()
;
i
++
)
outgoing_write
(
slot
,
8
+
i
*
4
,
data
[
i
])
;
outgoing_write
(
slot
,
`MQUEUE_SLOT_COMMAND
,
`MQUEUE_CMD_READY
|
data
.
size
())
;
endtask
// send
endclass
class
MQueueHost
;
protected
CBusAccessor
bus
;
protected
uint32_t
base
;
protected
bit
initialized
;
protected
int
n_in
,
n_out
;
typedef
struct
{
uint32_t
data
[$]
;
}
mqueue_message_t
;
typedef
mqueue_message_t
slot_queue_t
[$]
;
slot_queue_t
slots_in
[
16
]
,
slots_out
[
16
]
;
function
bit
poll
(
int
slot
)
;
return
slots_in
[
slot
]
.
size
()
!=
0
;
endfunction
// poll
function
mqueue_message_t
recv
(
int
slot
)
;
mqueue_message_t
tmp
=
slots_in
[
slot
][$]
;
slots_in
[
slot
]
.
pop_back
()
;
return
tmp
;
endfunction
task
send
(
int
slot
,
uint32_t
data
[$])
;
mqueue_message_t
msg
;
msg
.
data
=
data
;
slots_out
[
slot
]
.
push_back
(
msg
)
;
endtask
// send
function
int
idle
()
;
int
i
;
for
(
i
=
0
;
i
<
n_out
;
i
++
)
if
(
slots_out
[
i
]
.
size
())
return
0
;
return
1
;
endfunction
// idle
function
new
(
CBusAccessor
bus_
,
input
uint32_t
base_
)
;
base
=
base_
;
bus
=
bus_
;
initialized
=
0
;
endfunction
// new
task
incoming_write
(
int
slot
,
uint32_t
r
,
uint32_t
v
)
;
bus
.
write
(
base
+
`MQUEUE_BASE_IN
(
slot
)
+
r
,
v
)
;
endtask
// slot_write
task
incoming_read
(
int
slot
,
uint32_t
r
,
ref
uint32_t
v
)
;
uint64_t
tmp
;
bus
.
read
(
base
+
`MQUEUE_BASE_IN
(
slot
)
+
r
,
tmp
)
;
v
=
tmp
;
endtask
// slot_write
task
outgoing_read
(
int
slot
,
uint32_t
r
,
ref
uint32_t
v
)
;
uint64_t
tmp
;
bus
.
read
(
base
+
`MQUEUE_BASE_OUT
(
slot
)
+
r
,
tmp
)
;
v
=
tmp
;
endtask
// slot_write
task
outgoing_write
(
int
slot
,
uint32_t
r
,
uint32_t
v
)
;
bus
.
write
(
base
+
`MQUEUE_BASE_OUT
(
slot
)
+
r
,
v
)
;
endtask
// slot_write
task
gcr_read
(
uint32_t
r
,
output
uint32_t
rv
)
;
uint64_t
tmp
;
bus
.
read
(
base
+
r
,
tmp
)
;
rv
=
tmp
;
endtask
// gcr_read
task
outgoing_check_full
(
int
slot
,
output
int
full
)
;
uint32_t
rv
;
outgoing_read
(
slot
,
`MQUEUE_SLOT_STATUS
,
rv
)
;
full
=
(
rv
&
1
)
?
1
:
0
;
endtask
// outgoing_full
task
incoming_send
(
int
slot
,
uint32_t
data
[$]
)
;
int
i
;
incoming_write
(
slot
,
`MQUEUE_SLOT_COMMAND
,
`MQUEUE_CMD_CLAIM
)
;
for
(
i
=
0
;
i
<
data
.
size
()
;
i
++
)
incoming_write
(
slot
,
8
+
i
*
4
,
data
[
i
])
;
incoming_write
(
slot
,
`MQUEUE_SLOT_COMMAND
,
`MQUEUE_CMD_READY
|
data
.
size
())
;
$
display
(
"in%d tx size=%d "
,
slot
,
data
.
size
())
;
endtask
// send
task
init
()
;
uint32_t
slot_count
,
slot_status
;
int
i
,
entries
,
size
;
gcr_read
(
`MQUEUE_GCR_SLOT_COUNT
,
slot_count
)
;
n_in
=
slot_count
&
'hff
;
n_out
=
(
slot_count
>>
8
)
&
'hff
;
$
display
(
"HMQ init: CPU->Host (outgoing) slots: %d Host->CPU (incoming) slots: %d"
,
n_out
,
n_in
)
;
for
(
i
=
0
;
i
<
n_out
;
i
++
)
begin
outgoing_read
(
i
,
`MQUEUE_SLOT_STATUS
,
slot_status
)
;
size
=
1
<<
((
slot_status
>>
28
)
&
'hf
)
;
entries
=
1
<<
((
slot_status
>>
2
)
&
'h3f
)
;
$
display
(
" - out%d: size=%d, entries=%d"
,
i
,
size
,
entries
)
;
end
for
(
i
=
0
;
i
<
n_in
;
i
++
)
begin
incoming_read
(
i
,
`MQUEUE_SLOT_STATUS
,
slot_status
)
;
size
=
1
<<
((
slot_status
>>
28
)
&
'hf
)
;
entries
=
1
<<
((
slot_status
>>
2
)
&
'h3f
)
;
$
display
(
" - in%d: size=%d, entries=%d"
,
i
,
size
,
entries
)
;
end
initialized
=
1
;
endtask
// init
task
outgoing_input
(
int
slot
)
;
uint32_t
stat
;
int
count
,
i
;
outgoing_read
(
slot
,
`MQUEUE_SLOT_STATUS
,
stat
)
;
count
=
(
stat
>>
16
)
&
'hff
;
$
display
(
"slot stat %x"
,
stat
)
;
$
display
(
"out%d rx size=%d "
,
slot
,
count
)
;
for
(
i
=
0
;
i
<
count
;
i
++
)
begin
uint32_t
d
;
outgoing_read
(
slot
,
8
+
i
*
4
,
d
)
;
$
display
(
"data: %x '%c'"
,
d
,
d
)
;
end
outgoing_write
(
slot
,
`MQUEUE_SLOT_COMMAND
,
`MQUEUE_CMD_DISCARD
)
;
endtask
// read_incoming
task
update
()
;
uint32_t
in_stat
,
irq_mask
;
int
i
;
if
(
!
initialized
)
init
()
;
gcr_read
(
`MQUEUE_GCR_SLOT_STATUS
,
in_stat
)
;
$
display
(
"GCR stat %x"
,
in_stat
)
;
gcr_read
(
`MQUEUE_GCR_IRQ_MASK
,
irq_mask
)
;
$
display
(
"GCR irq_mask %x"
,
irq_mask
)
;
if
(
in_stat
&
`MQUEUE_GCR_INCOMING_STATUS_MASK
)
begin
for
(
i
=
0
;
i
<
n_in
;
i
++
)
if
(
in_stat
&
(
1
<<
i
))
outgoing_input
(
i
)
;
end
for
(
i
=
0
;
i
<
n_out
;
i
++
)
begin
if
(
slots_out
[
i
]
.
size
()
)
begin
incoming_send
(
i
,
slots_out
[
i
][$]
.
data
)
;
slots_out
[
i
]
.
pop_back
()
;
end
end
endtask
// update
endclass
hdl/testbench/include/vhd_wishbone_master.svh
0 → 100644
View file @
389734e7
`include
"simdrv_defs.svh"
`include
"if_wb_master.svh"
interface
IVHDWishboneMaster
(
input
clk_i
,
input
rst_n_i
)
;
parameter
g_addr_width
=
32
;
parameter
g_data_width
=
32
;
typedef
virtual
IWishboneMaster
VIWishboneMaster
;
IWishboneMaster
#(
g_addr_width
,
g_data_width
)
TheMaster
(
clk_i
,
rst_n_i
)
;
t_wishbone_master_in
in
;
t_wishbone_master_out
out
;
modport
master
(
input
in
,
output
out
)
;
assign
out
.
cyc
=
TheMaster
.
cyc
;
assign
out
.
stb
=
TheMaster
.
stb
;
assign
out
.
we
=
TheMaster
.
we
;
assign
out
.
sel
=
TheMaster
.
sel
;
assign
out
.
adr
=
TheMaster
.
adr
;
assign
out
.
dat
=
TheMaster
.
dat_o
;
assign
TheMaster
.
ack
=
in
.
ack
;
assign
TheMaster
.
stall
=
in
.
stall
;
assign
TheMaster
.
rty
=
in
.
rty
;
assign
TheMaster
.
err
=
in
.
err
;
assign
TheMaster
.
dat_i
=
in
.
dat
;
function
CBusAccessor
get_accessor
()
;
return
TheMaster
.
get_accessor
()
;
endfunction
// get_accessor
initial
begin
CWishboneAccessor
acc
;
@
(
posedge
rst_n_i
)
;
@
(
posedge
clk_i
)
;
TheMaster
.
settings
.
addr_gran
=
BYTE
;
TheMaster
.
settings
.
cyc_on_stall
=
1
;
acc
=
TheMaster
.
get_accessor
()
;
acc
.
set_mode
(
PIPELINED
)
;
end
endinterface
// IVHDWishboneMaster
hdl/testbench/include/vme64x_bfm/components/sn74vmeh22501.v
0 → 100644
View file @
389734e7
`timescale
1
ns
/
1
ns
module
sn74vmeh22501
(
input
oeab1
,
oeby1_n
,
a1
,
output
y1
,
inout
b1
,
input
oeab2
,
oeby2_n
,
a2
,
output
y2
,
inout
b2
,
input
oe_n
,
input
dir
,
clkab
,
le
,
clkba
,
inout
[
1
:
8
]
a3
,
inout
[
1
:
8
]
b3
)
;
assign
b1
=
oeab1
?
a1
:
1'bz
;
assign
y1
=
oeby1_n
?
1'bz
:
b1
;
assign
b2
=
oeab2
?
a2
:
1'bz
;
assign
y2
=
oeby2_n
?
1'bz
:
b2
;
reg
[
1
:
8
]
b3LFF
;
always
@
(
posedge
clkab
)
if
(
~
le
)
b3LFF
<=
#
1
a3
;
always
@*
if
(
le
)
b3LFF
=
a3
;
assign
b3
=
(
~
oe_n
&&
dir
)
?
b3LFF
:
8
'
hz
;
reg
[
1
:
8
]
a3LFF
;
always
@
(
posedge
clkba
)
if
(
~
le
)
a3LFF
<=
#
1
b3
;
always
@*
if
(
le
)
a3LFF
=
b3
;
assign
a3
=
(
~
oe_n
&&
~
dir
)
?
a3LFF
:
8
'
hz
;
endmodule
hdl/testbench/include/vme64x_bfm/svec_vme_buffers.svh
0 → 100644
View file @
389734e7
`include
"components/sn74vmeh22501.v"
`include
"vme64x_bfm.svh"
module
bidir_buf
(
a
,
b
,
dir
,
/* 0: a->b, 1: b->a */
oe_n
)
;
parameter
g_width
=
1
;
inout
[
g_width
-
1
:
0
]
a
,
b
;
input
dir
,
oe_n
;
assign
b
=
(
!
dir
&&
!
oe_n
)
?
a
:
'bz
;
assign
a
=
(
dir
&&
!
oe_n
)
?
b
:
'bz
;
endmodule
// bidir_buf
module
svec_vme_buffers
(
output
VME_AS_n_o
,
output
VME_RST_n_o
,
output
VME_WRITE_n_o
,
output
[
5
:
0
]
VME_AM_o
,
output
[
1
:
0
]
VME_DS_n_o
,
output
[
5
:
0
]
VME_GA_o
,
input
VME_BERR_i
,
input
VME_DTACK_n_i
,
input
VME_RETRY_n_i
,
input
VME_RETRY_OE_i
,
inout
VME_LWORD_n_b
,
inout
[
31
:
1
]
VME_ADDR_b
,
inout
[
31
:
0
]
VME_DATA_b
,
output
VME_BBSY_n_o
,
input
[
6
:
0
]
VME_IRQ_n_i
,
output
VME_IACKIN_n_o
,
input
VME_IACKOUT_n_i
,
output
VME_IACK_n_o
,
input
VME_DTACK_OE_i
,
input
VME_DATA_DIR_i
,
input
VME_DATA_OE_N_i
,
input
VME_ADDR_DIR_i
,
input
VME_ADDR_OE_N_i
,
IVME64X
.
slave
slave
)
;
pullup
(
slave
.
as_n
)
;
pullup
(
slave
.
rst_n
)
;
pullup
(
slave
.
irq_n
[
0
])
;
pullup
(
slave
.
irq_n
[
1
])
;
pullup
(
slave
.
irq_n
[
2
])
;
pullup
(
slave
.
irq_n
[
3
])
;
pullup
(
slave
.
irq_n
[
4
])
;
pullup
(
slave
.
irq_n
[
5
])
;
pullup
(
slave
.
irq_n
[
6
])
;
pullup
(
slave
.
iack_n
)
;
pullup
(
slave
.
dtack_n
)
;
pullup
(
slave
.
retry_n
)
;
pullup
(
slave
.
ds_n
[
1
])
;
pullup
(
slave
.
ds_n
[
0
])
;
pullup
(
slave
.
lword_n
)
;
pullup
(
slave
.
berr_n
)
;
pullup
(
slave
.
write_n
)
;
pulldown
(
slave
.
bbsy_n
)
;
pullup
(
slave
.
iackin_n
)
;
pullup
(
slave
.
iackout_n
)
;
genvar
i
;
generate
for
(
i
=
0
;
i
<
6
;
i
++
)
assign
slave
.
irq_n
[
i
]
=
(
VME_IRQ_n_i
[
i
]
?
1'b0
:
1'bz
)
;
endgenerate
assign
VME_RST_n_o
=
slave
.
rst_n
;
assign
VME_AS_n_o
=
slave
.
as_n
;
assign
VME_GA_o
=
slave
.
ga
;
assign
VME_WRITE_n_o
=
slave
.
write_n
;
assign
VME_AM_o
=
slave
.
am
;
assign
VME_DS_n_o
=
slave
.
ds_n
;
assign
VME_BBSY_n_o
=
slave
.
bbsy_n
;
assign
VME_IACKIN_n_o
=
slave
.
iackin_n
;
assign
VME_IACK_n_o
=
slave
.
iack_n
;
bidir_buf
#(
1
)
b0
(
slave
.
lword_n
,
VME_LWORD_n_b
,
VME_ADDR_DIR_i
,
VME_ADDR_OE_N_i
)
;
bidir_buf
#(
31
)
b1
(
slave
.
addr
,
VME_ADDR_b
,
VME_ADDR_DIR_i
,
VME_ADDR_OE_N_i
)
;
bidir_buf
#(
33
)
b2
(
slave
.
data
,
VME_DATA_b
,
VME_DATA_DIR_i
,
VME_DATA_OE_N_i
)
;
pulldown
(
VME_BERR_i
)
;
pulldown
(
VME_ADDR_DIR_i
)
;
pulldown
(
VME_ADDR_OE_N_i
)
;
pulldown
(
VME_DATA_DIR_i
)
;
pulldown
(
VME_DATA_OE_N_i
)
;
assign
slave
.
dtack_n
=
VME_DTACK_n_i
;
assign
slave
.
berr_n
=
~
VME_BERR_i
;
assign
slave
.
retry_n
=
VME_RETRY_n_i
;
assign
slave
.
iackout_n
=
VME_IACKOUT_n_i
;
endmodule
`define
DECLARE_VME_BUFFERS
(
iface
)
\
wire VME_AS_n
;
\
wire VME_RST_n
;
\
wire VME_WRITE_n
;
\
wire
[
5
:
0
]
VME_AM
;
\
wire
[
1
:
0
]
VME_DS_n
;
\
wire VME_BERR
;
\
wire VME_DTACK_n
;
\
wire VME_RETRY_n
;
\
wire VME_RETRY_OE
;
\
wire VME_LWORD_n
;
\
wire
[
31
:
1
]
VME_ADDR
;
\
wire
[
31
:
0
]
VME_DATA
;
\
wire VME_BBSY_n
;
\
wire
[
6
:
0
]
VME_IRQ_n
;
\
wire VME_IACKIN_n
,
VME_IACK_n
;
\
wire VME_IACKOUT_n
;
\
wire VME_DTACK_OE
;
\
wire VME_DATA_DIR
;
\
wire VME_DATA_OE_N
;
\
wire VME_ADDR_DIR
;
\
wire VME_ADDR_OE_N
;
\
svec_vme_buffers U_VME_Bufs
(
\
.
VME_AS_n_o
(
VME_AS_n
),
\
.
VME_RST_n_o
(
VME_RST_n
),
\
.
VME_WRITE_n_o
(
VME_WRITE_n
),
\
.
VME_AM_o
(
VME_AM
),
\
.
VME_DS_n_o
(
VME_DS_n
),
\
.
VME_BERR_i
(
VME_BERR
),
\
.
VME_DTACK_n_i
(
VME_DTACK_n
),
\
.
VME_RETRY_n_i
(
VME_RETRY_n
),
\
.
VME_RETRY_OE_i
(
VME_RETRY_OE
),
\
.
VME_LWORD_n_b
(
VME_LWORD_n
),
\
.
VME_ADDR_b
(
VME_ADDR
),
\
.
VME_DATA_b
(
VME_DATA
),
\
.
VME_BBSY_n_o
(
VME_BBSY_n
),
\
.
VME_IRQ_n_i
(
VME_IRQ_n
),
\
.
VME_IACK_n_o
(
VME_IACK_n
),
\
.
VME_IACKIN_n_o
(
VME_IACKIN_n
),
\
.
VME_IACKOUT_n_i
(
VME_IACKOUT_n
),
\
.
VME_DTACK_OE_i
(
VME_DTACK_OE
),
\
.
VME_DATA_DIR_i
(
VME_DATA_DIR
),
\
.
VME_DATA_OE_N_i
(
VME_DATA_OE_N
),
\
.
VME_ADDR_DIR_i
(
VME_ADDR_DIR
),
\
.
VME_ADDR_OE_N_i
(
VME_ADDR_OE_N
),
\
.
slave
(
iface
)
\
)
;
function
automatic
bit
[
5
:
0
]
_
gen_ga
(
int
slot
)
;
bit
[
4
:
0
]
slot_id
=
slot
;
return
{^
slot_id
,
~
slot_id
};
endfunction
// _gen_ga
`define
WIRE_VME_PINS
(
slot_id
)
\
.
VME_AS_n_i
(
VME_AS_n
),
\
.
VME_RST_n_i
(
VME_RST_n
),
\
.
VME_WRITE_n_i
(
VME_WRITE_n
),
\
.
VME_AM_i
(
VME_AM
),
\
.
VME_DS_n_i
(
VME_DS_n
),
\
.
VME_GA_i
(
_gen_ga
(
slot_id
)),
\
.
VME_BERR_o
(
VME_BERR
),
\
.
VME_DTACK_n_o
(
VME_DTACK_n
),
\
.
VME_RETRY_n_o
(
VME_RETRY_n
),
\
.
VME_RETRY_OE_o
(
VME_RETRY_OE
),
\
.
VME_LWORD_n_b
(
VME_LWORD_n
),
\
.
VME_ADDR_b
(
VME_ADDR
),
\
.
VME_DATA_b
(
VME_DATA
),
\
.
VME_BBSY_n_i
(
VME_BBSY_n
),
\
.
VME_IRQ_n_o
(
VME_IRQ_n
),
\
.
VME_IACK_n_i
(
VME_IACK_n
),
\
.
VME_IACKIN_n_i
(
VME_IACKIN_n
),
\
.
VME_IACKOUT_n_o
(
VME_IACKOUT_n
),
\
.
VME_DTACK_OE_o
(
VME_DTACK_OE
),
\
.
VME_DATA_DIR_o
(
VME_DATA_DIR
),
\
.
VME_DATA_OE_N_o
(
VME_DATA_OE_N
),
\
.
VME_ADDR_DIR_o
(
VME_ADDR_DIR
),
\
.
VME_ADDR_OE_N_o
(
VME_ADDR_OE_N
)
\ No newline at end of file
hdl/testbench/include/vme64x_bfm/vme64x_bfm.svh
0 → 100644
View file @
389734e7
This diff is collapsed.
Click to expand it.
hdl/testbench/svec/Manifest.py
View file @
389734e7
action
=
"simulation"
target
=
"xilinx"
fetchto
=
"../../ip_cores"
vlog_opt
=
"+incdir+../../sim
/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
"
vlog_opt
=
"+incdir+../../sim
+incdir+../include/vme64x_bfm +incdir+../include
"
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../../top/svec"
]
}
modules
=
{
"local"
:
[
"../../top/svec
/with_wrabbit
"
]
}
hdl/testbench/svec/main.sv
View file @
389734e7
`include
"simdrv_defs.svh"
`include
"vme64x_bfm.svh"
`include
"svec_vme_buffers.svh"
module
main
;
reg
rst_n
=
0
;
reg
clk_125m
=
0
,
clk_20m
=
0
,
acam_refclk
=
0
;
reg
clk_125m
=
0
,
clk_20m
=
0
;
always
#
4
ns
clk_125m
<=
~
clk_125m
;
always
#
16
ns
acam_refclk
<=
~
acam_refclk
;
always
#
25
ns
clk_20m
<=
~
clk_20m
;
initial
begin
repeat
(
20
)
@
(
posedge
clk_125m
)
;
rst_n
=
1
;
end
IVME64X
VME
(
rst_n
)
;
`DECLARE_VME_BUFFERS
(
VME
.
slave
)
;
reg
acam_ef
=
1
;
wire
acam_rd
;
reg
tdc_ef1
=
1
;
reg
tdc_pulse
=
0
;
wire
tdc_rd_n
;
always
@
(
posedge
tdc_pulse
)
begin
#
100
ns
;
tdc_ef1
<=
0
;
while
(
tdc_rd_n
!=
0
)
#
1
ns
;
#
10
ns
;
tdc_ef1
<=
1
;
end
reg
clk_acam
=
0
;
reg
clk_62m5
=
0
;
always
@
(
posedge
clk_125m
)
clk_62m5
<=
~
clk_62m5
;
always
@
(
posedge
clk_62m5
)
clk_acam
<=
~
clk_acam
;
top_tdc
#(
.
values_for_simul
(
1
)
wr_svec_tdc
#(
.
g_with_wr_phy
(
0
)
,
.
g_simulation
(
1
)
)
DUT
(
.
clk_125m_pllref_p_i
(
clk_125m
)
,
.
clk_125m_pllref_n_i
(
~
clk_125m
)
,
.
clk_125m_gtp_p_i
(
clk_125m
)
,
.
clk_125m_gtp_n_i
(
~
clk_125m
)
,
.
tdc1_125m_clk_p_i
(
clk_125m
)
,
.
tdc1_125m_clk_n_i
(
~
clk_125m
)
,
.
tdc1_acam_refclk_p_i
(
clk_acam
)
,
.
tdc1_acam_refclk_n_i
(
~
clk_acam
)
,
.
clk_20m_vcxo_i
(
clk_20m
)
,
.
por_n_i
(
rst_n
)
,
.
ft0_tdc_125m_clk_p_i
(
clk_125m
)
,
.
ft0_tdc_125m_clk_n_i
(
~
clk_125m
)
,
.
ft0_acam_refclk_p_i
(
acam_refclk
)
,
.
ft0_acam_refclk_n_i
(
~
acam_refclk
)
,
.
ft0_pll_status_i
(
1'b1
)
,
.
ft0_rd_n_o
(
acam_rd
)
,
.
ft0_ef1_i
(
acam_ef
)
,
.
ft0_ef2_i
(
1'b1
)
,
.
ft1_tdc_125m_clk_p_i
(
clk_125m
)
,
.
ft1_tdc_125m_clk_n_i
(
~
clk_125m
)
,
.
ft1_pll_status_i
(
1'b1
)
,
.
tdc1_pll_status_i
(
1'b1
)
,
.
por_n_i
(
rst_n
)
,
.
tdc1_ef1_i
(
tdc_ef1
)
,
.
tdc1_ef2_i
(
1'b1
)
,
.
tdc1_err_flag_i
(
1'b0
)
,
.
tdc1_int_flag_i
(
1'b0
)
,
.
tdc1_rd_n_o
(
tdc_rd_n
)
,
.
tdc1_in_fpga_1_i
(
tdc_pulse
)
,
.
tdc1_in_fpga_2_i
(
1'b0
)
,
.
tdc1_in_fpga_3_i
(
1'b0
)
,
.
tdc1_in_fpga_4_i
(
1'b0
)
,
.
tdc1_in_fpga_5_i
(
1'b0
)
,
.
tdc1_data_bus_io
(
28'hcafebab
)
,
`WIRE_VME_PINS
(
8
)
)
;
)
;
initial
begin
#
500u
s
;
forever
begin
acam_ef
=
0
;
wait
(
!
acam_rd
)
;
#
10
ns
;
acam_ef
=
1
;
#
50u
s
;
end
end
task
automatic
config_vme_function
(
ref
CBusAccessor_VME64x
acc
,
input
int
func
,
uint64_t
base
,
int
am
)
;
uint64_t
addr
=
'h7ff63
+
func
*
'h10
;
uint64_t
val
=
(
base
)
|
(
am
<<
2
)
;
$
display
(
"Func%d ADER=0x%x"
,
func
,
val
)
;
if
(
am
==
0
)
val
=
1
;
acc
.
write
(
addr
+
0
,
(
val
>>
24
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
4
,
(
val
>>
16
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
8
,
(
val
>>
8
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
12
,
(
val
>>
0
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
endtask
// config_vme_function
task
automatic
init_vme64x_core
(
ref
CBusAccessor_VME64x
acc
)
;
uint64_t
rv
;
/* map func0 to 0x80000000, A32 */
acc
.
write
(
'h7ff63
,
'h80
,
A32
|
CR_CSR
|
D08Byte3
)
;
acc
.
write
(
'h7ff67
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6b
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6f
,
36
,
CR_CSR
|
A32
|
D08Byte3
)
;
// config_vme_function(acc, 0, 'h80000000, 'h09);
/* map func1 to 0xc00000, A24 */
config_vme_function
(
acc
,
1
,
'hc00000
,
'h39
)
;
config_vme_function
(
acc
,
0
,
0
,
0
)
;
acc
.
write
(
'h7ff33
,
1
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7fffb
,
'h10
,
CR_CSR
|
A32
|
D08Byte3
)
;
/* enable module (BIT_SET = 0x10) */
acc
.
set_default_modifiers
(
A24
|
D32
|
SINGLE
)
;
endtask
// init_vme64x_core
reg
force_irq
=
0
;
initial
begin
CBusAccessor_VME64x
acc
=
new
(
VME
.
master
)
;
CBusAccessor
acc_casted
=
CBusAccessor
'
(
acc
)
;
uint64_t
d
;
#
30u
s
;
uint64_t
d
;
const
uint64_t
tdc1_base
=
'h30000
;
#
100u
s
;
init_vme64x_core
(
acc
)
;
acc_casted
.
set_default_xfer_size
(
A32
|
SINGLE
|
D32
)
;
acc_casted
.
set_default_xfer_size
(
A24
|
SINGLE
|
D32
)
;
#
15u
s
;
$
display
(
"Un-reset FMCs..."
)
;
acc
.
read
(
'h80000000
,
d
,
D32
|
A32
|
SINGLE
)
;
$
display
(
"Master SDB 0 = %x. Un-resetting TDC cores."
,
d
)
;
acc
.
write
(
'hc2000c
,
'h3
)
;
acc
.
write
(
'h80020008
,
'hff
,
D32
|
A32
|
SINGLE
)
;
#
500u
s
;
acc
.
read
(
'hc40000
,
d
)
;
$
display
(
"TDC SDB ID : %x"
,
d
)
;
// wait for the PLLs to settle up
#
300u
s
;
acc
.
write
(
'hc510a0
,
1234
)
;
// set UTC
acc
.
write
(
'hc510fc
,
1
<<
9
)
;
// load UTC
acc
.
read
(
'h80040000
,
d
,
D32
|
A32
|
SINGLE
)
;
$
display
(
"SDB core 0 = %x"
,
d
)
;
acc
.
read
(
'h80060000
,
d
,
D32
|
A32
|
SINGLE
)
;
$
display
(
"SDB core 1 = %x"
,
d
)
;
acc
.
write
(
'hc52004
,
'hf
)
;
// enable EIC irq
acc
.
write
(
'h800500fc
,
1
,
D32
|
A32
|
SINGLE
)
;
// init acquisition
forever
begin
acc
.
read
(
'h800500a8
,
d
,
D32
|
A32
|
SINGLE
)
;
// init acquisition
$
display
(
"wr-ptr %x"
,
d
)
;
#
10u
s
;
acc
.
write
(
'hc51084
,
'h1f
)
;
// enable all ACAM inputs
acc
.
write
(
'hc510fc
,
(
1
<<
0
))
;
// start acquisition
#
300u
s
;
forever
begin
tdc_pulse
<=
1
;
#
1000
ns
;
tdc_pulse
<=
0
;
#
10
ns
;
end
end
// initial begin
end
...
...
hdl/testbench/svec/run.do
View file @
389734e7
vlog -sv main.sv +incdir+.
+incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
vsim work.main -voptargs=+acc
vlog -sv main.sv +incdir+.
./../sim +incdir+../include/vme64x_bfm +incdir+../include
vsim
-L unisim
work.main -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 100us
\ No newline at end of file
run 1ms
\ No newline at end of file
hdl/testbench/svec/wave.do
View file @
389734e7
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment