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FMC TDC 1ns 5cha
Commit 365e3f48 authored by egousiou's avatar egousiou
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- hdl: corrected misalignment between wrabbit_tai_p and arrival of a new wrabbit_tai second 


git-svn-id: http://svn.ohwr.org/fmc-tdc@185 85dfdc96-de2c-444c-878d-45b388be74a9
parent a2393b49
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hdl/rtl/data_formatting.vhd
View file @ 365e3f48
......@@ -145,7 +145,7 @@ architecture rtl of data_formatting is
signal acam_start_nb_32 : unsigned(31 downto 0);
-- final timestamp fields
signal full_timestamp : std_logic_vector(127 downto 0);
signal metadata, local_utc, coarse_time, fine_time : std_logic_vector(31 downto 0);
signal metadata, utc, coarse_time, fine_time : std_logic_vector(31 downto 0);
-- circular buffer timestamp writings WISHBONE interface
signal tstamp_wr_cyc, tstamp_wr_stb, tstamp_wr_we : std_logic;
-- circular buffer counters
......@@ -378,7 +378,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The following process makes essential calculations for the definition of the coarse time.
-- Regarding the signals: un_clk_i_cycles_offset, un_retrig_nb_offset, local_utc it has to be defined
-- Regarding the signals: un_clk_i_cycles_offset, un_retrig_nb_offset, utc it has to be defined
-- if the values that characterize the current second or the one previous to it should be used.
-- In the case where: a timestamp came on the same retgigger after a new second
-- (un_current_retrig_from_roll_over is 0 and un_acam_start_nb = un_current_retrig_nb_offset)
......@@ -405,38 +405,31 @@ begin
begin
if rising_edge (clk_i) then
if rst_i ='1' then
un_clk_i_cycles_offset <= (others => '0');
un_retrig_nb_offset <= (others => '0');
un_retrig_from_roll_over <= (others => '0');
local_utc <= (others => '0');
coarse_zero <= '0';
un_clk_i_cycles_offset <= (others => '0');
un_retrig_nb_offset <= (others => '0');
un_retrig_from_roll_over <= (others => '0');
utc <= (others => '0');
coarse_zero <= '0';
else
-- ACAM tstamp arrived on the same retgigger after a new second
if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
-- ACAM tstamp arrived on the same retgigger after a new second
if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
(un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318 and (un_current_retrig_from_roll_over = 0) ) then
--if (un_acam_start_nb = un_current_retrig_nb_offset) or
-- (un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318) then
coarse_zero <= '1';
un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
un_retrig_nb_offset <= un_previous_retrig_nb_offset;
local_utc <= previous_utc;
-- ACAM tstamp arrived when roll_over has just increased
--if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
-- un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb-1, 8);
--else
un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb, 8);
--end if;
coarse_zero <= '1';
un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
un_retrig_nb_offset <= un_previous_retrig_nb_offset;
utc <= previous_utc;
un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb, 8);
else
un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
local_utc <= utc_i;
coarse_zero <= '0';
un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
utc <= utc_i;
coarse_zero <= '0';
if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i)-1, 8);
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i)-1, 8);
else
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i), 8);
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i), 8);
end if;
end if;
end if;
......@@ -474,7 +467,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
full_timestamp(31 downto 0) <= fine_time;
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(95 downto 64) <= local_utc;
full_timestamp(95 downto 64) <= utc;
full_timestamp(127 downto 96) <= metadata;
tstamp_wr_dat_o <= full_timestamp;
......
hdl/rtl/fmc_tdc_core.vhd
View file @ 365e3f48
......@@ -651,7 +651,9 @@ begin
-- TRIG2(31 downto 0) <= utc(31 downto 0);
--
-- TRIG3(0) <= tdc_in_fpga_1_i;
-- TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
-- TRIG3(1) <= roll_over_incr_recent;
-- TRIG3(2) <= wrabbit_tai_p_i;
-- TRIG3(31 downto 3) <= current_retrig_nb(28 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 365e3f48
......@@ -73,6 +73,7 @@
-- 07/2013 v1 EG First version |
-- 01/2014 v2 EG Different output for the timestamp data |
-- 01/2014 v3 EG Removed option for timestamps retrieval through DMA |
-- 08/2014 v4 EG Corrected missalignement between wrabbit_tai and wrabbit_tai_p (line 444) |
-- |
---------------------------------------------------------------------------------------------------
......@@ -436,14 +437,19 @@ begin
wrabbit_one_hz_pulse : process(clk_ref_0_i)
begin
if rising_edge(clk_ref_0_i) then
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
if unsigned(wrabbit_cycles_i) = unsigned(c_SYN_CLK_PERIOD) -1 then
wrabbit_utc_p <= '1';
if rst_ref_0_n = '0' then
wrabbit_utc_p <= '0';
else
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
if unsigned(wrabbit_cycles_i) = (unsigned(c_SYN_CLK_PERIOD)-3) then -- so that the end of the pulse
-- comes exactly upon the UTC change
wrabbit_utc_p <= '1';
else
wrabbit_utc_p <= '0';
end if;
else
wrabbit_utc_p <= '0';
wrabbit_utc_p <= '0';
end if;
else
wrabbit_utc_p <= '0';
end if;
end if;
end process;
......
hdl/syn/spec/no_wrabbit/spec_tdc.par
View file @ 365e3f48
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Mon Jun 23 18:46:11 2014
PCBE13136:: Tue Jul 08 10:29:26 2014
par -w -intstyle ise -ol high -xe c -mt off spec_tdc_map.ncd spec_tdc.ncd
spec_tdc.pcf
......@@ -17,12 +17,6 @@ INFO:Par:338 -
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
speed improvements have shrunk to the point that the time specs are not expected to be met.
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
......@@ -40,7 +34,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,896 out of 27,288 14%
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -53,18 +47,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 113
Number with same-slice register load: 67
Number with same-slice carry load: 46
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,433 out of 6,822 21%
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,679
Number with an unused Flip Flop: 1,407 out of 4,679 30%
Number with an unused LUT: 783 out of 4,679 16%
Number of fully used LUT-FF pairs: 2,489 out of 4,679 53%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -123,8 +117,8 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
Starting initial Timing Analysis. REAL time: 11 secs
Finished initial Timing Analysis. REAL time: 11 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -134,31 +128,31 @@ WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt t
Starting Router
Phase 1 : 24061 unrouted; REAL time: 11 secs
Phase 1 : 24084 unrouted; REAL time: 13 secs
Phase 2 : 20719 unrouted; REAL time: 13 secs
Phase 2 : 20731 unrouted; REAL time: 16 secs
Phase 3 : 9189 unrouted; REAL time: 24 secs
Phase 3 : 8906 unrouted; REAL time: 27 secs
Phase 4 : 9209 unrouted; (Setup:0, Hold:1100, Component Switching Limit:0) REAL time: 26 secs
Phase 4 : 8912 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 30 secs
Updating file: spec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:1100, Component Switching Limit:0) REAL time: 46 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1100, Component Switching Limit:0) REAL time: 46 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1100, Component Switching Limit:0) REAL time: 46 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1100, Component Switching Limit:0) REAL time: 46 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:1100, Component Switching Limit:0) REAL time: 46 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 46 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 47 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 48 secs
Total REAL time to Router completion: 48 secs
Total CPU time to Router completion: 47 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Total REAL time to Router completion: 49 secs
Total CPU time to Router completion: 46 secs
Partition Implementation Status
-------------------------------
......@@ -176,13 +170,13 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_125m | BUFGMUX_X3Y7| No | 930 | 0.549 | 1.762 |
| clk_125m | BUFGMUX_X3Y7| No | 944 | 0.551 | 1.762 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X3Y13| No | 236 | 0.518 | 1.729 |
| clk | BUFGMUX_X3Y13| No | 235 | 0.518 | 1.729 |
+---------------------+--------------+------+------+------------+-------------+
|clk_20m_vcxo_buf_BUF | | | | | |
| G | BUFGMUX_X2Y3| No | 26 | 0.521 | 1.737 |
| G | BUFGMUX_X2Y3| No | 26 | 0.519 | 1.737 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -190,7 +184,7 @@ Generating Clock Report
|cmp_tdc_mezz/cmp_tdc | | | | | |
|_core/data_engine_bl | | | | | |
|ock/engine_st[3]_PWR | | | | | |
| _227_o_Mux_41_o | Local| | 2 | 0.019 | 0.493 |
| _227_o_Mux_41_o | Local| | 2 | 0.000 | 0.469 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -212,11 +206,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.077ns| 7.923ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.317ns| | 0| 0
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.051ns| 7.949ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.395ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.109ns| 4.891ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.042ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.248ns| 4.752ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.043ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
......@@ -246,7 +240,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
clk_125m_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | SETUP | 43.579ns| 6.421ns| 0| 0
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | SETUP | 44.742ns| 5.258ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | HOLD | 0.369ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
......@@ -288,12 +282,12 @@ Derived Constraints for TS_p2l_clk_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 4.891ns| 0| 0| 0| 5842|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.891ns| 0| 0| 0| 5842|
|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 4.752ns| 0| 0| 0| 5842|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.752ns| 0| 0| 0| 5842|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.891ns| N/A| 0| 0| 5842| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.752ns| N/A| 0| 0| 5842| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -311,10 +305,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 50 secs
Total CPU time to PAR completion: 50 secs
Total REAL time to PAR completion: 53 secs
Total CPU time to PAR completion: 48 secs
Peak Memory Usage: 332 MB
Peak Memory Usage: 333 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/syn/spec/no_wrabbit/spec_tdc.twr
View file @ 365e3f48
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/no_wrabbit/spec_tdc_map.map
View file @ 365e3f48
......@@ -10,14 +10,8 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 18:44:18 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapped Date : Tue Jul 08 10:27:13 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
......@@ -25,56 +19,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 18 secs
Total CPU time at the beginning of Placer: 16 secs
Total REAL time at the beginning of Placer: 21 secs
Total CPU time at the beginning of Placer: 17 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 20 secs
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 37 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 20 secs
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 38 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 20 secs
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 38 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:46e77852) REAL time: 52 secs
(Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 52 secs
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 9.8 Global Placement
................................
....................................................................
...............................................................
......................
Phase 9.8 Global Placement (Checksum:bed8b73d) REAL time: 1 mins 24 secs
..................................
........................................................
........................................................
..........................
Phase 9.8 Global Placement (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:bed8b73d) REAL time: 1 mins 24 secs
Phase 10.5 Local Placement Optimization (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:d7b12fa8) REAL time: 1 mins 39 secs
Phase 11.18 Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:d7b12fa8) REAL time: 1 mins 40 secs
Phase 12.5 Local Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:ad8925d5) REAL time: 1 mins 40 secs
Phase 13.34 Placement Validation (Checksum:d7bfac99) REAL time: 1 mins 59 secs
Total REAL time to Placer completion: 1 mins 47 secs
Total CPU time to Placer completion: 1 mins 44 secs
Total REAL time to Placer completion: 2 mins 6 secs
Total CPU time to Placer completion: 1 mins 47 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -94,7 +88,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,896 out of 27,288 14%
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -107,18 +101,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 113
Number with same-slice register load: 67
Number with same-slice carry load: 46
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,433 out of 6,822 21%
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,679
Number with an unused Flip Flop: 1,407 out of 4,679 30%
Number with an unused LUT: 783 out of 4,679 16%
Number of fully used LUT-FF pairs: 2,489 out of 4,679 53%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
......@@ -174,9 +168,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 1 mins 51 secs
Total CPU time to MAP completion: 1 mins 48 secs
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 2 mins 11 secs
Total CPU time to MAP completion: 1 mins 52 secs
Mapping completed.
See MAP report file "spec_tdc_map.mrp" for details.
hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp
View file @ 365e3f48
......@@ -10,7 +10,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 18:44:18 2014
Mapped Date : Tue Jul 08 10:27:13 2014
Design Summary
--------------
......@@ -22,7 +22,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,896 out of 27,288 14%
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -35,18 +35,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 113
Number with same-slice register load: 67
Number with same-slice carry load: 46
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,433 out of 6,822 21%
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,679
Number with an unused Flip Flop: 1,407 out of 4,679 30%
Number with an unused LUT: 783 out of 4,679 16%
Number of fully used LUT-FF pairs: 2,489 out of 4,679 53%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
......@@ -102,9 +102,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 1 mins 51 secs
Total CPU time to MAP completion: 1 mins 48 secs
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 2 mins 11 secs
Total CPU time to MAP completion: 1 mins 52 secs
Table of Contents
-----------------
......@@ -127,9 +127,6 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
......@@ -137,7 +134,6 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network button1_i has no load.
INFO:LIT:395 - The above info message is repeated 142 more times for the
following (max. 5 shown):
......
hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
View file @ 365e3f48
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Wed Jun 25 17:54:53 2014
PCBE13136:: Tue Jul 08 11:06:17 2014
par -w -intstyle ise -ol high -xe c -mt off wr_spec_tdc_map.ncd wr_spec_tdc.ncd
wr_spec_tdc.pcf
......@@ -34,11 +34,11 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,641 out of 27,288 38%
Number used as logic: 10,381 out of 27,288 38%
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 775
Number using O5 and O6: 2,232
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
......@@ -50,18 +50,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 193
Number with same-slice register load: 116
Number with same-slice carry load: 77
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,975 out of 6,822 58%
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,385
Number with an unused Flip Flop: 4,772 out of 12,385 38%
Number with an unused LUT: 1,744 out of 12,385 14%
Number of fully used LUT-FF pairs: 5,869 out of 12,385 47%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -125,7 +125,7 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 21 secs
Finished initial Timing Analysis. REAL time: 20 secs
WARNING:Par:288 - The signal sfp_rate_select_b_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_tx_fault_i_IBUF has no load. PAR will not attempt to route this signal.
......@@ -138,51 +138,51 @@ WARNING:Par:288 - The signal p_wr_req_i<1>_IBUF has no load. PAR will not attem
WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_los_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
PAR will not attempt to route this signal.
Starting Router
Phase 1 : 70820 unrouted; REAL time: 22 secs
Phase 1 : 70638 unrouted; REAL time: 22 secs
Phase 2 : 62168 unrouted; REAL time: 27 secs
Phase 2 : 62023 unrouted; REAL time: 26 secs
Phase 3 : 33642 unrouted; REAL time: 1 mins
Phase 3 : 32684 unrouted; REAL time: 54 secs
Phase 4 : 33737 unrouted; (Setup:287, Hold:65529, Component Switching Limit:0) REAL time: 1 mins 5 secs
Phase 4 : 32741 unrouted; (Setup:0, Hold:72789, Component Switching Limit:0) REAL time: 58 secs
Updating file: wr_spec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:445, Hold:63078, Component Switching Limit:0) REAL time: 2 mins 22 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 6 : 0 unrouted; (Setup:445, Hold:63078, Component Switching Limit:0) REAL time: 2 mins 24 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 26 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 26 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:63078, Component Switching Limit:0) REAL time: 3 mins 26 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 27 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 3 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 32 secs
Total REAL time to Router completion: 3 mins 32 secs
Total CPU time to Router completion: 3 mins 44 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 7 secs
Total REAL time to Router completion: 2 mins 7 secs
Total CPU time to Router completion: 2 mins 11 secs
Partition Implementation Status
-------------------------------
......@@ -200,29 +200,24 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X3Y13| No | 1639 | 0.529 | 1.740 |
| clk_62m5_sys | BUFGMUX_X3Y13| No | 1643 | 0.529 | 1.740 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_mezz | BUFGMUX_X3Y7| No | 805 | 0.551 | 1.762 |
| clk_125m_mezz | BUFGMUX_X3Y7| No | 727 | 0.551 | 1.762 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y4| No | 256 | 0.522 | 1.733 |
| clk | BUFGMUX_X2Y4| No | 247 | 0.522 | 1.733 |
+---------------------+--------------+------+------+------------+-------------+
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 140 | 0.076 | 1.290 |
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 153 | 0.077 | 1.290 |
+---------------------+--------------+------+------+------------+-------------+
|clk_125m_pllref_BUFG | | | | | |
| | BUFGMUX_X2Y1| No | 144 | 0.068 | 1.281 |
| | BUFGMUX_X2Y1| No | 152 | 0.065 | 1.281 |
+---------------------+--------------+------+------+------------+-------------+
| clk_dmtd | BUFGMUX_X2Y2| No | 86 | 0.046 | 1.279 |
| clk_dmtd | BUFGMUX_X2Y2| No | 88 | 0.032 | 1.245 |
+---------------------+--------------+------+------+------------+-------------+
|U_WR_CORE/WRPC/LM32_ | | | | | |
|CORE/gen_profile_med | | | | | |
|ium_icache_debug.U_W | | | | | |
| rapped_LM32/jtck | Local| | 9 | 2.259 | 5.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc_mezz/cmp_tdc | | | | | |
|_core/data_engine_bl | | | | | |
|ock/engine_st[3]_PWR | | | | | |
| _441_o_Mux_41_o | Local| | 2 | 0.000 | 0.820 |
| rapped_LM32/jtck | Local| | 9 | 3.112 | 6.373 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F2 | Local| | 1 | 0.000 | 0.002 |
......@@ -235,6 +230,11 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_gtp | Local| | 1 | 0.000 | 1.256 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc_mezz/cmp_tdc | | | | | |
|_core/data_engine_bl | | | | | |
|ock/engine_st[3]_PWR | | | | | |
| _441_o_Mux_41_o | Local| | 1 | 0.000 | 0.972 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
......@@ -255,44 +255,40 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.034ns| 7.966ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.373ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.055ns| 4.945ns| 0| 0
1_1 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.403ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.050ns| 4.950ns| 0| 0
1_1 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.115ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_1" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | SETUP | 0.073ns| 7.854ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | HOLD | 0.340ns| | 0| 0
TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.051ns| 7.949ns| 0| 0
_clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.421ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP " | SETUP | 0.169ns| 7.831ns| 0| 0
U_GTP_ch1_rx_divclk" TS_U_GTP_ch1 | HOLD | 0.322ns| | 0| 0
_gtp_clkout_int_1_ HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_tr | SETUP | 0.359ns| 1.641ns| 0| 0
ig" TO TIMEGRP "FFS" 2 ns DATAPAT | HOLD | 0.413ns| | 0| 0
TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_tr | SETUP | 0.169ns| 1.831ns| 0| 0
ig" TO TIMEGRP "FFS" 2 ns DATAPAT | HOLD | 0.704ns| | 0| 0
HONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock = MAXDELAY FROM TIME | SETUP | 0.605ns| 9.395ns| 0| 0
GRP "clk_62m5_sys" TO TIMEGRP "td | HOLD | 0.408ns| | 0| 0
c_clk_125m_p_i" 10 ns DATAPATHONLY | | | | |
ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_s | SETUP | 0.181ns| 9.819ns| 0| 0
ys" TO TIMEGRP "U_GTP_ch1_rx_divclk" | HOLD | 0.448ns| | 0| 0
10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_ = MAXDELAY FROM TIMEGRP "skew_limit" | SETUP | 0.735ns| 1.265ns| 0| 0
TO TIMEGRP "FFS" 2 ns DATAPATHONLY | HOLD | 0.396ns| | 0| 0
TS_ = MAXDELAY FROM TIMEGRP "skew_limit" | SETUP | 0.557ns| 1.443ns| 0| 0
TO TIMEGRP "FFS" 2 ns DATAPATHONLY | HOLD | 0.434ns| | 0| 0
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | SETUP | 0.807ns| 9.193ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "clk_1 | HOLD | 0.382ns| | 0| 0
25m_pllref_n_i" 10 ns DATAPATHONLY | | | | |
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | SETUP | 0.774ns| 6.711ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | HOLD | 0.393ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP " | SETUP | 0.873ns| 7.127ns| 0| 0
U_GTP_ch1_rx_divclk" TS_U_GTP_ch1 | HOLD | 0.363ns| | 0| 0
_gtp_clkout_int_1_ HIGH 50% | | | | |
TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_ | SETUP | 0.861ns| 9.139ns| 0| 0
rx_divclk" TO TIMEGRP "clk_62m5_sys" | HOLD | 0.344ns| | 0| 0
10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_pllout_clk_sys = PERIOD TIMEGRP "pllou | SETUP | 1.083ns| 14.917ns| 0| 0
t_clk_sys" TS_clk_20m_vcxo_i / 3.125 | HOLD | 0.126ns| | 0| 0
TS_pllout_clk_sys = PERIOD TIMEGRP "pllou | SETUP | 1.200ns| 14.800ns| 0| 0
t_clk_sys" TS_clk_20m_vcxo_i / 3.125 | HOLD | 0.039ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_s | SETUP | 1.558ns| 8.442ns| 0| 0
ys" TO TIMEGRP "U_GTP_ch1_rx_divclk" | HOLD | 0.443ns| | 0| 0
10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
......@@ -326,6 +322,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | SETUP | 3.332ns| 6.668ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "clk_1 | HOLD | 0.491ns| | 0| 0
25m_pllref_n_i" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_P_clk = PER | MINPERIOD | 4.075ns| 0.925ns| 0| 0
IOD TIMEGRP "cmp_gn4124_core/cmp_ | | | | |
......@@ -334,12 +337,9 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
n_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p_i" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_ | SETUP | 4.221ns| 5.779ns| 0| 0
rx_divclk" TO TIMEGRP "clk_62m5_sys" | HOLD | 0.603ns| | 0| 0
10 ns DATAPATHONLY | | | | |
ts_ignore_crossclock = MAXDELAY FROM TIME | SETUP | 4.274ns| 5.726ns| 0| 0
GRP "clk_62m5_sys" TO TIMEGRP "td | HOLD | 0.456ns| | 0| 0
c_clk_125m_p_i" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_p_i" 8 ns HIGH 50% | | | | |
......@@ -350,21 +350,21 @@ Asterisk (*) preceding a constraint indicates it was not met.
TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
clk_125m_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllo | SETUP | 5.326ns| 10.674ns| 0| 0
ut_clk_dmtd" TS_clk_20m_vcxo_i / | HOLD | 0.073ns| | 0| 0
TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllo | SETUP | 5.919ns| 10.081ns| 0| 0
ut_clk_dmtd" TS_clk_20m_vcxo_i / | HOLD | 0.014ns| | 0| 0
3.125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 6.079ns| 3.921ns| 0| 0
"clk_125m_pllref_p_i" TO TIMEGRP | HOLD | 0.446ns| | 0| 0
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 6.013ns| 3.987ns| 0| 0
"clk_125m_pllref_p_i" TO TIMEGRP | HOLD | 0.448ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock2 = MAXDELAY FROM TIM | SETUP | 6.783ns| 3.217ns| 0| 0
EGRP "tdc_clk_125m_p_i" TO TIMEGRP | HOLD | 0.367ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD T | MINPERIOD | 7.075ns| 0.925ns| 0| 0
IMEGRP "U_GTP/ch1_gtp_clkout_int<1>" | | | | |
125 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_crossclock2 = MAXDELAY FROM TIM | SETUP | 7.139ns| 2.861ns| 0| 0
EGRP "tdc_clk_125m_p_i" TO TIMEGRP | HOLD | 0.377ns| | 0| 0
"clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int = PERIOD TIMEGRP "cmp_gn412 | | | | |
......@@ -396,9 +396,9 @@ Derived Constraints for TS_clk_20m_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 46.616ns| 0| 0| 0| 1682593|
| TS_pllout_clk_dmtd | 16.000ns| 10.674ns| N/A| 0| 0| 9425| 0|
| TS_pllout_clk_sys | 16.000ns| 14.917ns| N/A| 0| 0| 1673168| 0|
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 46.250ns| 0| 0| 0| 1682593|
| TS_pllout_clk_dmtd | 16.000ns| 10.081ns| N/A| 0| 0| 9425| 0|
| TS_pllout_clk_sys | 16.000ns| 14.800ns| N/A| 0| 0| 1673168| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_p2l_clk_p_i
......@@ -437,13 +437,13 @@ Derived Constraints for TS_cmp_gn4124_core_cmp_clk_in_P_clk
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_cmp_gn4124_core_cmp_clk_in_P| 5.000ns| 0.925ns| 4.945ns| 0| 0| 0| 5838|
|TS_cmp_gn4124_core_cmp_clk_in_P| 5.000ns| 0.925ns| 4.950ns| 0| 0| 0| 5838|
|_clk | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.945ns| 0| 0| 0| 5838|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.950ns| 0| 0| 0| 5838|
| buf_P_clk_1 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_1 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.945ns| N/A| 0| 0| 5838| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.950ns| N/A| 0| 0| 5838| 0|
| _rx_pllout_x1_1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -453,8 +453,8 @@ Derived Constraints for TS_U_GTP_ch1_gtp_clkout_int_1_
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_GTP_ch1_gtp_clkout_int_1_ | 8.000ns| 0.925ns| 7.127ns| 0| 0| 0| 20096|
| TS_U_GTP_ch1_rx_divclk | 8.000ns| 7.127ns| N/A| 0| 0| 20096| 0|
|TS_U_GTP_ch1_gtp_clkout_int_1_ | 8.000ns| 0.925ns| 7.831ns| 0| 0| 0| 20096|
| TS_U_GTP_ch1_rx_divclk | 8.000ns| 7.831ns| N/A| 0| 0| 20096| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
......@@ -471,10 +471,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 16 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 mins 38 secs
Total CPU time to PAR completion: 3 mins 49 secs
Total REAL time to PAR completion: 2 mins 13 secs
Total CPU time to PAR completion: 2 mins 17 secs
Peak Memory Usage: 462 MB
Peak Memory Usage: 458 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
View file @ 365e3f48
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
View file @ 365e3f48
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 25 17:48:14 2014
Mapped Date : Tue Jul 08 10:59:56 2014
Mapping design into LUTs...
Running directed packing...
......@@ -21,56 +21,56 @@ INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 44 secs
Total CPU time at the beginning of Placer: 38 secs
Total CPU time at the beginning of Placer: 39 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:89307510) REAL time: 49 secs
Phase 1.1 Initial Placement Analysis (Checksum:2f07b54b) REAL time: 48 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:89307510) REAL time: 50 secs
Phase 2.7 Design Feasibility Check (Checksum:2f07b54b) REAL time: 49 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:476872d8) REAL time: 50 secs
Phase 3.31 Local Placement Optimization (Checksum:ed3fb313) REAL time: 49 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:87ab2a92) REAL time: 1 mins 38 secs
(Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 5.36 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 6.30 Global Clock Region Assignment (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 7.3 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 8.5 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 9.8 Global Placement
.....................
...............................................................................................
............................................................................................................................................................................................
..........................................................................................................................................................................................
........................................................................
Phase 9.8 Global Placement (Checksum:e5911db4) REAL time: 5 mins 20 secs
........................
..................................................................................................
.................................................................................
..................................................................................................................................
..............................
Phase 9.8 Global Placement (Checksum:9fd444c4) REAL time: 5 mins
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:e5911db4) REAL time: 5 mins 21 secs
Phase 10.5 Local Placement Optimization (Checksum:9fd444c4) REAL time: 5 mins 1 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 6 secs
Phase 11.18 Placement Optimization (Checksum:887f371b) REAL time: 5 mins 47 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 6 secs
Phase 12.5 Local Placement Optimization (Checksum:887f371b) REAL time: 5 mins 48 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:f1209e85) REAL time: 6 mins 7 secs
Phase 13.34 Placement Validation (Checksum:27e1a814) REAL time: 5 mins 48 secs
Total REAL time to Placer completion: 6 mins 25 secs
Total CPU time to Placer completion: 6 mins 17 secs
Total REAL time to Placer completion: 6 mins 7 secs
Total CPU time to Placer completion: 6 mins 1 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -79,27 +79,27 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -127,11 +127,11 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,641 out of 27,288 38%
Number used as logic: 10,381 out of 27,288 38%
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 775
Number using O5 and O6: 2,232
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
......@@ -143,18 +143,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 193
Number with same-slice register load: 116
Number with same-slice carry load: 77
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,975 out of 6,822 58%
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,385
Number with an unused Flip Flop: 4,772 out of 12,385 38%
Number with an unused LUT: 1,744 out of 12,385 14%
Number of fully used LUT-FF pairs: 5,869 out of 12,385 47%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 992 out of 54,576 1%
......@@ -214,9 +214,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 37 secs
Total CPU time to MAP completion: 6 mins 28 secs
Peak Memory Usage: 476 MB
Total REAL time to MAP completion: 6 mins 19 secs
Total CPU time to MAP completion: 6 mins 12 secs
Mapping completed.
See MAP report file "wr_spec_tdc_map.mrp" for details.
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp
View file @ 365e3f48
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 25 17:48:14 2014
Mapped Date : Tue Jul 08 10:59:56 2014
Design Summary
--------------
......@@ -23,11 +23,11 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,641 out of 27,288 38%
Number used as logic: 10,381 out of 27,288 38%
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 775
Number using O5 and O6: 2,232
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
......@@ -39,18 +39,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 193
Number with same-slice register load: 116
Number with same-slice carry load: 77
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,975 out of 6,822 58%
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,385
Number with an unused Flip Flop: 4,772 out of 12,385 38%
Number with an unused LUT: 1,744 out of 12,385 14%
Number of fully used LUT-FF pairs: 5,869 out of 12,385 47%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 992 out of 54,576 1%
......@@ -110,9 +110,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 37 secs
Total CPU time to MAP completion: 6 mins 28 secs
Peak Memory Usage: 476 MB
Total REAL time to MAP completion: 6 mins 19 secs
Total CPU time to MAP completion: 6 mins 12 secs
Table of Contents
-----------------
......@@ -141,27 +141,27 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......
hdl/syn/svec/with_wrabbit/wr_svec_tdc.par
View file @ 365e3f48
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Mon Jun 23 17:29:07 2014
PCBE13136:: Tue Jul 08 10:54:36 2014
par -w -intstyle ise -ol high -xe c -mt off wr_svec_tdc_map.ncd wr_svec_tdc.ncd
wr_svec_tdc.pcf
......@@ -17,12 +17,6 @@ INFO:Par:338 -
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
speed improvements have shrunk to the point that the time specs are not expected to be met.
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
......@@ -40,11 +34,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,151 out of 92,152 17%
Number used as logic: 15,779 out of 92,152 17%
Number using O6 output only: 11,156
Number using O5 output only: 843
Number using O5 and O6: 3,780
Number of Slice LUTs: 16,122 out of 92,152 17%
Number used as logic: 15,780 out of 92,152 17%
Number using O6 output only: 11,157
Number using O5 output only: 844
Number using O5 and O6: 3,779
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
......@@ -56,18 +50,18 @@ Slice Logic Utilization:
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 285
Number with same-slice register load: 178
Number with same-slice carry load: 107
Number used exclusively as route-thrus: 255
Number with same-slice register load: 150
Number with same-slice carry load: 105
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,354 out of 23,038 27%
Number of occupied Slices: 6,416 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,631
Number with an unused Flip Flop: 7,987 out of 18,631 42%
Number with an unused LUT: 2,480 out of 18,631 13%
Number of fully used LUT-FF pairs: 8,164 out of 18,631 43%
Number of LUT Flip Flop pairs used: 18,651
Number with an unused Flip Flop: 7,970 out of 18,651 42%
Number with an unused LUT: 2,529 out of 18,651 13%
Number of fully used LUT-FF pairs: 8,152 out of 18,651 43%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -125,59 +119,59 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 23 secs
Finished initial Timing Analysis. REAL time: 24 secs
Starting initial Timing Analysis. REAL time: 30 secs
Finished initial Timing Analysis. REAL time: 30 secs
WARNING:Par:288 - The signal sfp_tx_fault_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_los_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc1_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc2_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
PAR will not attempt to route this signal.
Starting Router
Phase 1 : 102842 unrouted; REAL time: 27 secs
Phase 1 : 102859 unrouted; REAL time: 34 secs
Phase 2 : 91133 unrouted; REAL time: 37 secs
Phase 2 : 91138 unrouted; REAL time: 45 secs
Phase 3 : 44433 unrouted; REAL time: 2 mins 38 secs
Phase 3 : 42992 unrouted; REAL time: 2 mins 50 secs
Phase 4 : 44444 unrouted; (Setup:2732, Hold:0, Component Switching Limit:0) REAL time: 2 mins 48 secs
Phase 4 : 42992 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 56 secs
Updating file: wr_svec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:4319, Hold:0, Component Switching Limit:0) REAL time: 5 mins 52 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 6 : 0 unrouted; (Setup:4319, Hold:0, Component Switching Limit:0) REAL time: 5 mins 54 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 33 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 33 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 33 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 33 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 36 secs
Total REAL time to Router completion: 6 mins 36 secs
Total CPU time to Router completion: 6 mins 34 secs
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 2 secs
Total REAL time to Router completion: 4 mins 3 secs
Total CPU time to Router completion: 3 mins 50 secs
Partition Implementation Status
-------------------------------
......@@ -195,18 +189,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X2Y3| No | 2258 | 0.839 | 1.923 |
| clk_62m5_sys | BUFGMUX_X2Y3| No | 2267 | 0.839 | 1.923 |
+---------------------+--------------+------+------+------------+-------------+
| clk_dmtd | BUFGMUX_X3Y13| No | 115 | 0.068 | 1.417 |
| clk_dmtd | BUFGMUX_X3Y13| No | 117 | 0.147 | 1.411 |
+---------------------+--------------+------+------+------------+-------------+
|clk_125m_pllref_BUFG | | | | | |
| | BUFGMUX_X2Y4| No | 141 | 0.247 | 1.433 |
| | BUFGMUX_X2Y4| No | 142 | 0.314 | 1.411 |
+---------------------+--------------+------+------+------------+-------------+
| tdc1_125m_clk | BUFGMUX_X3Y7| No | 723 | 0.830 | 1.916 |
| tdc1_125m_clk | BUFGMUX_X3Y7| No | 748 | 0.832 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| tdc2_125m_clk | BUFGMUX_X2Y12| No | 759 | 0.819 | 1.916 |
| tdc2_125m_clk | BUFGMUX_X2Y12| No | 738 | 0.830 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 144 | 0.249 | 1.429 |
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 140 | 0.193 | 1.427 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F2 | Local| | 1 | 0.000 | 0.002 |
......@@ -217,14 +211,14 @@ Generating Clock Report
|U_WR_CORE/WRPC/LM32_ | | | | | |
|CORE/gen_profile_med | | | | | |
|ium_icache_debug.U_W | | | | | |
| rapped_LM32/jtck | Local| | 9 | 2.628 | 6.629 |
| rapped_LM32/jtck | Local| | 9 | 0.244 | 7.114 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_gtp | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc2/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_290 | | | | | |
| _o_Mux_41_o | Local| | 2 | 0.000 | 0.302 |
| _o_Mux_41_o | Local| | 2 | 1.187 | 2.006 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc1/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
......@@ -251,14 +245,14 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "td | SETUP | 0.244ns| 7.756ns| 0| 0
c1_125m_clk_p_i" 8 ns HIGH 50% | HOLD | 0.348ns| | 0| 0
TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "td | SETUP | 0.255ns| 7.745ns| 0| 0
c1_125m_clk_p_i" 8 ns HIGH 50% | HOLD | 0.346ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP | SETUP | 0.263ns| 7.737ns| 0| 0
"tdc2_125m_clk_n_i" 8 ns HIGH 50% | HOLD | 0.335ns| | 0| 0
TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP | SETUP | 0.293ns| 7.707ns| 0| 0
"tdc2_125m_clk_n_i" 8 ns HIGH 50% | HOLD | 0.247ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | SETUP | 0.456ns| 7.088ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | HOLD | 0.200ns| | 0| 0
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | SETUP | 0.977ns| 7.023ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | HOLD | 0.311ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | MINPERIOD | 1.750ns| 6.250ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | | | | |
......@@ -275,12 +269,12 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_tdc2_tdc_125m_clk_p_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc2_125m_clk_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP | SETUP | 12.115ns| 7.885ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "tdc2_ | HOLD | 0.423ns| | 0| 0
ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP | SETUP | 10.800ns| 9.200ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "tdc2_ | HOLD | 0.557ns| | 0| 0
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 17.140ns| 2.860ns| 0| 0
"tdc2_125m_clk" TO TIMEGRP "clk_ | HOLD | 0.681ns| | 0| 0
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 16.122ns| 3.878ns| 0| 0
"tdc2_125m_clk" TO TIMEGRP "clk_ | HOLD | 0.473ns| | 0| 0
62m5_sys" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | N/A | N/A| N/A| N/A| N/A
......@@ -303,10 +297,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 mins 43 secs
Total CPU time to PAR completion: 6 mins 41 secs
Total REAL time to PAR completion: 4 mins 12 secs
Total CPU time to PAR completion: 3 mins 58 secs
Peak Memory Usage: 663 MB
Peak Memory Usage: 655 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/syn/svec/with_wrabbit/wr_svec_tdc.twr
View file @ 365e3f48
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.map
View file @ 365e3f48
......@@ -11,14 +11,8 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 17:22:57 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapped Date : Tue Jul 08 10:48:00 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
......@@ -26,57 +20,57 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 52 secs
Total CPU time at the beginning of Placer: 48 secs
Total REAL time at the beginning of Placer: 54 secs
Total CPU time at the beginning of Placer: 50 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:727220ca) REAL time: 1 mins
Phase 1.1 Initial Placement Analysis (Checksum:b36b8248) REAL time: 1 mins 5 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:727220ca) REAL time: 1 mins 2 secs
Phase 2.7 Design Feasibility Check (Checksum:b36b8248) REAL time: 1 mins 7 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:c940f3c7) REAL time: 1 mins 2 secs
Phase 3.31 Local Placement Optimization (Checksum:131da998) REAL time: 1 mins 7 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a365d66e) REAL time: 1 mins 20 secs
(Checksum:947c35ac) REAL time: 1 mins 26 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a365d66e) REAL time: 1 mins 20 secs
Phase 5.36 Local Placement Optimization (Checksum:947c35ac) REAL time: 1 mins 26 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a365d66e) REAL time: 1 mins 20 secs
Phase 6.30 Global Clock Region Assignment (Checksum:947c35ac) REAL time: 1 mins 26 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a365d66e) REAL time: 1 mins 21 secs
Phase 7.3 Local Placement Optimization (Checksum:947c35ac) REAL time: 1 mins 27 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a365d66e) REAL time: 1 mins 21 secs
Phase 8.5 Local Placement Optimization (Checksum:947c35ac) REAL time: 1 mins 27 secs
Phase 9.8 Global Placement
.....................
.........................................................................
....................................................................................................................................................................
.....................................................................................................
................................................................
Phase 9.8 Global Placement (Checksum:b067106b) REAL time: 3 mins 22 secs
................................................................................
.........................................................................................................................................................
.........................................................................................................................................
.....................................................................................................................................
Phase 9.8 Global Placement (Checksum:acc0a8e6) REAL time: 3 mins 42 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:b067106b) REAL time: 3 mins 23 secs
Phase 10.5 Local Placement Optimization (Checksum:acc0a8e6) REAL time: 3 mins 43 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1bfa6c45) REAL time: 4 mins 15 secs
Phase 11.18 Placement Optimization (Checksum:2df3d620) REAL time: 4 mins 33 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1bfa6c45) REAL time: 4 mins 15 secs
Phase 12.5 Local Placement Optimization (Checksum:2df3d620) REAL time: 4 mins 34 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:a7b00f1c) REAL time: 4 mins 16 secs
Phase 13.34 Placement Validation (Checksum:fa538ed7) REAL time: 4 mins 35 secs
Total REAL time to Placer completion: 5 mins 51 secs
Total CPU time to Placer completion: 5 mins 43 secs
Total REAL time to Placer completion: 6 mins 16 secs
Total CPU time to Placer completion: 6 mins 3 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -89,7 +83,7 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
......@@ -97,19 +91,19 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -137,11 +131,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,151 out of 92,152 17%
Number used as logic: 15,779 out of 92,152 17%
Number using O6 output only: 11,156
Number using O5 output only: 843
Number using O5 and O6: 3,780
Number of Slice LUTs: 16,122 out of 92,152 17%
Number used as logic: 15,780 out of 92,152 17%
Number using O6 output only: 11,157
Number using O5 output only: 844
Number using O5 and O6: 3,779
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
......@@ -153,18 +147,18 @@ Slice Logic Utilization:
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 285
Number with same-slice register load: 178
Number with same-slice carry load: 107
Number used exclusively as route-thrus: 255
Number with same-slice register load: 150
Number with same-slice carry load: 105
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,354 out of 23,038 27%
Number of occupied Slices: 6,416 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,631
Number with an unused Flip Flop: 7,987 out of 18,631 42%
Number with an unused LUT: 2,480 out of 18,631 13%
Number of fully used LUT-FF pairs: 8,164 out of 18,631 43%
Number of LUT Flip Flop pairs used: 18,651
Number with an unused Flip Flop: 7,970 out of 18,651 42%
Number with an unused LUT: 2,529 out of 18,651 13%
Number of fully used LUT-FF pairs: 8,152 out of 18,651 43%
Number of unique control sets: 502
Number of slice register sites lost
to control set restrictions: 1,224 out of 184,304 1%
......@@ -220,8 +214,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 6 mins 7 secs
Total CPU time to MAP completion: 5 mins 59 secs
Total REAL time to MAP completion: 6 mins 34 secs
Total CPU time to MAP completion: 6 mins 19 secs
Mapping completed.
See MAP report file "wr_svec_tdc_map.mrp" for details.
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.mrp
View file @ 365e3f48
......@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 17:22:57 2014
Mapped Date : Tue Jul 08 10:48:00 2014
Design Summary
--------------
......@@ -23,11 +23,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,151 out of 92,152 17%
Number used as logic: 15,779 out of 92,152 17%
Number using O6 output only: 11,156
Number using O5 output only: 843
Number using O5 and O6: 3,780
Number of Slice LUTs: 16,122 out of 92,152 17%
Number used as logic: 15,780 out of 92,152 17%
Number using O6 output only: 11,157
Number using O5 output only: 844
Number using O5 and O6: 3,779
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
......@@ -39,18 +39,18 @@ Slice Logic Utilization:
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 285
Number with same-slice register load: 178
Number with same-slice carry load: 107
Number used exclusively as route-thrus: 255
Number with same-slice register load: 150
Number with same-slice carry load: 105
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,354 out of 23,038 27%
Number of occupied Slices: 6,416 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,631
Number with an unused Flip Flop: 7,987 out of 18,631 42%
Number with an unused LUT: 2,480 out of 18,631 13%
Number of fully used LUT-FF pairs: 8,164 out of 18,631 43%
Number of LUT Flip Flop pairs used: 18,651
Number with an unused Flip Flop: 7,970 out of 18,651 42%
Number with an unused LUT: 2,529 out of 18,651 13%
Number of fully used LUT-FF pairs: 8,152 out of 18,651 43%
Number of unique control sets: 502
Number of slice register sites lost
to control set restrictions: 1,224 out of 184,304 1%
......@@ -106,8 +106,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 6 mins 7 secs
Total CPU time to MAP completion: 5 mins 59 secs
Total REAL time to MAP completion: 6 mins 34 secs
Total CPU time to MAP completion: 6 mins 19 secs
Table of Contents
-----------------
......@@ -130,9 +130,6 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
......@@ -143,7 +140,7 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
......@@ -151,19 +148,19 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -181,7 +178,6 @@ WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
Section 3 - Informational
-------------------------
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
INFO:LIT:395 - The above info message is repeated 271 more times for the
following (max. 5 shown):
......
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