Commit 365e3f48 authored by egousiou's avatar egousiou

- hdl: corrected misalignment between wrabbit_tai_p and arrival of a new wrabbit_tai second


git-svn-id: http://svn.ohwr.org/fmc-tdc@185 85dfdc96-de2c-444c-878d-45b388be74a9
parent a2393b49
......@@ -145,7 +145,7 @@ architecture rtl of data_formatting is
signal acam_start_nb_32 : unsigned(31 downto 0);
-- final timestamp fields
signal full_timestamp : std_logic_vector(127 downto 0);
signal metadata, local_utc, coarse_time, fine_time : std_logic_vector(31 downto 0);
signal metadata, utc, coarse_time, fine_time : std_logic_vector(31 downto 0);
-- circular buffer timestamp writings WISHBONE interface
signal tstamp_wr_cyc, tstamp_wr_stb, tstamp_wr_we : std_logic;
-- circular buffer counters
......@@ -378,7 +378,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The following process makes essential calculations for the definition of the coarse time.
-- Regarding the signals: un_clk_i_cycles_offset, un_retrig_nb_offset, local_utc it has to be defined
-- Regarding the signals: un_clk_i_cycles_offset, un_retrig_nb_offset, utc it has to be defined
-- if the values that characterize the current second or the one previous to it should be used.
-- In the case where: a timestamp came on the same retgigger after a new second
-- (un_current_retrig_from_roll_over is 0 and un_acam_start_nb = un_current_retrig_nb_offset)
......@@ -405,38 +405,31 @@ begin
begin
if rising_edge (clk_i) then
if rst_i ='1' then
un_clk_i_cycles_offset <= (others => '0');
un_retrig_nb_offset <= (others => '0');
un_retrig_from_roll_over <= (others => '0');
local_utc <= (others => '0');
coarse_zero <= '0';
un_clk_i_cycles_offset <= (others => '0');
un_retrig_nb_offset <= (others => '0');
un_retrig_from_roll_over <= (others => '0');
utc <= (others => '0');
coarse_zero <= '0';
else
-- ACAM tstamp arrived on the same retgigger after a new second
if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
-- ACAM tstamp arrived on the same retgigger after a new second
if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
(un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318 and (un_current_retrig_from_roll_over = 0) ) then
--if (un_acam_start_nb = un_current_retrig_nb_offset) or
-- (un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318) then
coarse_zero <= '1';
un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
un_retrig_nb_offset <= un_previous_retrig_nb_offset;
local_utc <= previous_utc;
-- ACAM tstamp arrived when roll_over has just increased
--if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
-- un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb-1, 8);
--else
un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb, 8);
--end if;
coarse_zero <= '1';
un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
un_retrig_nb_offset <= un_previous_retrig_nb_offset;
utc <= previous_utc;
un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb, 8);
else
un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
local_utc <= utc_i;
coarse_zero <= '0';
un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
utc <= utc_i;
coarse_zero <= '0';
if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i)-1, 8);
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i)-1, 8);
else
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i), 8);
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i), 8);
end if;
end if;
end if;
......@@ -474,7 +467,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
full_timestamp(31 downto 0) <= fine_time;
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(95 downto 64) <= local_utc;
full_timestamp(95 downto 64) <= utc;
full_timestamp(127 downto 96) <= metadata;
tstamp_wr_dat_o <= full_timestamp;
......
......@@ -651,7 +651,9 @@ begin
-- TRIG2(31 downto 0) <= utc(31 downto 0);
--
-- TRIG3(0) <= tdc_in_fpga_1_i;
-- TRIG3(31 downto 1) <= current_retrig_nb(30 downto 0);
-- TRIG3(1) <= roll_over_incr_recent;
-- TRIG3(2) <= wrabbit_tai_p_i;
-- TRIG3(31 downto 3) <= current_retrig_nb(28 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
......
......@@ -73,6 +73,7 @@
-- 07/2013 v1 EG First version |
-- 01/2014 v2 EG Different output for the timestamp data |
-- 01/2014 v3 EG Removed option for timestamps retrieval through DMA |
-- 08/2014 v4 EG Corrected missalignement between wrabbit_tai and wrabbit_tai_p (line 444) |
-- |
---------------------------------------------------------------------------------------------------
......@@ -436,14 +437,19 @@ begin
wrabbit_one_hz_pulse : process(clk_ref_0_i)
begin
if rising_edge(clk_ref_0_i) then
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
if unsigned(wrabbit_cycles_i) = unsigned(c_SYN_CLK_PERIOD) -1 then
wrabbit_utc_p <= '1';
if rst_ref_0_n = '0' then
wrabbit_utc_p <= '0';
else
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
if unsigned(wrabbit_cycles_i) = (unsigned(c_SYN_CLK_PERIOD)-3) then -- so that the end of the pulse
-- comes exactly upon the UTC change
wrabbit_utc_p <= '1';
else
wrabbit_utc_p <= '0';
end if;
else
wrabbit_utc_p <= '0';
wrabbit_utc_p <= '0';
end if;
else
wrabbit_utc_p <= '0';
end if;
end if;
end process;
......
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This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -10,14 +10,8 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 18:44:18 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapped Date : Tue Jul 08 10:27:13 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
......@@ -25,56 +19,56 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 18 secs
Total CPU time at the beginning of Placer: 16 secs
Total REAL time at the beginning of Placer: 21 secs
Total CPU time at the beginning of Placer: 17 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 20 secs
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 37 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 20 secs
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 38 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 20 secs
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 38 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:46e77852) REAL time: 52 secs
(Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 52 secs
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 52 secs
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 9.8 Global Placement
................................
....................................................................
...............................................................
......................
Phase 9.8 Global Placement (Checksum:bed8b73d) REAL time: 1 mins 24 secs
..................................
........................................................
........................................................
..........................
Phase 9.8 Global Placement (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:bed8b73d) REAL time: 1 mins 24 secs
Phase 10.5 Local Placement Optimization (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:d7b12fa8) REAL time: 1 mins 39 secs
Phase 11.18 Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:d7b12fa8) REAL time: 1 mins 40 secs
Phase 12.5 Local Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:ad8925d5) REAL time: 1 mins 40 secs
Phase 13.34 Placement Validation (Checksum:d7bfac99) REAL time: 1 mins 59 secs
Total REAL time to Placer completion: 1 mins 47 secs
Total CPU time to Placer completion: 1 mins 44 secs
Total REAL time to Placer completion: 2 mins 6 secs
Total CPU time to Placer completion: 1 mins 47 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -94,7 +88,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,896 out of 27,288 14%
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -107,18 +101,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 113
Number with same-slice register load: 67
Number with same-slice carry load: 46
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,433 out of 6,822 21%
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,679
Number with an unused Flip Flop: 1,407 out of 4,679 30%
Number with an unused LUT: 783 out of 4,679 16%
Number of fully used LUT-FF pairs: 2,489 out of 4,679 53%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
......@@ -174,9 +168,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 1 mins 51 secs
Total CPU time to MAP completion: 1 mins 48 secs
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 2 mins 11 secs
Total CPU time to MAP completion: 1 mins 52 secs
Mapping completed.
See MAP report file "spec_tdc_map.mrp" for details.
......@@ -10,7 +10,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 18:44:18 2014
Mapped Date : Tue Jul 08 10:27:13 2014
Design Summary
--------------
......@@ -22,7 +22,7 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,896 out of 27,288 14%
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
......@@ -35,18 +35,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 113
Number with same-slice register load: 67
Number with same-slice carry load: 46
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,433 out of 6,822 21%
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,679
Number with an unused Flip Flop: 1,407 out of 4,679 30%
Number with an unused LUT: 783 out of 4,679 16%
Number of fully used LUT-FF pairs: 2,489 out of 4,679 53%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
......@@ -102,9 +102,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 354 MB
Total REAL time to MAP completion: 1 mins 51 secs
Total CPU time to MAP completion: 1 mins 48 secs
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 2 mins 11 secs
Total CPU time to MAP completion: 1 mins 52 secs
Table of Contents
-----------------
......@@ -127,9 +127,6 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
......@@ -137,7 +134,6 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network button1_i has no load.
INFO:LIT:395 - The above info message is repeated 142 more times for the
following (max. 5 shown):
......
This diff is collapsed.
This diff is collapsed.
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 25 17:48:14 2014
Mapped Date : Tue Jul 08 10:59:56 2014
Mapping design into LUTs...
Running directed packing...
......@@ -21,56 +21,56 @@ INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 44 secs
Total CPU time at the beginning of Placer: 38 secs
Total CPU time at the beginning of Placer: 39 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:89307510) REAL time: 49 secs
Phase 1.1 Initial Placement Analysis (Checksum:2f07b54b) REAL time: 48 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:89307510) REAL time: 50 secs
Phase 2.7 Design Feasibility Check (Checksum:2f07b54b) REAL time: 49 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:476872d8) REAL time: 50 secs
Phase 3.31 Local Placement Optimization (Checksum:ed3fb313) REAL time: 49 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:87ab2a92) REAL time: 1 mins 38 secs
(Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 5.36 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 6.30 Global Clock Region Assignment (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 7.3 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:87ab2a92) REAL time: 1 mins 38 secs
Phase 8.5 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
Phase 9.8 Global Placement
.....................
...............................................................................................
............................................................................................................................................................................................
..........................................................................................................................................................................................
........................................................................
Phase 9.8 Global Placement (Checksum:e5911db4) REAL time: 5 mins 20 secs
........................
..................................................................................................
.................................................................................
..................................................................................................................................
..............................
Phase 9.8 Global Placement (Checksum:9fd444c4) REAL time: 5 mins
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:e5911db4) REAL time: 5 mins 21 secs
Phase 10.5 Local Placement Optimization (Checksum:9fd444c4) REAL time: 5 mins 1 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 6 secs
Phase 11.18 Placement Optimization (Checksum:887f371b) REAL time: 5 mins 47 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:675f2f74) REAL time: 6 mins 6 secs
Phase 12.5 Local Placement Optimization (Checksum:887f371b) REAL time: 5 mins 48 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:f1209e85) REAL time: 6 mins 7 secs
Phase 13.34 Placement Validation (Checksum:27e1a814) REAL time: 5 mins 48 secs
Total REAL time to Placer completion: 6 mins 25 secs
Total CPU time to Placer completion: 6 mins 17 secs
Total REAL time to Placer completion: 6 mins 7 secs
Total CPU time to Placer completion: 6 mins 1 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
......@@ -79,27 +79,27 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -127,11 +127,11 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,641 out of 27,288 38%
Number used as logic: 10,381 out of 27,288 38%
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 775
Number using O5 and O6: 2,232
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
......@@ -143,18 +143,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 193
Number with same-slice register load: 116
Number with same-slice carry load: 77
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,975 out of 6,822 58%
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,385
Number with an unused Flip Flop: 4,772 out of 12,385 38%
Number with an unused LUT: 1,744 out of 12,385 14%
Number of fully used LUT-FF pairs: 5,869 out of 12,385 47%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 992 out of 54,576 1%
......@@ -214,9 +214,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 37 secs
Total CPU time to MAP completion: 6 mins 28 secs
Peak Memory Usage: 476 MB
Total REAL time to MAP completion: 6 mins 19 secs
Total CPU time to MAP completion: 6 mins 12 secs
Mapping completed.
See MAP report file "wr_spec_tdc_map.mrp" for details.
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jun 25 17:48:14 2014
Mapped Date : Tue Jul 08 10:59:56 2014
Design Summary
--------------
......@@ -23,11 +23,11 @@ Slice Logic Utilization:
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 24
Number of Slice LUTs: 10,641 out of 27,288 38%
Number used as logic: 10,381 out of 27,288 38%
Number of Slice LUTs: 10,646 out of 27,288 39%
Number used as logic: 10,382 out of 27,288 38%
Number using O6 output only: 7,374
Number using O5 output only: 775
Number using O5 and O6: 2,232
Number using O5 output only: 777
Number using O5 and O6: 2,231
Number used as ROM: 0
Number used as Memory: 67 out of 6,408 1%
Number used as Dual Port RAM: 24
......@@ -39,18 +39,18 @@ Slice Logic Utilization:
Number using O6 output only: 22
Number using O5 output only: 0
Number using O5 and O6: 21
Number used exclusively as route-thrus: 193
Number with same-slice register load: 116
Number with same-slice carry load: 77
Number used exclusively as route-thrus: 197
Number with same-slice register load: 122
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,975 out of 6,822 58%
Number of occupied Slices: 4,050 out of 6,822 59%
Nummber of MUXCYs used: 2,388 out of 13,644 17%
Number of LUT Flip Flop pairs used: 12,385
Number with an unused Flip Flop: 4,772 out of 12,385 38%
Number with an unused LUT: 1,744 out of 12,385 14%
Number of fully used LUT-FF pairs: 5,869 out of 12,385 47%
Number of LUT Flip Flop pairs used: 12,451
Number with an unused Flip Flop: 4,848 out of 12,451 38%
Number with an unused LUT: 1,805 out of 12,451 14%
Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
Number of unique control sets: 372
Number of slice register sites lost
to control set restrictions: 992 out of 54,576 1%
......@@ -110,9 +110,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.59
Peak Memory Usage: 477 MB
Total REAL time to MAP completion: 6 mins 37 secs
Total CPU time to MAP completion: 6 mins 28 secs
Peak Memory Usage: 476 MB
Total REAL time to MAP completion: 6 mins 19 secs
Total CPU time to MAP completion: 6 mins 12 secs
Table of Contents
-----------------
......@@ -141,27 +141,27 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......
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......@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 17:22:57 2014
Mapped Date : Tue Jul 08 10:48:00 2014
Design Summary
--------------
......@@ -23,11 +23,11 @@ Slice Logic Utilization:
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,151 out of 92,152 17%
Number used as logic: 15,779 out of 92,152 17%
Number using O6 output only: 11,156
Number using O5 output only: 843
Number using O5 and O6: 3,780
Number of Slice LUTs: 16,122 out of 92,152 17%
Number used as logic: 15,780 out of 92,152 17%
Number using O6 output only: 11,157
Number using O5 output only: 844
Number using O5 and O6: 3,779
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
......@@ -39,18 +39,18 @@ Slice Logic Utilization:
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 285
Number with same-slice register load: 178
Number with same-slice carry load: 107
Number used exclusively as route-thrus: 255
Number with same-slice register load: 150
Number with same-slice carry load: 105
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,354 out of 23,038 27%
Number of occupied Slices: 6,416 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,631
Number with an unused Flip Flop: 7,987 out of 18,631 42%
Number with an unused LUT: 2,480 out of 18,631 13%
Number of fully used LUT-FF pairs: 8,164 out of 18,631 43%
Number of LUT Flip Flop pairs used: 18,651
Number with an unused Flip Flop: 7,970 out of 18,651 42%
Number with an unused LUT: 2,529 out of 18,651 13%
Number of fully used LUT-FF pairs: 8,152 out of 18,651 43%
Number of unique control sets: 502
Number of slice register sites lost
to control set restrictions: 1,224 out of 184,304 1%
......@@ -106,8 +106,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 6 mins 7 secs
Total CPU time to MAP completion: 5 mins 59 secs
Total REAL time to MAP completion: 6 mins 34 secs
Total CPU time to MAP completion: 6 mins 19 secs
Table of Contents
-----------------
......@@ -130,9 +130,6 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
......@@ -143,7 +140,7 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
......@@ -151,19 +148,19 @@ WARNING:PhysDesignRules:367 - The signal
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
......@@ -181,7 +178,6 @@ WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
Section 3 - Informational
-------------------------
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
INFO:LIT:395 - The above info message is repeated 271 more times for the
following (max. 5 shown):
......
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