Several fixes/features (sorry for big commit):

- fake timestamp generation option - fixed timestamp calculation in data_formatting.vhd Still a test bitstream, not fully functional.

Several fixes/features (sorry for big commit):
- fake timestamp generation option - fixed timestamp calculation in data_formatting.vhd Still a test bitstream, not fully functional.
338ea4a3 · Tomasz Wlostowski · 6b2e87d4 · 338ea4a3 · 338ea4a3 · 338ea4a3
Commit 338ea4a3 authored Aug 30, 2018 by Tomasz Wlostowski
14 changed files
--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
@@ -94,11 +94,15 @@ entity data_formatting is
     clk_i_cycles_offset_i   : in std_logic_vector(31 downto 0);
     roll_over_nb_i          : in std_logic_vector(31 downto 0);
     retrig_nb_offset_i      : in std_logic_vector(31 downto 0);
+     current_retrig_nb_i : in std_logic_vector(31 downto 0);
+     gen_fake_ts_enable_i  : in std_logic;
+     gen_fake_ts_period_i  : in std_logic_vector(27 downto 0);
+     gen_fake_ts_channel_i : in std_logic_vector(2 downto 0);
     -- Signal from the WRabbit core or the one_hz_generator unit
     utc_p_i : in std_logic;
     -- OUTPUTS
     timestamp_o       : out t_raw_acam_timestamp;
@@ -139,6 +143,15 @@ architecture rtl of data_formatting is
  signal previous_utc                                         : std_logic_vector(31 downto 0);
  signal timestamp_valid_int                                  : std_logic;
+  signal raw_seq : unsigned(27 downto 0);
+  signal fake_cnt_coarse : unsigned(27 downto 0);
+  signal fake_cnt_period : unsigned(27 downto 0);
+  signal fake_cnt_tai    : unsigned(31 downto 0);
+  signal fake_ts_valid   : std_logic;
+  signal timestamp_valid_int_d : std_logic;
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
@@ -152,6 +165,7 @@ begin
        timestamp_valid_int <= '0';
      else
        timestamp_valid_int <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
+        timestamp_valid_int_d <= timestamp_valid_int;
      end if;
    end if;
  end process;
@@ -200,13 +214,13 @@ begin
        acam_channel        <= "0" & acam_tstamp1_i(27 downto 26);
        acam_fine_timestamp <= acam_tstamp1_i(16 downto 0);
        acam_slope          <= acam_tstamp1_i(17);
-        acam_start_nb       <= unsigned(acam_tstamp1_i(25 downto 18))-1;
+        acam_start_nb       <= unsigned(acam_tstamp1_i(25 downto 18));
      elsif acam_tstamp2_ok_p_i = '1' then
        acam_channel        <= "1" & acam_tstamp2_i(27 downto 26);
        acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
        acam_slope          <= acam_tstamp2_i(17);
-        acam_start_nb       <= unsigned(acam_tstamp2_i(25 downto 18))-1;
+        acam_start_nb       <= unsigned(acam_tstamp2_i(25 downto 18));
      end if;
    end if;
  end process;
@@ -237,6 +251,7 @@ begin
  un_acam_start_nb                 <= unsigned(acam_start_nb_32);
  un_current_retrig_nb_offset      <= unsigned(retrig_nb_offset_i);
  un_current_roll_over_nb          <= unsigned(roll_over_nb_i);
  un_current_retrig_from_roll_over <= shift_left(un_current_roll_over_nb-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 and un_current_roll_over_nb > 0
                                      else shift_left(un_current_roll_over_nb, 8);
@@ -290,7 +305,7 @@ begin
          un_retrig_nb_offset    <= unsigned(retrig_nb_offset_i);
          utc                    <= utc_i;
          coarse_zero            <= '0';
-          if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
+          if acam_start_nb = 255 and unsigned(current_retrig_nb_i) = 0 then
            un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i)-1, 8);
          else
            un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i), 8);
@@ -336,19 +351,60 @@ begin
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if gen_fake_ts_enable_i = '0' then
+        fake_cnt_coarse <= (others => '0');
+        fake_cnt_tai    <= (others => '0');
+        fake_cnt_period <= (others => '0');
+      else
+        if unsigned(gen_fake_ts_period_i) = fake_cnt_period then
+          fake_cnt_period <= (others => '0');
+          fake_ts_valid   <= '1';
+        else
+          fake_cnt_period <= fake_cnt_period + 1;
+          fake_ts_valid   <= '0';
+        end if;
+        if fake_cnt_coarse = 124999999 then
+          fake_cnt_coarse <= (others => '0');
+          fake_cnt_tai    <= fake_cnt_tai + 1;
+        else
+          fake_cnt_coarse <= fake_cnt_coarse + 1;
+        end if;
+      end if;
+    end if;
+  end process;
  process(clk_i)
  begin
    if rising_edge(clk_i) then
-      if(timestamp_valid_int = '1') then
+      if rst_i = '1' then
-        timestamp_o.slope   <= acam_slope;
+        raw_seq <= (others => '0');
-        timestamp_o.channel <= acam_channel;
+      else
-        timestamp_o.n_bins  <= fine_time(16 downto 0);
+        if(gen_fake_ts_enable_i = '1' and fake_ts_valid = '1')then
-        timestamp_o.coarse  <= coarse_time;
+          timestamp_o.slope   <= '1';
-        timestamp_o.tai     <= utc;
+          timestamp_o.channel <= gen_fake_ts_channel_i;
-        timestamp_valid_o   <= '1';
+          timestamp_o.n_bins  <= (others => '0');
+          timestamp_o.coarse  <= std_logic_vector(resize(fake_cnt_coarse, 32));
+          timestamp_o.tai     <= std_logic_vector(fake_cnt_tai);
+          timestamp_o.seq     <= std_logic_vector(raw_seq);
+          timestamp_valid_o   <= '1';
+          raw_seq             <= raw_seq + 1;
+        elsif(timestamp_valid_int_d = '1') then
+          timestamp_o.slope   <= acam_slope;
+          timestamp_o.channel <= acam_channel;
+          timestamp_o.n_bins  <= fine_time(16 downto 0);
+          timestamp_o.coarse  <= coarse_time; 
+          timestamp_o.tai     <= utc; 
+          timestamp_o.seq     <= std_logic_vector(raw_seq);
+          timestamp_valid_o   <= '1';
+          raw_seq             <= raw_seq + 1;
      else
        timestamp_valid_o <= '0';
+        end if;
      end if;
    end if;
  end process;

--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
@@ -269,10 +269,18 @@ architecture rtl of fmc_tdc_core is
  signal final_timestamp       : t_tdc_timestamp_array(4 downto 0);
-  signal channel_enable_int : std_logic_vector(4 downto 0);
+  signal channel_enable_tdc : std_logic_vector(4 downto 0);
+  signal channel_enable_sys : std_logic_vector(4 downto 0);
  signal rst_sys, rst_tdc : std_logic;
  signal core_status : std_logic_vector(31 downto 0);
+  signal gen_fake_ts_enable : std_logic;
+  signal gen_fake_ts_channel : std_logic_vector(2 downto 0);
+  signal gen_fake_ts_period : std_logic_vector(27 downto 0);
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
@@ -329,7 +337,11 @@ begin
     irq_time_threshold_o   => irq_time_threshold,
     send_dac_word_p_o      => send_dac_word_p_o,
     dac_word_o             => dac_word_o,
-     one_hz_phase_o         => pulse_delay);
+     one_hz_phase_o         => pulse_delay,
+     gen_fake_ts_period_o => gen_fake_ts_period,
+     gen_fake_ts_enable_o => gen_fake_ts_enable,
+     gen_fake_ts_channel_o => gen_fake_ts_channel
+     );
  process(clk_tdc_i)
  begin
@@ -512,8 +524,12 @@ begin
     clk_i_cycles_offset_i   => clk_i_cycles_offset,
     roll_over_nb_i          => roll_over_nb,
     retrig_nb_offset_i      => retrig_nb_offset,
+     current_retrig_nb_i => current_retrig_nb,
     utc_p_i                 => utc_p,
     utc_i                   => utc,
+     gen_fake_ts_period_i => gen_fake_ts_period,
+     gen_fake_ts_enable_i => gen_fake_ts_enable,
+     gen_fake_ts_channel_i => gen_fake_ts_channel,
     timestamp_o             => raw_timestamp,
     timestamp_valid_o       => raw_timestamp_valid
     );
@@ -526,7 +542,7 @@ begin
      clk_sys_i   => clk_sys_i,
      rst_sys_n_i => rst_sys_n_i,
-      enable_i   => channel_enable_int,
+      enable_i   => channel_enable_sys,
      ts_i       => raw_timestamp,
      ts_valid_i => raw_timestamp_valid,
      ts_o       => final_timestamp,
@@ -573,8 +589,17 @@ begin
 --------------------------------------------------------------------------------------------------- 
  start_dis_o <= '0';
-  channel_enable_int <= acam_inputs_en(20 downto 16);
+  U_Sync_ChannelEnable: entity work.gc_sync_register
-  channel_enable_o   <= channel_enable_int;
+    generic map (
+      g_width => 5)
+    port map (
+      clk_i     => clk_sys_i,
+      rst_n_a_i => rst_sys_n_i,
+      d_i       => channel_enable_tdc,
+      q_o       => channel_enable_sys);
+  channel_enable_tdc <= acam_inputs_en(20 downto 16);
+  channel_enable_o   <= channel_enable_sys;
 end rtl;
 ----------------------------------------------------------------------------------------------------

--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
@@ -433,6 +433,8 @@ begin
    timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
  end generate gen_fifos;
+  timestamp_ready <= (others => '1');
  gen_with_dma_readout : if g_use_dma_readout generate
    U_DMA_Engine : entity work.tdc_dma_engine
      generic map (
@@ -440,9 +442,10 @@ begin
      port map (
        clk_i      => clk_sys_i,
        rst_n_i    => rst_sys_n_i,
+        enable_i => channel_enable,
        ts_i       => timestamp,
        ts_valid_i => timestamp_valid,
-        ts_ready_o => timestamp_ready,
+--        ts_ready_o => timestamp_ready,
        slave_i    => cnx_master_out(c_WB_SLAVE_TDC_DMA),
        slave_o    => cnx_master_in(c_WB_SLAVE_TDC_DMA),
        irq_o      => irq_dma,

--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -128,6 +128,11 @@ entity reg_ctrl is
      acam_rdbk_ififo2_p_o  : out std_logic;  -- enables reading of ACAM reg 9
      acam_rdbk_start01_p_o : out std_logic;  -- enables reading of ACAM reg 10
+      gen_fake_ts_enable_o  : out std_logic;
+      gen_fake_ts_period_o  : out std_logic_vector(27 downto 0);
+      gen_fake_ts_channel_o : out std_logic_vector(2 downto 0);
      -- Signals to the clks_resets_manager unit
      send_dac_word_p_o : out std_logic;  -- initiates the reconfiguration of the DAC
      dac_word_o        : out std_logic_vector(23 downto 0);
@@ -351,6 +356,8 @@ begin
        irq_time_threshold   <= x"00000001";  -- default 200 ms
        dac_word             <= c_DEFAULT_DAC_WORD;  -- default DAC Vout = 1.65
+        gen_fake_ts_enable_o <= '0';
      elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
        if reg_adr = c_STARTING_UTC_ADR then
@@ -385,6 +392,12 @@ begin
          wrabbit_ctrl_reg <= wb_in.dat;
        end if;
+        if reg_adr = c_TEST0_ADR then
+          gen_fake_ts_enable_o <= wb_in.dat(31);
+          gen_fake_ts_channel_o <= wb_in.dat(30 downto 28);
+          gen_fake_ts_period_o <= wb_in.dat(27 downto 0);
+        end if;
      end if;
    end if;

--- a/hdl/rtl/tdc_core_pkg.vhd
+++ b/hdl/rtl/tdc_core_pkg.vhd
@@ -67,9 +67,11 @@ package tdc_core_pkg is
    n_bins : std_logic_vector(16 downto 0);
    coarse : std_logic_vector(31 downto 0);
    tai : std_logic_vector(31 downto 0);
+    seq : std_logic_vector(27 downto 0);
  end record;
  type t_tdc_timestamp is record
+    raw : t_raw_acam_timestamp;
    slope : std_logic;
    channel : std_logic_vector(2 downto 0);
    frac : std_logic_vector(11 downto 0);
@@ -79,7 +81,7 @@ package tdc_core_pkg is
  end record;
  constant c_dummy_timestamp : t_tdc_timestamp :=
-    ( '0', "000", x"000", x"00000000", x"00000000", x"00000000" );
+    ( ( '0', "000", "00000000000000000", x"00000000", x"00000000", x"0000000" ), '0', "000", x"000", x"00000000", x"00000000", x"00000000" );
  type t_tdc_timestamp_array is array(integer range<>) of t_tdc_timestamp;
@@ -323,6 +325,8 @@ package tdc_core_pkg is
  constant c_WRABBIT_STATUS_ADR   : std_logic_vector(7 downto 0) := x"2C"; -- address 0x510B0 of GN4124 BAR 0
  constant c_WRABBIT_CTRL_ADR     : std_logic_vector(7 downto 0) := x"2D"; -- address 0x510B4 of GN4124 BAR 0
+  constant c_TEST0_ADR     : std_logic_vector(7 downto 0) := x"2E"; -- address 0x510B4 of GN4124 BAR 0
 ---------------------------------------------------------------------------------------------------
 -- Address of TDC core Control register
                                                                           -- corresponds to:
@@ -711,7 +715,11 @@ package tdc_core_pkg is
      one_hz_phase_o         : out std_logic_vector(g_width-1 downto 0);
      acam_inputs_en_o       : out std_logic_vector(g_width-1 downto 0);
      wrabbit_ctrl_reg_o     : out std_logic_vector(g_width-1 downto 0);
-      start_phase_o          : out std_logic_vector(g_width-1 downto 0));
+      start_phase_o          : out std_logic_vector(g_width-1 downto 0);
+      gen_fake_ts_enable_o  : out std_logic;
+      gen_fake_ts_period_o  : out std_logic_vector(27 downto 0);
+      gen_fake_ts_channel_o : out std_logic_vector(2 downto 0)
+    );
  end component reg_ctrl;
 ---------------------------------------------------------------------------------------------------
  component acam_timecontrol_interface
@@ -748,6 +756,9 @@ package tdc_core_pkg is
      roll_over_nb_i          : in  std_logic_vector(31 downto 0);
      retrig_nb_offset_i      : in  std_logic_vector(31 downto 0);
      utc_p_i                 : in  std_logic;
+      gen_fake_ts_enable_i  : in std_logic;
+      gen_fake_ts_period_i  : in std_logic_vector(27 downto 0);
+      gen_fake_ts_channel_i : in std_logic_vector(2 downto 0);
      timestamp_o             : out std_logic_vector(127 downto 0);
      timestamp_valid_o       : out std_logic);
  end component data_formatting;

--- a/hdl/rtl/tdc_dma_channel.vhd
+++ b/hdl/rtl/tdc_dma_channel.vhd
@@ -14,6 +14,8 @@ entity tdc_dma_channel is
    clk_i : in std_logic;
    rst_n_i   : in std_logic;
+    enable_i : in std_logic;
    ts_i       : in  t_tdc_timestamp;
    ts_valid_i : in  std_logic;
    ts_ready_o : out std_logic;
@@ -103,7 +105,7 @@ begin
  p_irq_timer : process(clk_i)
  begin
    if rising_edge(clk_i) then
-      if rst_n_i = '0' then
+      if rst_n_i = '0' or enable_i = '0' then
        irq_timer <= (others => '0');
        irq_o     <= '0';
      else
@@ -198,7 +200,9 @@ begin
              state <= SWITCH_BUFFERS;
            end if;
-            if regs_out.tdc_buf_csr_enable_o = '1' and ts_valid_i = '1' then
+            if enable_i = '1' and regs_out.tdc_buf_csr_enable_o = '1' and ts_valid_i = '1' then
              if cur_valid = '1' then
@@ -226,7 +230,7 @@ begin
          when WAIT_NEXT_TS =>
            fifo_in_is_addr <= '0';
-            if regs_out.tdc_buf_csr_enable_o = '0' or burst_count = unsigned(regs_out.tdc_buf_csr_burst_size_o) or buffer_switch_latched = '1' then
+            if enable_i = '0' or regs_out.tdc_buf_csr_enable_o = '0' or burst_count = unsigned(regs_out.tdc_buf_csr_burst_size_o) or buffer_switch_latched = '1' then
              burst_add <= '1';
              state     <= IDLE;
            elsif ts_valid_i = '1' then
@@ -245,22 +249,22 @@ begin
 --  bit  2-0 chan  (mask: 0x7)
          when SER0 =>
-            fifo_in_data    <= ts.tai;
+            fifo_in_data    <= ts.raw.tai;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER1;
          when SER1 =>
-            fifo_in_data    <= ts.coarse;
+            fifo_in_data    <= ts.raw.coarse;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER2;
          when SER2 =>
-            fifo_in_data    <= x"00000" & ts.frac;
+            fifo_in_data    <= "000000000000000" & ts.raw.n_bins;
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= SER3;
          when SER3 =>
-            fifo_in_data    <= ts.seq(27 downto 0) & ts.slope & ts.channel(2 downto 0);
+            fifo_in_data    <= ts.raw.seq(27 downto 0) & ts.raw.slope & ts.raw.channel(2 downto 0);
            fifo_in_is_addr <= '0';
            fifo_wr         <= '1';
            state           <= WAIT_NEXT_TS;

--- a/hdl/rtl/tdc_dma_engine.vhd
+++ b/hdl/rtl/tdc_dma_engine.vhd
@@ -16,6 +16,8 @@ entity tdc_dma_engine is
    clk_i : in std_logic;
    rst_n_i   : in std_logic;
+    enable_i : in std_logic_vector(4 downto 0);
    ts_i       : in  t_tdc_timestamp_array(4 downto 0);
    ts_valid_i : in  std_logic_vector(4 downto 0);
    ts_ready_o : out std_logic_vector(4 downto 0);
@@ -114,6 +116,7 @@ begin
      port map (
        clk_i      => clk_i,
        rst_n_i    => rst_n_i,
+        enable_i => enable_i(i),
        ts_i       => ts_i(i),
        ts_valid_i => ts_valid_i(i),
        ts_ready_o => ts_ready_o(i),

--- a/hdl/rtl/timestamp_convert_filter.vhd
+++ b/hdl/rtl/timestamp_convert_filter.vhd
@@ -20,6 +20,7 @@ entity timestamp_convert_filter is
    ts_valid_i : in std_logic;
    -- converted and filtered timestamp output, clk_sys_i domain
+--    ts_offset_i : in t_tdc_timestamp_array(4 downto 0);
    ts_o       : out t_tdc_timestamp_array(4 downto 0);
    ts_valid_o : out std_logic_vector(4 downto 0);
    ts_ready_i : in std_logic_vector(4 downto 0)
@@ -64,6 +65,8 @@ architecture rtl of timestamp_convert_filter is
  signal s3_ts : t_tdc_timestamp;
  signal ts_valid_sys : std_logic;
+  signal ts_latched : t_raw_acam_timestamp;
 begin
@@ -79,6 +82,16 @@ begin
      d_p_i       => ts_valid_i,
      q_p_o       => ts_valid_sys);
+  process(clk_tdc_i)
+  begin
+    if rising_edge(clk_tdc_i) then
+      if ts_valid_i = '1' then
+        ts_latched <= ts_i;
+      end if;
+    end if;
+  end process;
  process(clk_sys_i)
  begin
@@ -151,58 +164,71 @@ begin
        else
          channels(i).s1_valid <= '0';
+          if(ts_ready_i(i) = '1') then
+            ts_valid_o(i) <= '0';
+          end if;
-          if s3_valid = '1' and unsigned(s3_channel) = i then
+          if( ts_valid_sys = '1' and ts_latched.slope = '1' )then
--            report "s3_valid";
+            ts_o(i).raw <= ts_latched;
+            ts_o(i).seq <= std_logic_vector(channels(i).seq);
-            if (s3_ts.slope = '1') then  -- rising edge
+            if( i = unsigned( ts_i.channel ) ) then
-              channels(i).last_ts    <= s3_ts;
+              ts_valid_o(i) <=  '1';
-              channels(i).last_valid <= '1';
+              channels(i).seq <= channels(i).seq + 1;
-              channels(i).s1_valid   <= '0';
-  --            report "rise";
-            else
-              channels(i).last_valid <= '0';
-              channels(i).s1_valid   <= '1';
-    --          report "fall";
            end if;
+          end if;
-            channels(i).s1_delta_coarse <= unsigned(s3_ts.coarse) - unsigned(channels(i).last_ts.coarse);
-            channels(i).s1_delta_tai    <= unsigned(s3_ts.tai) - unsigned(channels(i).last_ts.tai);
+--          if s3_valid = '1' and unsigned(s3_channel) = i then
+----            report "s3_valid";
-          end if;
+--            if (s3_ts.slope = '1') then  -- rising edge
+----              channels(i).last_ts    <= s3_ts;
+--  --            channels(i).last_valid <= '1';
+--    --          channels(i).s1_valid   <= '0';
+--  --            report "rise";
+--            else
+--              channels(i).last_valid <= '0';
+--              channels(i).s1_valid   <= '1';
+--    --          report "fall";
+--            end if;
+--            channels(i).s1_delta_coarse <= unsigned(s3_ts.coarse) - unsigned(channels(i).last_ts.coarse);
+--            channels(i).s1_delta_tai    <= unsigned(s3_ts.tai) - unsigned(channels(i).last_ts.tai);
-          if channels(i).s1_delta_coarse(31) = '1' then
+--          end if;
-            channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse + to_unsigned(125000000, 32);
-            channels(i).s2_delta_tai    <= channels(i).s1_delta_tai - 1;
-          else
-            channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse;
-            channels(i).s2_delta_tai    <= channels(i).s1_delta_tai;
-          end if;
-          channels(i).s2_valid <= channels(i).s1_valid;
+--          if channels(i).s1_delta_coarse(31) = '1' then
+--            channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse + to_unsigned(125000000, 32);
+--            channels(i).s2_delta_tai    <= channels(i).s1_delta_tai - 1;
+--          else
+--            channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse;
+--            channels(i).s2_delta_tai    <= channels(i).s1_delta_tai;
+--          end if;
+--          channels(i).s2_valid <= channels(i).s1_valid;
-          if(ts_ready_i(i) = '1') then
-            ts_valid_o(i) <= '0';
-          end if;
-          if channels(i).s2_valid = '1' then
+--          if channels(i).s2_valid = '1' then
-            if channels(i).s2_delta_tai = 0 and channels(i).s2_delta_coarse >= 12 then
+--            if channels(i).s2_delta_tai = 0 and channels(i).s2_delta_coarse >= 12 then
-              ts_o(i).tai       <= channels(i).last_ts.tai;
+--              ts_o(i).tai       <= channels(i).last_ts.tai;
-              ts_o(i).coarse       <= channels(i).last_ts.coarse;
+--              ts_o(i).coarse       <= channels(i).last_ts.coarse;
-              ts_o(i).frac       <= channels(i).last_ts.frac;
+--              ts_o(i).frac       <= channels(i).last_ts.frac;
-              ts_o(i).channel       <= channels(i).last_ts.channel;
+--              ts_o(i).channel       <= channels(i).last_ts.channel;
-              ts_o(i).slope       <= channels(i).last_ts.slope;
+--              ts_o(i).slope       <= channels(i).last_ts.slope;
-              ts_o(i).seq <= std_logic_vector(channels(i).seq);
+--              ts_o(i).seq <= std_logic_vector(channels(i).seq);
-              ts_valid_o(i) <= '1';
+--              ts_valid_o(i) <= '1';
-              channels(i).seq <= channels(i).seq + 1;
+--              channels(i).seq <= channels(i).seq + 1;
-            end if;
+--            end if;
-          end if;
+--          end if;

--- a/hdl/rtl/timestamp_fifo.vhd
+++ b/hdl/rtl/timestamp_fifo.vhd
@@ -78,13 +78,22 @@ signal ref_valid : std_logic;
 begin
-  timestamp_with_seq(31 downto 0)    <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
+  --timestamp_with_seq(31 downto 0)    <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
-  timestamp_with_seq(63 downto 32)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
+  --timestamp_with_seq(63 downto 32)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
-  timestamp_with_seq(95 downto 64)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).frac), 32));
+  --timestamp_with_seq(95 downto 64)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).frac), 32));
-  timestamp_with_seq(98 downto 96)   <= timestamp_i(g_channel).channel;
+  --timestamp_with_seq(98 downto 96)   <= timestamp_i(g_channel).channel;
-  timestamp_with_seq(99)            <= timestamp_i(g_channel).slope;
+  --timestamp_with_seq(99)            <= timestamp_i(g_channel).slope;
+  --timestamp_with_seq(127 downto 100) <= timestamp_i(g_channel).seq(27 downto 0);
+  timestamp_with_seq(31 downto 0)    <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).raw.tai), 32));
+  timestamp_with_seq(63 downto 32)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).raw.coarse), 32));
+  timestamp_with_seq(95 downto 64)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).raw.n_bins), 32));
+  timestamp_with_seq(98 downto 96)   <= timestamp_i(g_channel).raw.channel;
+  timestamp_with_seq(99)            <= timestamp_i(g_channel).raw.slope;
  timestamp_with_seq(127 downto 100) <= timestamp_i(g_channel).seq(27 downto 0);
  U_WB_Slave : entity work.timestamp_fifo_wb
    port map (
      rst_n_i   => rst_sys_n_i,

--- a/hdl/syn/spec/wr_spec_tdc.xise
+++ b/hdl/syn/spec/wr_spec_tdc.xise
@@ -157,7 +157,7 @@
    </file>
    <file xil_pn:name="../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
    </file>
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
@@ -185,7 +185,7 @@
    </file>
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
    </file>
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
@@ -241,7 +241,7 @@
    </file>
    <file xil_pn:name="../../top/spec/wr_spec_tdc.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
    </file>
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
@@ -329,7 +329,7 @@
    </file>
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
    </file>
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
@@ -357,7 +357,7 @@
    </file>
    <file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
    </file>
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
@@ -709,7 +709,7 @@
    </file>
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="176"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
    </file>
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="177"/>
@@ -891,6 +891,10 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="272"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
    </file>
+    <file xil_pn:name="../../rtl/dma_eic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="273"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
+    </file>
  </files>
  <properties>
@@ -1094,6 +1098,7 @@
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -1125,7 +1130,7 @@
    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>

--- a/hdl/top/spec/wr_spec_tdc.ucf
+++ b/hdl/top/spec/wr_spec_tdc.ucf
@@ -523,7 +523,6 @@ NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
 NET "gn_rst_n" TIG;
 #NET "gen_with_gennum/cmp_gn4124_core/rst_*" TIG;
 #NET "gen_with_gennum/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
 NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
 TIMESPEC ts_ignore_crossclock = FROM "clk_sys_62m5" TO "tdc_clk_125m_p_i" 10ns DATAPATHONLY;
 TIMESPEC ts_ignore_crossclock2 = FROM "tdc_clk_125m_p_i" TO "clk_sys_62m5" 10ns  DATAPATHONLY;
@@ -538,16 +537,22 @@ TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_sys_62m5" 10ns DATAPATHONLY;
 NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
 TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
-TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
+#TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
 NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
 NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
-NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
+#NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/07/26
 NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback;
 TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
 NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk;
 TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
+NET "gn_rst_n" TIG;
+# NET "*/cmp_gn4124_core/rst_*" TIG;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/08/24
+NET "gen_with_gennum.cmp_gn4124_core/rst_reg_d" TIG;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/08/27
--- a/hdl/top/spec/wr_spec_tdc.vhd
+++ b/hdl/top/spec/wr_spec_tdc.vhd
@@ -517,6 +517,9 @@ architecture rtl of wr_spec_tdc is
  -- Clocks and resets
  signal clk_sys_62m5              : std_logic;
  signal rst_sys_62m5_n            : std_logic;
+  signal clk_ref_125m : std_logic;
+  signal rst_ref_125_n : std_logic;
  -- DAC configuration through PCIe/VME
  -- WISHBONE from crossbar master port
  signal cnx_master_out            : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
@@ -526,7 +529,9 @@ architecture rtl of wr_spec_tdc is
  signal cnx_slave_in              : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
  signal gn_wb_adr                 : std_logic_vector(31 downto 0);
  -- Carrier CSR info
+  signal gn4124_clk : std_logic;
  signal gn4124_status             : std_logic_vector(31 downto 0);
+  signal gn4124_ext_status             : std_logic_vector(31 downto 0);
  -- VIC
  signal irq_to_gn4124             : std_logic;
  -- WRabbit time
@@ -578,6 +583,7 @@ architecture rtl of wr_spec_tdc is
  signal dma_irq              : std_logic_vector(1 downto 0);
  signal ddr_wr_fifo_empty    : std_logic;
  signal dma_eic_irq : std_logic;
+  signal gn4124_dbg : std_logic_vector(127 downto 0);
  component chipscope_icon
    port (
@@ -598,6 +604,12 @@ architecture rtl of wr_spec_tdc is
  signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
+  attribute keep : string;
+  attribute keep of trig0 : signal is "true";
+  attribute keep of trig1 : signal is "true";
+  attribute keep of trig2 : signal is "true";
+  attribute keep of trig3 : signal is "true";
  signal ddr3_status : std_logic_vector(31 downto 0);
  function f_to_string(x : boolean) return string is
@@ -639,7 +651,8 @@ begin
      g_with_external_clock_input => false,
      g_aux_clks                  => 1,
      g_dpram_initf               => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
-      g_fabric_iface              => PLAIN)
+      g_fabric_iface              => PLAIN,
+      g_enable_wr_core => false)
    port map (
      areset_n_i              => button1_i,
      areset_edge_n_i         => gn_rst_n,
@@ -649,9 +662,11 @@ begin
      clk_125m_gtp_n_i        => clk_125m_gtp_n_i,
      clk_125m_gtp_p_i        => clk_125m_gtp_p_i,
      clk_ddr_o => clk_ddr_333m,
+      clk_ref_125m_o => clk_ref_125m,
      clk_sys_62m5_o          => clk_sys_62m5,
      clk_aux_i(0)            => tdc0_clk_125m,
      rst_sys_62m5_n_o        => rst_sys_62m5_n,
+      rst_ref_125m_n_o => rst_ref_125_n,
      plldac_sclk_o           => wr_dac_sclk_o,
      plldac_din_o            => wr_dac_din_o,
      pll25dac_cs_n_o         => wr_25dac_cs_n_o,
@@ -738,6 +753,8 @@ begin
      port map
      (rst_n_a_i    => gn_rst_n,
       status_o     => gn4124_status,
+       ext_status_o     => gn4124_ext_status,
+       sys_clk_o => gn4124_clk,
       ---------------------------------------------------------
       -- P2L Direction
       --
@@ -788,7 +805,8 @@ begin
       csr_err_i   => '0',
       csr_rty_i   => '0',
       csr_int_i   => '0',
-       dma_clk_i   => clk_sys_62m5,
+       dma_clk_i   => clk_ref_125m,
       dma_adr_o   => wb_dma_adr,
       dma_dat_o   => wb_dma_dat_o,
       dma_sel_o   => wb_dma_sel,
@@ -812,7 +830,9 @@ begin
       dma_reg_cyc_i   => cnx_master_out(c_WB_SLAVE_DMA).cyc,
       dma_reg_dat_o   => cnx_master_in(c_WB_SLAVE_DMA).dat,
       dma_reg_ack_o   => cnx_master_in(c_WB_SLAVE_DMA).ack,
-       dma_reg_stall_o => cnx_master_in(c_WB_SLAVE_DMA).stall
+       dma_reg_stall_o => cnx_master_in(c_WB_SLAVE_DMA).stall,
+       dbg_o => gn4124_dbg
       );
@@ -965,7 +985,7 @@ begin
     carrier_info_carrier_reserved_i   => (others => '0'),
     carrier_info_carrier_type_i       => c_CARRIER_TYPE,
     carrier_info_stat_fmc_pres_i      => prsnt_m2c_n_i,
-     carrier_info_stat_p2l_pll_lck_i   => gn4124_status(0),
+     carrier_info_stat_p2l_pll_lck_i   => '1', --gn4124_status(0),
     -- SPEC board wrapper releases rst_sys_62m5_n only when system clock pll is
     -- locked. Therefore we report here '1' - pll locked
     carrier_info_stat_sys_pll_lck_i   => '1',
@@ -1048,8 +1068,8 @@ begin
      p0_wr_underrun_o => open,
      p0_wr_error_o    => open,
-      wb1_rst_n_i => rst_sys_62m5_n,
+      wb1_rst_n_i => rst_ref_125_n,
-      wb1_clk_i   => clk_sys_62m5,
+      wb1_clk_i   => clk_ref_125m,
      wb1_sel_i   => wb_dma_sel,
      wb1_cyc_i   => wb_dma_cyc,
      wb1_stb_i   => wb_dma_stb,
@@ -1078,31 +1098,6 @@ begin
  ddr3_tdc_adr <= "00" & tdc_dma_out.adr(31 downto 2);
-  --CS_ICON : chipscope_icon
-  --  port map (
-  --    CONTROL0 => CONTROL0);
-  --CS_ILA : chipscope_ila
-  --  port map (
-  --    CONTROL => CONTROL0,
-  --    CLK     => clk_sys_62m5,
-  --    TRIG0   => TRIG0,
-  --    TRIG1   => TRIG1,
-  --    TRIG2   => TRIG2,
-  --    TRIG3   => TRIG3);
-  trig0(0) <= ddr3_calib_done;
-  trig0(1) <= wb_dma_cyc;
-  trig0(2) <= wb_dma_we;
-  trig0(3) <= wb_dma_stb;
-  trig0(4) <= wb_dma_ack;
-  trig0(5) <= wb_dma_stall;
-  trig0(6) <= irq_to_gn4124;
-  trig0(7) <= tdc0_irq;
-  trig0(8) <= dma_irq(0);
-  trig1 <= wb_dma_dat_o;
-  trig2 <= wb_dma_dat_i;
-  trig3 <= wb_dma_adr;
  ddr3_calib_done <= ddr3_status(0);

--- a/hdl/top/svec/Manifest.py
+++ b/hdl/top/svec/Manifest.py
@@ -13,8 +13,7 @@ modules = {
 	    ],
    "git" : [ 
        "git://ohwr.org/hdl-core-lib/general-cores.git",
-        "git://ohwr.org/hdl-core-lib/vme64x-core.git",
+        "git://ohwr.org/hdl-core-lib/vme64x-core.git"
-        "git://ohwr.org/hdl-core-lib/etherbone-core.git",
        ],
    }
--- a/hdl/top/svec/wr_svec_tdc.vhd
+++ b/hdl/top/svec/wr_svec_tdc.vhd
@@ -576,7 +576,7 @@ begin
 ---------------------------------------------------------------------------------------------------
 --                                           VME CORE                                            --
 ---------------------------------------------------------------------------------------------------
-  U_VME_Core : xvme64x_core
+  U_VME_Core : entity work.xvme64x_core
  generic map (
    g_CLOCK_PERIOD    => 16,
    g_DECODE_AM       => True,
@@ -615,7 +615,8 @@ begin
     vme_o.addr_dir   => vme_addr_dir_int,
     vme_o.addr_oe_n  => vme_addr_oe_n_o,
     wb_o             => cnx_slave_in(c_MASTER_VME),
-     wb_i             => vme_wb_in);
+     wb_i             => vme_wb_in,
+     int_i => irq_to_vmecore);
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  vme_berr_o <= not vme_berr_n;
  vme_irq_o  <= not vme_irq_n;
@@ -626,7 +627,6 @@ begin
  vme_wb_in.rty      <= cnx_slave_out(c_MASTER_VME).rty;
  vme_wb_in.stall    <= cnx_slave_out(c_MASTER_VME).stall;
  vme_wb_in.dat      <= cnx_slave_out(c_MASTER_VME).dat;
-  vme_wb_in.int      <= irq_to_vmecore;
  -- VME tri-state bufferes
  vme_data_b         <= vme_data_b_out    when vme_data_dir_int = '1' else (others => 'Z');
@@ -683,11 +683,6 @@ begin
      tdc_led_trig3_o      => tdc1_led_trig3_o,
      tdc_led_trig4_o      => tdc1_led_trig4_o,
      tdc_led_trig5_o      => tdc1_led_trig5_o,
-      tdc_in_fpga_1_i      => tdc1_in_fpga_1_i,
-      tdc_in_fpga_2_i      => tdc1_in_fpga_2_i,
-      tdc_in_fpga_3_i      => tdc1_in_fpga_3_i,
-      tdc_in_fpga_4_i      => tdc1_in_fpga_4_i,
-      tdc_in_fpga_5_i      => tdc1_in_fpga_5_i,
      mezz_scl_i           => tdc1_scl_in,
      mezz_sda_i           => tdc1_sda_in,
@@ -760,11 +755,6 @@ begin
      tdc_led_trig3_o      => tdc2_led_trig3_o,
      tdc_led_trig4_o      => tdc2_led_trig4_o,
      tdc_led_trig5_o      => tdc2_led_trig5_o,
-      tdc_in_fpga_1_i      => tdc2_in_fpga_1_i,
-      tdc_in_fpga_2_i      => tdc2_in_fpga_2_i,
-      tdc_in_fpga_3_i      => tdc2_in_fpga_3_i,
-      tdc_in_fpga_4_i      => tdc2_in_fpga_4_i,
-      tdc_in_fpga_5_i      => tdc2_in_fpga_5_i,
      mezz_scl_i           => tdc2_scl_in,
      mezz_sda_i           => tdc2_sda_in,
@@ -857,7 +847,6 @@ begin
  -- Unused wishbone signals
  cnx_master_in(c_SLAVE_SVEC_INFO).err   <= '0';
  cnx_master_in(c_SLAVE_SVEC_INFO).rty   <= '0';
-  cnx_master_in(c_SLAVE_SVEC_INFO).int   <= '0';
 ---------------------------------------------------------------------------------------------------