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FMC TDC 1ns 5cha - Gateware
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FMC TDC 1ns 5cha - Gateware
Commits
e4906dab
Commit
e4906dab
authored
Oct 15, 2020
by
Tristan Gingold
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testbench/spec: adjust Manifest.py
parent
9fbbe697
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30 additions
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3 deletions
+30
-3
Manifest.py
hdl/testbench/spec/Manifest.py
+30
-3
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hdl/testbench/spec/Manifest.py
View file @
e4906dab
...
@@ -3,12 +3,17 @@ top_module="main"
...
@@ -3,12 +3,17 @@ top_module="main"
syn_device
=
"xc6slx45t"
syn_device
=
"xc6slx45t"
sim_top
=
"main"
sim_top
=
"main"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../../ip_cores"
action
=
"simulation"
action
=
"simulation"
target
=
"xilinx"
target
=
"xilinx"
fetchto
=
"../../ip_cores"
include_dirs
=
[
"../../sim"
,
"../include"
]
include_dirs
=
[
"../../sim"
,
"../include"
]
vcom_opt
=
"-mixedsvvh l"
vcom_opt
=
"-mixedsvvh l"
# For wr-cores
board
=
'spec'
include_dirs
=
[
include_dirs
=
[
"../include"
,
"../include"
,
"../../sim"
,
"../../sim"
,
...
@@ -23,10 +28,23 @@ include_dirs = [
...
@@ -23,10 +28,23 @@ include_dirs = [
files
=
[
files
=
[
"main.sv"
,
"main.sv"
,
"buildinfo_pkg.vhd"
,
"buildinfo_pkg.vhd"
,
"sourceid_wr_spec_tdc_pkg.vhd"
,
]
]
modules
=
{
"local"
:
[
"../../top/spec"
,
"../../ip_cores/gn4124-core/hdl/sim/gn4124_bfm"
]
}
modules
=
{
"local"
:
[
"../../top/spec"
,
fetchto
+
"/gn4124-core/hdl/sim/gn4124_bfm"
],
"git"
:
[
"https://ohwr.org/project/wr-cores.git"
,
"https://ohwr.org/project/general-cores.git"
,
"https://ohwr.org/project/gn4124-core.git"
,
"https://ohwr.org/project/ddr3-sp6-core.git"
,
],
"system"
:
[
'xilinx'
]
}
ctrls
=
[
"bank3_32b_32b"
]
ctrls
=
[
"bank3_32b_32b"
]
...
@@ -34,4 +52,13 @@ ctrls = ["bank3_32b_32b"]
...
@@ -34,4 +52,13 @@ ctrls = ["bank3_32b_32b"]
try
:
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
except
:
pass
pass
\ No newline at end of file
try
:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_sourceid.py"
)
.
read
(),
None
,
{
'project'
:
'wr_spec_tdc'
})
except
Exception
as
e
:
print
(
"Error: cannot generate source id file"
)
raise
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