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FMC TDC 1ns 5cha - Gateware
Commit caaf87ad authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top/spec: removed non-WR top level

parent c2a10e64
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hdl/top/spec/Manifest.py deleted 100644 → 0
View file @ c2a10e64
files = ["fmc_tdc_wrapper.vhd",
"tdc_core_pkg.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd"
];
modules = {"local" : [ "../../platform/xilinx" ] }
hdl/top/spec/no_wrabbit/spec_reset_gen.vhd deleted 100644 → 0
View file @ c2a10e64
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/no_wrabbit/spec_tdc.ucf deleted 100644 → 0
View file @ c2a10e64
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "tdc_clk_125m_p_i" LOC = "L20";
NET "tdc_clk_125m_p_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_p_i" TNM_NET = "tdc_clk_125m_p_i";
TIMESPEC TStdc_clk_125m_p_i = PERIOD "tdc_clk_125m_p_i" 8 ns HIGH 50%;
NET "tdc_clk_125m_n_i" LOC = "L22";
NET "tdc_clk_125m_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_n_i" TNM_NET = "tdc_clk_125m_n_i";
TIMESPEC TS_tdc_clk_125m_n_i = PERIOD "tdc_clk_125m_n_i" 8 ns HIGH 50%;
NET "p2l_clk_n_i" LOC = M19;
NET "p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" LOC = M20;
NET "p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" TNM_NET = "p2l_clk_p_i";
TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
NET "p2l_clk_n_i" TNM_NET = "p2l_clk_n_i";
TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
#----------------------------------------
# FMC slot
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "acam_refclk_p_i" LOC = "E16";
NET "acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "acam_refclk_n_i" LOC = "F16";
NET "acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_led_trig1_o" LOC = "W18";
NET "tdc_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig2_o" LOC = "B20";
NET "tdc_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig3_o" LOC = "A20";
NET "tdc_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "term_en_1_o" LOC = "Y11";
NET "term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "term_en_2_o" LOC = "AB11";
NET "term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "ef1_i" LOC = "W12";
NET "ef1_i" IOSTANDARD = "LVCMOS25";
NET "ef2_i" LOC = "Y12";
NET "ef2_i" IOSTANDARD = "LVCMOS25";
NET "term_en_3_o" LOC = "R11";
NET "term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "term_en_4_o" LOC = "T11";
NET "term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "term_en_5_o" LOC = "R13";
NET "term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_status_o" LOC = "T14";
NET "tdc_led_status_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig4_o" LOC = "D17";
NET "tdc_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig5_o" LOC = "C18";
NET "tdc_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "pll_sclk_o" LOC = "AA16";
NET "pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "pll_dac_sync_o" LOC = "AB16";
NET "pll_dac_sync_o" IOSTANDARD = "LVCMOS25";
NET "pll_cs_o" LOC = "Y17";
NET "pll_cs_o" IOSTANDARD = "LVCMOS25";
NET "cs_n_o" LOC = "AB17";
NET "cs_n_o" IOSTANDARD = "LVCMOS25";
NET "err_flag_i" LOC = "V11";
NET "err_flag_i" IOSTANDARD = "LVCMOS25";
NET "int_flag_i" LOC = "W11";
NET "int_flag_i" IOSTANDARD = "LVCMOS25";
NET "start_dis_o" LOC = "T15";
NET "start_dis_o" IOSTANDARD = "LVCMOS25";
NET "stop_dis_o" LOC = "U15";
NET "stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "pll_sdo_i" LOC = "AB18";
NET "pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "pll_status_i" LOC = "Y18";
NET "pll_status_i" IOSTANDARD = "LVCMOS25";
NET "pll_sdi_o" LOC = "AA18";
NET "pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "start_from_fpga_o" LOC = "W17";
NET "start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[27]" LOC = "AB4";
NET "data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[26]" LOC = "AA4";
NET "data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[25]" LOC = "AB9";
NET "data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[24]" LOC = "Y9";
NET "data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[23]" LOC = "Y10";
NET "data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[22]" LOC = "W10";
NET "data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[21]" LOC = "U10";
NET "data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[20]" LOC = "T10";
NET "data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[19]" LOC = "AB8";
NET "data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[18]" LOC = "AA8";
NET "data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[17]" LOC = "AB7";
NET "data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[16]" LOC = "Y7";
NET "data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[15]" LOC = "V9";
NET "data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[14]" LOC = "U9";
NET "data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[13]" LOC = "AB6";
NET "data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[12]" LOC = "AA6";
NET "data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[11]" LOC = "R8";
NET "data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[10]" LOC = "R9";
NET "data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[9]" LOC = "AB5";
NET "data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[8]" LOC = "Y5";
NET "data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[7]" LOC = "AB12";
NET "data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[6]" LOC = "U8";
NET "data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[5]" LOC = "AA12";
NET "data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[4]" LOC = "T8";
NET "data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[3]" LOC = "W8";
NET "data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[2]" LOC = "V7";
NET "data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[1]" LOC = "Y6";
NET "data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[0]" LOC = "W6";
NET "data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "address_o[3]" LOC = "AB15";
NET "address_o[3]" IOSTANDARD = "LVCMOS25";
NET "address_o[2]" LOC = "Y15";
NET "address_o[2]" IOSTANDARD = "LVCMOS25";
NET "address_o[1]" LOC = "U12";
NET "address_o[1]" IOSTANDARD = "LVCMOS25";
NET "address_o[0]" LOC = "T12";
NET "address_o[0]" IOSTANDARD = "LVCMOS25";
NET "oe_n_o" LOC = "V13";
NET "oe_n_o" IOSTANDARD = "LVCMOS25";
NET "rd_n_o" LOC = "AB13";
NET "rd_n_o" IOSTANDARD = "LVCMOS25";
NET "wr_n_o" LOC = "Y13";
NET "wr_n_o" IOSTANDARD = "LVCMOS25";
NET "enable_inputs_o" LOC = "C19";
NET "enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "mezz_onewire_b" LOC = "A19";
NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
NET "mezz_sys_scl_b" LOC = "F7";
NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
NET "mezz_sys_sda_b" LOC = "F8";
NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "rst_n_a_i" LOC = N20;
NET "rst_n_a_i" IOSTANDARD = "LVCMOS18";
NET "l2p_clk_n_o" LOC = K22;
NET "l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_clk_p_o" LOC = K21;
NET "l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_dframe_o" LOC = U22;
NET "l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "l2p_edb_o" LOC = U20;
NET "l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "l2p_rdy_i" LOC = U19;
NET "l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "l2p_valid_o" LOC = T18;
NET "l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[0]" LOC = R20;
NET "l_wr_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[1]" LOC = T22;
NET "l_wr_rdy_i[1]" IOSTANDARD = "SSTL18_I";
#NET "L_CLKN" LOC = N19;
#NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
#NET "L_CLKP" LOC = P20;
#NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_dframe_i" LOC = J22;
NET "p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "p2l_rdy_o" LOC = J16;
NET "p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "p2l_valid_i" LOC = L19;
NET "p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[0]" LOC = N16;
NET "p_rd_d_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[1]" LOC = P19;
NET "p_rd_d_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[0]" LOC = L15;
NET "p_wr_rdy_o[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[1]" LOC = K16;
NET "p_wr_rdy_o[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[0]" LOC = M22;
NET "p_wr_req_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[1]" LOC = M21;
NET "p_wr_req_i[1]" IOSTANDARD = "SSTL18_I";
NET "rx_error_o" LOC = J17;
NET "rx_error_o" IOSTANDARD = "SSTL18_I";
NET "tx_error_i" LOC = M17;
NET "tx_error_i" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[0]" LOC = B21;
NET "vc_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[1]" LOC = B22;
NET "vc_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[0]" LOC = P16;
NET "l2p_data_o[0]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[1]" LOC = P21;
NET "l2p_data_o[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[2]" LOC = P18;
NET "l2p_data_o[2]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[3]" LOC = T20;
NET "l2p_data_o[3]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[4]" LOC = V21;
NET "l2p_data_o[4]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[5]" LOC = V19;
NET "l2p_data_o[5]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[6]" LOC = W22;
NET "l2p_data_o[6]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[7]" LOC = Y22;
NET "l2p_data_o[7]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[8]" LOC = P22;
NET "l2p_data_o[8]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[9]" LOC = R22;
NET "l2p_data_o[9]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[10]" LOC = T21;
NET "l2p_data_o[10]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[11]" LOC = T19;
NET "l2p_data_o[11]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[12]" LOC = V22;
NET "l2p_data_o[12]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[13]" LOC = V20;
NET "l2p_data_o[13]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[14]" LOC = W20;
NET "l2p_data_o[14]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[15]" LOC = Y21;
NET "l2p_data_o[15]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[0]" LOC = K20;
NET "p2l_data_i[0]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[1]" LOC = H22;
NET "p2l_data_i[1]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[2]" LOC = H21;
NET "p2l_data_i[2]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[3]" LOC = L17;
NET "p2l_data_i[3]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[4]" LOC = K17;
NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[5]" LOC = G22;
NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[7]" LOC = K18;
NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[8]" LOC = K19;
NET "p2l_data_i[8]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[9]" LOC = H20;
NET "p2l_data_i[9]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[10]" LOC = J19;
NET "p2l_data_i[10]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[11]" LOC = E22;
NET "p2l_data_i[11]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[12]" LOC = E20;
NET "p2l_data_i[12]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[13]" LOC = F22;
NET "p2l_data_i[13]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[14]" LOC = F21;
NET "p2l_data_i[14]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[15]" LOC = H19;
NET "p2l_data_i[15]" IOSTANDARD = "SSTL18_I";
NET "irq_p_o" LOC = U16;
NET "irq_p_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
#----------------------------------------
NET "prsnt_m2c_n_i" LOC = AB14;
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier LEDs and Buttons
#----------------------------------------
#NET "spec_aux0_i" LOC = C22;
#NET "spec_aux0_i" IOSTANDARD = "LVCMOS18";
#NET "spec_aux1_i" LOC = D21;
#NET "spec_aux1_i" IOSTANDARD = "LVCMOS18";
#NET "spec_aux2_o" LOC = G19;
#NET "spec_aux2_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux3_o" LOC = F20;
#NET "spec_aux3_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux4_o" LOC = F18;
#NET "spec_aux4_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux5_o" LOC = C20;
#NET "spec_aux5_o" IOSTANDARD = "LVCMOS18";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "rst_n_a_i" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
hdl/top/spec/no_wrabbit/spec_tdc.vhd deleted 100644 → 0
View file @ c2a10e64
--_________________________________________________________________________________________________
-- |
-- |SPEC TDC| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_tdc |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_tdc.vhd |
-- |
-- Description TDC top level for a SPEC carrier, without White Rabbit support. |
-- Figure 1 shows the architecture of the unit. |
-- |
-- For the communication with the PCIe, the ohwr.org GN4124 core is instantiated. |
-- |
-- The TDC mezzanine core is instantiated for the communication with the TDC board. |
-- The VIC core is forwarding the interrupts coming from the TDC mezzanine core to |
-- the GN4124 core. |
-- The carrier_info module provides general information on the SPEC PCB version, PLLs|
-- locking state etc. |
-- The 1-Wire core provides communication with the SPEC Thermometer&UniqueID chip. |
-- All the cores communicate with the GN4124 core through the SDB crossbar. The SDB |
-- crossbar is responsible for managing the access to the GN4124 core. |
-- |
-- The speed of all the cores (TDC mezzanine, VIC, carrier csr, 1-Wire, SDB as well |
-- as the GN4124 core) is 125 MHz. |
-- |
-- The 125 MHz clock comes from the PLL located on the TDC mezzanine board. |
-- The clks_rsts_manager unit is responsible for automatically configuring the PLL |
-- upon the FPGA startup or after a PCIe reset, using the 20 MHz VCXO on the SPEC |
-- carrier board. The clks_rsts_manager is keeping all the rest of the logic under |
-- reset until the mezzanine PLL gets locked. |
-- |
-- __________________________________________________________________ |
-- ________ | ___ _____ | |
-- | | | ___________________ | | | | | |
-- | PLL |<->| | clks rsts manager | | | | | | |
-- | DAC | | |___________________| | | | | | |
-- | | | ____________________________ | | | | | |
-- | | | | | \ | | | | | |
-- | ACAM |<->| | TDC mezzanine | \ | | | | | |
-- |________| | |--|____________________________| \ | | | G | | |
-- TDC mezz | | \ | | | | | |
-- | | ____________________________ | S | | N | | |
-- | |->| | | | | | | |
-- | | Vector Interrupt Controller| ---- | D | <--> | 4 | | |
-- | |____________________________| | | | | | |
-- | | B | | 1 | | |
-- | ____________________________ | | | | | |
-- | | | | | | 2 | | |
-- SPEC 1Wire <->| | 1-Wire | ---- | | | | | |
-- | |____________________________| | | | 4 | | |
-- | / | | | | | |
-- | ____________________________ / | | | | | |
-- | | | / | | | | | |
-- | | carrier_info | / | | | | | |
-- | |____________________________| | | | | | |
-- | |___| |_____| | |
-- | | |
-- | ______________________________________________ | |
-- SPEC LEDs <->| |___________________LEDs_______________________| | |
-- | | |
-- |__________________________________________________________________| |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2014 |
-- Version v6 (see sdb_meta_pkg) |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v1 GP First version |
-- 06/2012 v2 EG Revamping; Comments added, signals renamed |
-- removed LEDs from top level |
-- new GN4124 core integrated |
-- carrier 1 wire master added |
-- mezzanine I2C master added |
-- mezzanine 1 wire master added |
-- interrupts generator added |
-- changed generation of rst_125m |
-- DAC reconfiguration+needed regs added |
-- 06/2012 v3 EG Changes for v2 of TDC mezzanine |
-- Several pinout changes, |
-- acam_ref_clk LVDS instead of CMOS, |
-- no PLL_LD only PLL_STATUS |
-- 04/2013 v4 EG added SDB; fixed bugs in data_formatting; added carrier CSR information |
-- 01/2014 v5 EG added VIC and EIC in the TDC mezzanine |
-- 06/2014 v6 EG added possibility for White Rabbit support |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_xilinx_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;
--=================================================================================================
-- Entity declaration for spec_tdc
--=================================================================================================
entity spec_tdc is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- this generic is set to TRUE
-- when instantiated in a test-bench
port
(-- SPEC carrier
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
carrier_scl_b : inout std_logic; -- SPEC EEPROM
carrier_sda_b : inout std_logic;
carrier_onewire_b : inout std_logic; -- SPEC 1-wire
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
-- Interface with GN4124
rst_n_a_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
-- Timing interface with the ACAM on TDC mezzanine
start_from_fpga_o : out std_logic; -- start signal
err_flag_i : in std_logic; -- error flag
int_flag_i : in std_logic; -- interrupt flag
start_dis_o : out std_logic; -- start disable, not used
stop_dis_o : out std_logic; -- stop disable, not used
-- Data interface with the ACAM on TDC mezzanine
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic; -- chip select for ACAM
oe_n_o : out std_logic; -- output enable for ACAM
rd_n_o : out std_logic; -- read signal for ACAM
wr_n_o : out std_logic; -- write signal for ACAM
ef1_i : in std_logic; -- empty flag iFIFO1
ef2_i : in std_logic; -- empty flag iFIFO2
-- Enable of input Logic on TDC mezzanine
enable_inputs_o : out std_logic; -- enables all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
-- 1-wire interface on TDC mezzanine
mezz_onewire_b : inout std_logic;
-- font panel leds (not used)
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
end spec_tdc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_tdc is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- Carrier onewire interface
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 2; -- Interrupt controller
constant c_WB_SLAVE_TDC : integer := 3; -- TDC core configuration
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00000000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
3 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
4 => f_sdb_embed_repo_url (c_sdb_repo_url),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) := (0 => x"00052000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- SPEC VCXO clock
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
-- TDC core clock and reset
signal clk_125m, pll_status : std_logic;
signal rst_125m_n, rst_125m : std_logic;
signal acam_refclk_r_edge_p : std_logic;
-- DAC configuration through PCIe/VME
signal send_dac_word_p : std_logic;
signal dac_word : std_logic_vector(23 downto 0);
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Carrier CSR info
signal gn4124_status : std_logic_vector(31 downto 0);
-- Carrier 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- VIC
signal fmc_eic_irq, irq_to_gn4124 : std_logic;
signal fmc_eic_irq_synch : std_logic_vector (1 downto 0);
-- EEPROM on mezzanine
signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in: std_logic;
signal tdc_scl_oen, tdc_sda_oen : std_logic;
-- aux
signal pll_sclk, pll_sdi, pll_dac_sync, pll_cs,led_red : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- 125 MHz clk and Reset for TDC core --
---------------------------------------------------------------------------------------------------
spec_clk_ibuf : IBUFG
port map
(I => clk_20m_vcxo_i,
O => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tdc_clks_rsts_mgment : clks_rsts_manager
generic map
(nb_of_reg => 68)
port map
(clk_sys_i => clk_20m_vcxo_buf,
acam_refclk_p_i => acam_refclk_p_i,
acam_refclk_n_i => acam_refclk_n_i,
tdc_125m_clk_p_i => tdc_clk_125m_p_i,
tdc_125m_clk_n_i => tdc_clk_125m_n_i,
rst_n_i => rst_n_a_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
send_dac_word_p_i => send_dac_word_p,
dac_word_i => dac_word,
acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
wrabbit_dac_value_i => (others => '0'), -- not used
wrabbit_dac_wr_p_i => '0', -- not used
internal_rst_o => rst_125m,
pll_cs_n_o => pll_cs,
pll_dac_sync_n_o => pll_dac_sync,
pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk,
tdc_125m_clk_o => clk_125m,
pll_status_o => pll_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_n <= not rst_125m;
pll_dac_sync_o <= pll_dac_sync;
pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk;
pll_cs_o <= pll_cs;
led_green_o <= pll_status;
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- 0x00000 -> SDB
-- 0x10000 -> Carrier 1-wire master
-- 0x20000 -> Carrier CSR information
-- 0x30000 -> Vector Interrupt Controller
-- 0x40000 -> TDC mezzanine SDB
-- 0x10000 -> TDC core configuration (including ACAM regs)
-- 0x11000 -> TDC Mezzanine 1-wire master
-- 0x12000 -> TDC Mezzanine Embedded Interrupt Controller
-- 0x13000 -> TDC Mezzanine I2C master
-- 0x14000 -> TDC core timestamps retrieval from memory
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_125m,
rst_n_i => rst_n_a_i,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
cmp_gn4124_core: gn4124_core
port map
(rst_n_a_i => rst_n_a_i,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
-- P2L Control
p2l_rdy_o => p2l_rdy_o,
p_wr_req_i => p_wr_req_i,
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => l2p_clk_p_o,
l2p_clk_n_o => l2p_clk_n_o,
l2p_data_o => l2p_data_o ,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
l2p_edb_o => l2p_edb_o,
-- L2P Control
l2p_rdy_i => l2p_rdy_i,
l_wr_rdy_i => l_wr_rdy_i,
p_rd_d_rdy_i => p_rd_d_rdy_i,
tx_error_i => tx_error_i,
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
dma_irq_o => open,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_p_o,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_125m,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
-- DMA: not used
dma_clk_i => clk_125m,
dma_adr_o => open,
dma_cyc_o => open,
dma_dat_o => open,
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_ack_i => '1',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_reg_clk_i => clk_125m,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
dma_reg_dat_o => open,
dma_reg_ack_o => open,
dma_reg_stall_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : fmc_tdc_mezzanine
generic map
(g_span => g_span,
g_width => g_width,
values_for_simul => FALSE)
port map
(-- 125M clk and reset
clk_ref_0_i => clk_125m,
rst_ref_0_i => rst_125m,
-- not used (only for White Rabbit stuff)
clk_sys_i => clk_125m,
rst_sys_n_i => rst_125m_n,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word,
-- ACAM interface
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
-- Input channels enable
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- Input channels to FPGA (not used)
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
-- WISHBONE interface with the GN4124 core
wb_tdc_csr_adr_i => cnx_master_out(c_WB_SLAVE_TDC).adr,
wb_tdc_csr_dat_i => cnx_master_out(c_WB_SLAVE_TDC).dat,
wb_tdc_csr_stb_i => cnx_master_out(c_WB_SLAVE_TDC).stb,
wb_tdc_csr_we_i => cnx_master_out(c_WB_SLAVE_TDC).we,
wb_tdc_csr_cyc_i => cnx_master_out(c_WB_SLAVE_TDC).cyc,
wb_tdc_csr_sel_i => cnx_master_out(c_WB_SLAVE_TDC).sel,
wb_tdc_csr_dat_o => cnx_master_in(c_WB_SLAVE_TDC).dat,
wb_tdc_csr_ack_o => cnx_master_in(c_WB_SLAVE_TDC).ack,
wb_tdc_csr_stall_o => cnx_master_in(c_WB_SLAVE_TDC).stall,
-- White Rabbit (not used)
wrabbit_link_up_i => '0',
wrabbit_time_valid_i => '0',
wrabbit_cycles_i => (others => '0'),
wrabbit_utc_i => (others => '0'),
wrabbit_clk_aux_lock_en_o => open,
wrabbit_clk_aux_locked_i => '0',
wrabbit_clk_dmtd_locked_i => '1',
wrabbit_dac_value_i => (others => '0'),
wrabbit_dac_wr_p_i => '0',
-- Interrupt line from EIC
wb_irq_o => fmc_eic_irq,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => tdc_scl_in,
i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => tdc_sda_in,
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
onewire_b => mezz_onewire_b);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for TDC mezzanine EEPROM
mezz_sys_scl_b <= tdc_scl_out when (tdc_scl_oen = '0') else 'Z';
mezz_sys_sda_b <= tdc_sda_out when (tdc_sda_oen = '0') else 'Z';
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TDC).err <= '0';
cnx_master_in(c_WB_SLAVE_TDC).rty <= '0';
cnx_master_in(c_WB_SLAVE_TDC).int <= '0';
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_125m,
rst_n_i => rst_125m_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_eic_irq,
irq_master_o => irq_to_gn4124);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_drive_SPEC_red_led: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_125m,
rst_n_i => rst_125m_n,
pulse_i => irq_to_gn4124,
extended_o => led_red);
-- -- -- -- -- -- --
led_red_o <= led_red;
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
---------------------------------------------------------------------------------------------------
cmp_carrier_onewire : xwb_onewire_master
generic map
(g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0")
port map
(clk_sys_i => clk_125m,
rst_n_i => rst_125m_n,
slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
desc_o => open,
owr_pwren_o => open,
owr_en_o => carrier_owr_en,
owr_i => carrier_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_onewire_b;
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_info : carrier_info
port map
(rst_n_i => rst_125m_n,
clk_sys_i => clk_125m,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).stall,
carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => pll_status,
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'),
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
carrier_info_ctrl_reserved_o => open,
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/top/spec/no_wrabbit/synthesis_descriptor.vhd deleted 100644 → 0
View file @ c2a10e64
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec_tdc ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"20140617",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/fmc-tdc "
);
end package synthesis_descriptor;
hdl/top/spec/no_wrabbit/tdc_core_pkg.vhd deleted 100644 → 0
View file @ c2a10e64
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- tdc_core_pkg |
-- |
---------------------------------------------------------------------------------------------------
-- File tdc_core_pkg.vhd |
-- |
-- Description Package containing core wide constants and components |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2011 v0.1 GP First version |
-- 04/2012 v0.2 EG Revamping; Gathering of all the constants, declarations of all the |
-- units; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wishbone_pkg.all;
use work.genram_pkg.all;
--=================================================================================================
-- Package declaration for tdc_core_pkg
--=================================================================================================
package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-- Constant regarding the Mezzanine DAC configuration --
---------------------------------------------------------------------------------------------------
-- Vout = Vref (DAC_WORD/ 65536); for Vout = 1.65V, with Vref = 2.5V the DAC_WORD = xA8F5
constant c_DEFAULT_DAC_WORD : std_logic_vector(23 downto 0) := x"00A8F5";
---------------------------------------------------------------------------------------------------
-- Constants regarding the SDB Devices Definitions --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Devices sdb description
constant c_ONEWIRE_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"0000000000000007",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000602", -- "WB-Onewire.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-Onewire.Control ")));
constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPEC.CSR ")));
constant c_TDC_EIC_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000605", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-FMC-TDC.EIC ")));
constant c_I2C_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000606", -- "WB-I2C.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-I2C.Control ")));
constant c_TDC_EIC_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-TDC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-FMC-TDC.EIC ")));
constant c_TDC_CONFIG_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604", -- "WB-TDC-Core-Config " | md5sum | cut -c1-8
version => x"00000001",
date => x"20130429",
name => "WB-TDC-Core-Config ")));
constant c_TDC_MEM_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601", -- "WB-TDC-Mem " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-TDC-Mem ")));
---------------------------------------------------------------------------------------------------
-- Constants regarding 1 Hz pulse generation --
---------------------------------------------------------------------------------------------------
-- for synthesis: 1 sec = x"07735940" clk_i cycles (1 clk_i cycle = 8ns)
constant c_SYN_CLK_PERIOD : std_logic_vector(31 downto 0) := x"07735940";
-- for simulation: 1 msec = x"0001E848" clk_i cycles (1 clk_i cycle = 8ns)
constant c_SIM_CLK_PERIOD : std_logic_vector(31 downto 0) := x"0001E848";
---------------------------------------------------------------------------------------------------
-- Vector with the 11 ACAM Configuration Registers --
---------------------------------------------------------------------------------------------------
subtype config_register is std_logic_vector(31 downto 0);
type config_vector is array (10 downto 0) of config_register;
---------------------------------------------------------------------------------------------------
-- Constants regarding addressing of the ACAM registers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM configuration registers to be written by the PCIe host
-- corresponds to:
constant c_ACAM_REG0_ADR : std_logic_vector(7 downto 0) := x"00"; -- address 0x51000 of GN4124 BAR 0
constant c_ACAM_REG1_ADR : std_logic_vector(7 downto 0) := x"01"; -- address 0x51004 of GN4124 BAR 0
constant c_ACAM_REG2_ADR : std_logic_vector(7 downto 0) := x"02"; -- address 0x51008 of GN4124 BAR 0
constant c_ACAM_REG3_ADR : std_logic_vector(7 downto 0) := x"03"; -- address 0x5100C of GN4124 BAR 0
constant c_ACAM_REG4_ADR : std_logic_vector(7 downto 0) := x"04"; -- address 0x51010 of GN4124 BAR 0
constant c_ACAM_REG5_ADR : std_logic_vector(7 downto 0) := x"05"; -- address 0x51014 of GN4124 BAR 0
constant c_ACAM_REG6_ADR : std_logic_vector(7 downto 0) := x"06"; -- address 0x51018 of GN4124 BAR 0
constant c_ACAM_REG7_ADR : std_logic_vector(7 downto 0) := x"07"; -- address 0x5101C of GN4124 BAR 0
constant c_ACAM_REG11_ADR : std_logic_vector(7 downto 0) := x"0B"; -- address 0x5102C of GN4124 BAR 0
constant c_ACAM_REG12_ADR : std_logic_vector(7 downto 0) := x"0C"; -- address 0x51030 of GN4124 BAR 0
constant c_ACAM_REG14_ADR : std_logic_vector(7 downto 0) := x"0E"; -- address 0x51038 of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM read-only registers, to be written by the ACAM and used within the core to access ACAM timestamps
constant c_ACAM_REG8_ADR : std_logic_vector(7 downto 0) := x"08"; -- not accessible for writing from PCI-e
constant c_ACAM_REG9_ADR : std_logic_vector(7 downto 0) := x"09"; -- not accessible for writing from PCI-e
constant c_ACAM_REG10_ADR : std_logic_vector(7 downto 0) := x"0A"; -- not accessible for writing from PCI-e
---------------------------------------------------------------------------------------------------
-- Addresses of ACAM configuration readback registers, to be written by the ACAM
-- corresponds to:
constant c_ACAM_REG0_RDBK_ADR : std_logic_vector(7 downto 0) := x"10"; -- address 0x51040 of the GN4124 BAR 0
constant c_ACAM_REG1_RDBK_ADR : std_logic_vector(7 downto 0) := x"11"; -- address 0x51044 of the GN4124 BAR 0
constant c_ACAM_REG2_RDBK_ADR : std_logic_vector(7 downto 0) := x"12"; -- address 0x51048 of the GN4124 BAR 0
constant c_ACAM_REG3_RDBK_ADR : std_logic_vector(7 downto 0) := x"13"; -- address 0x5104C of the GN4124 BAR 0
constant c_ACAM_REG4_RDBK_ADR : std_logic_vector(7 downto 0) := x"14"; -- address 0x51050 of the GN4124 BAR 0
constant c_ACAM_REG5_RDBK_ADR : std_logic_vector(7 downto 0) := x"15"; -- address 0x51054 of the GN4124 BAR 0
constant c_ACAM_REG6_RDBK_ADR : std_logic_vector(7 downto 0) := x"16"; -- address 0x51058 of the GN4124 BAR 0
constant c_ACAM_REG7_RDBK_ADR : std_logic_vector(7 downto 0) := x"17"; -- address 0x5105C of the GN4124 BAR 0
constant c_ACAM_REG8_RDBK_ADR : std_logic_vector(7 downto 0) := x"18"; -- address 0x51060 of the GN4124 BAR 0
constant c_ACAM_REG9_RDBK_ADR : std_logic_vector(7 downto 0) := x"19"; -- address 0x51064 of the GN4124 BAR 0
constant c_ACAM_REG10_RDBK_ADR : std_logic_vector(7 downto 0) := x"1A"; -- address 0x51068 of the GN4124 BAR 0
constant c_ACAM_REG11_RDBK_ADR : std_logic_vector(7 downto 0) := x"1B"; -- address 0x5106C of the GN4124 BAR 0
constant c_ACAM_REG12_RDBK_ADR : std_logic_vector(7 downto 0) := x"1C"; -- address 0x51070 of the GN4124 BAR 0
constant c_ACAM_REG14_RDBK_ADR : std_logic_vector(7 downto 0) := x"1E"; -- address 0x51078 of the GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Constants regarding addressing of the TDC core registers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Configuration registers to be written by the PCIe host
-- corresponds to:
constant c_STARTING_UTC_ADR : std_logic_vector(7 downto 0) := x"20"; -- address 0x51080 of GN4124 BAR 0
constant c_ACAM_INPUTS_EN_ADR : std_logic_vector(7 downto 0) := x"21"; -- address 0x51084 of GN4124 BAR 0
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 0x51098 of GN4124 BAR 0
constant c_DEACT_CHAN_ADR : std_logic_vector(7 downto 0) := x"27"; -- address 0x5109C of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of TDC core Status registers to be written by the different core units
-- corresponds to:
constant c_LOCAL_UTC_ADR : std_logic_vector(7 downto 0) := x"28"; -- address 0x510A0 of GN4124 BAR 0
constant c_IRQ_CODE_ADR : std_logic_vector(7 downto 0) := x"29"; -- address 0x510A4 of GN4124 BAR 0
constant c_WR_INDEX_ADR : std_logic_vector(7 downto 0) := x"2A"; -- address 0x510A8 of GN4124 BAR 0
constant c_CORE_STATUS_ADR : std_logic_vector(7 downto 0) := x"2B"; -- address 0x510AC of GN4124 BAR 0
constant c_WRABBIT_STATUS_ADR : std_logic_vector(7 downto 0) := x"2C"; -- address 0x510B0 of GN4124 BAR 0
constant c_WRABBIT_CTRL_ADR : std_logic_vector(7 downto 0) := x"2D"; -- address 0x510B4 of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Address of TDC core Control register
-- corresponds to:
constant c_CTRL_REG_ADR : std_logic_vector(7 downto 0) := x"3F"; -- address 0x510FC of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Constants regarding ACAM retriggers --
---------------------------------------------------------------------------------------------------
-- Number of clk_i cycles corresponding to the Acam retrigger period;
-- through Acam Reg 4 StartTimer the chip is programmed to retrigger every:
-- (15+1) * acam_ref_clk = (15+1) * 32 ns
-- x"00000040" * clk_i = 64 * 8 ns
-- 512 ns
constant c_ACAM_RETRIG_PERIOD : std_logic_vector(31 downto 0) := x"00000040";
-- Used to multiply by 64, which is the retrigger period in clk_i cycles
constant c_ACAM_RETRIG_PERIOD_SHIFT : integer := 6;
---------------------------------------------------------------------------------------------------
-- Constants regarding TDC & SPEC LEDs --
---------------------------------------------------------------------------------------------------
constant c_SPEC_LED_PERIOD_SIM : std_logic_vector(31 downto 0) := x"00004E20"; -- 1 ms at 20 MHz
constant c_SPEC_LED_PERIOD_SYN : std_logic_vector(31 downto 0) := x"01312D00"; -- 1 s at 20 MHz
constant c_BLINK_LGTH_SYN : std_logic_vector(31 downto 0) := x"00BEBC20"; -- 100 ms at 125 MHz
constant c_BLINK_LGTH_SIM : std_logic_vector(31 downto 0) := x"000004E2"; -- 10 us at 125 MHz
--c_RESET_WORD
---------------------------------------------------------------------------------------------------
-- Constants regarding the Circular Buffer --
---------------------------------------------------------------------------------------------------
constant c_CIRCULAR_BUFF_SIZE : unsigned(31 downto 0) := x"00000100";
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
constant c_FMC_ONEWIRE_NB : integer := 1;
---------------------------------------------------------------------------------------------------
-- Constants regarding the Carrier CSR info --
---------------------------------------------------------------------------------------------------
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
---------------------------------------------------------------------------------------------------
-- Components Declarations --
---------------------------------------------------------------------------------------------------
component fmc_tdc_mezzanine is
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
-- Signals from the clks_rsts_manager unit
clk_ref_0_i : in std_logic;
rst_ref_0_i : in std_logic;
-- TDC core
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
start_from_fpga_o : out std_logic;
err_flag_i : in std_logic;
int_flag_i : in std_logic;
start_dis_o : out std_logic;
stop_dis_o : out std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
oe_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
ef1_i : in std_logic;
ef2_i : in std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
enable_inputs_o : out std_logic;
term_en_1_o : out std_logic;
term_en_2_o : out std_logic;
term_en_3_o : out std_logic;
term_en_4_o : out std_logic;
term_en_5_o : out std_logic;
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- White Rabbit core
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic;
wrabbit_cycles_i : in std_logic_vector(27 downto 0);
wrabbit_utc_i : in std_logic_vector(31 downto 0);
wrabbit_clk_aux_lock_en_o : out std_logic;
wrabbit_clk_aux_locked_i : in std_logic;
wrabbit_clk_dmtd_locked_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | core interrupts | 1Wire | I2C
wb_tdc_csr_adr_i : in std_logic_vector(31 downto 0);
wb_tdc_csr_dat_i : in std_logic_vector(31 downto 0);
wb_tdc_csr_cyc_i : in std_logic;
wb_tdc_csr_sel_i : in std_logic_vector(3 downto 0);
wb_tdc_csr_stb_i : in std_logic;
wb_tdc_csr_we_i : in std_logic;
wb_tdc_csr_dat_o : out std_logic_vector(31 downto 0);
wb_tdc_csr_ack_o : out std_logic;
wb_tdc_csr_stall_o : out std_logic;
wb_irq_o : out std_logic;
-- I2C EEPROM interface
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
-- 1-wire UniqueID&Thermometer interface
onewire_b : inout std_logic);
end component;
---------------------------------------------------------------------------------------------------
component fmc_tdc_core
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_125m_i : in std_logic;
rst_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
start_from_fpga_o : out std_logic;
err_flag_i : in std_logic;
int_flag_i : in std_logic;
start_dis_o : out std_logic;
stop_dis_o : out std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
oe_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
ef1_i : in std_logic;
ef2_i : in std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
enable_inputs_o : out std_logic;
term_en_1_o : out std_logic;
term_en_2_o : out std_logic;
term_en_3_o : out std_logic;
term_en_4_o : out std_logic;
term_en_5_o : out std_logic;
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_synched_i : in std_logic;
wrabbit_tai_p_i : in std_logic;
wrabbit_tai_i : in std_logic_vector(31 downto 0);
irq_tstamp_p_o : out std_logic;
irq_time_p_o : out std_logic;
irq_acam_err_p_o : out std_logic;
tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0);
tdc_config_wb_dat_i : in std_logic_vector(g_width-1 downto 0);
tdc_config_wb_stb_i : in std_logic;
tdc_config_wb_we_i : in std_logic;
tdc_config_wb_cyc_i : in std_logic;
tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
tdc_config_wb_ack_o : out std_logic;
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0);
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0);
tdc_mem_wb_stb_i : in std_logic;
tdc_mem_wb_we_i : in std_logic;
tdc_mem_wb_cyc_i : in std_logic;
tdc_mem_wb_ack_o : out std_logic;
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
tdc_mem_wb_stall_o : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component wrabbit_sync is
generic
(g_simulation : boolean;
g_with_wrabbit_core : boolean);
port
(clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_ref_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic; -- this is i te clk_ref_0 domain, no??
wrabbit_clk_aux_lock_en_o : out std_logic;
wrabbit_clk_aux_locked_i : in std_logic;
wrabbit_clk_dmtd_locked_i : in std_logic;
wrabbit_synched_o : out std_logic;
wrabbit_reg_i : in std_logic_vector(31 downto 0);
wrabbit_reg_o : out std_logic_vector(31 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component spec_reset_gen is
port
(clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component decr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
-------------------------------------------------------------
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component free_counter is
generic
(width : integer := 32);
port
(clk_i : in std_logic;
counter_en_i : in std_logic;
rst_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
-------------------------------------------------------------
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component incr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
counter_incr_en_i : in std_logic;
rst_i : in std_logic;
-------------------------------------------------------------
counter_is_full_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component start_retrig_ctrl
generic
(g_width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
acam_intflag_f_edge_p_i : in std_logic;
utc_p_i : in std_logic;
----------------------------------------------------------------------
current_retrig_nb_o : out std_logic_vector(g_width-1 downto 0);
roll_over_incr_recent_o : out std_logic;
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component local_pps_gen
generic
(g_width : integer := 32);
port
(acam_refclk_r_edge_p_i : in std_logic;
clk_i : in std_logic;
clk_period_i : in std_logic_vector(g_width-1 downto 0);
load_utc_p_i : in std_logic;
pulse_delay_i : in std_logic_vector(g_width-1 downto 0);
rst_i : in std_logic;
starting_utc_i : in std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------
local_utc_o : out std_logic_vector(g_width-1 downto 0);
local_utc_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component data_engine
port
(acam_ack_i : in std_logic;
acam_dat_i : in std_logic_vector(31 downto 0);
clk_i : in std_logic;
rst_i : in std_logic;
acam_ef1_i : in std_logic;
acam_ef1_meta_i : in std_logic;
acam_ef2_i : in std_logic;
acam_ef2_meta_i : in std_logic;
activate_acq_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
acam_wr_config_p_i : in std_logic;
acam_rdbk_config_p_i : in std_logic;
acam_rdbk_status_p_i : in std_logic;
acam_rdbk_ififo1_p_i : in std_logic;
acam_rdbk_ififo2_p_i : in std_logic;
acam_rdbk_start01_p_i : in std_logic;
acam_rst_p_i : in std_logic;
acam_config_i : in config_vector;
start_from_fpga_i : in std_logic;
----------------------------------------------------------------------
state_active_p_o : out std_logic;
acam_adr_o : out std_logic_vector(7 downto 0);
acam_cyc_o : out std_logic;
acam_dat_o : out std_logic_vector(31 downto 0);
acam_stb_o : out std_logic;
acam_we_o : out std_logic;
acam_config_rdbk_o : out config_vector;
acam_ififo1_o : out std_logic_vector(31 downto 0);
acam_ififo2_o : out std_logic_vector(31 downto 0);
acam_start01_o : out std_logic_vector(31 downto 0);
acam_tstamp1_o : out std_logic_vector(31 downto 0);
acam_tstamp1_ok_p_o : out std_logic;
acam_tstamp2_o : out std_logic_vector(31 downto 0);
acam_tstamp2_ok_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component reg_ctrl
generic
(g_span : integer := 32;
g_width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0);
tdc_config_wb_cyc_i : in std_logic;
tdc_config_wb_dat_i : in std_logic_vector(g_width-1 downto 0);
tdc_config_wb_stb_i : in std_logic;
tdc_config_wb_we_i : in std_logic;
acam_config_rdbk_i : in config_vector;
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
wr_index_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------
tdc_config_wb_ack_o : out std_logic;
tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
activate_acq_p_o : out std_logic;
deactivate_acq_p_o : out std_logic;
deactivate_chan_o : out std_logic_vector(4 downto 0);
acam_wr_config_p_o : out std_logic;
acam_rdbk_config_p_o : out std_logic;
acam_rdbk_status_p_o : out std_logic;
acam_rdbk_ififo1_p_o : out std_logic;
acam_rdbk_ififo2_p_o : out std_logic;
acam_rdbk_start01_p_o : out std_logic;
acam_rst_p_o : out std_logic;
load_utc_p_o : out std_logic;
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0);
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0);
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
dacapo_c_rst_p_o : out std_logic;
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component acam_timecontrol_interface
port
(err_flag_i : in std_logic;
int_flag_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
utc_p_i : in std_logic;
clk_i : in std_logic;
activate_acq_p_i : in std_logic;
rst_i : in std_logic;
state_active_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
----------------------------------------------------------------------
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic;
acam_errflag_r_edge_p_o : out std_logic;
acam_errflag_f_edge_p_o : out std_logic;
acam_intflag_f_edge_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component data_formatting
port
(tstamp_wr_wb_ack_i : in std_logic;
tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
acam_tstamp1_i : in std_logic_vector(31 downto 0);
acam_tstamp1_ok_p_i : in std_logic;
acam_tstamp2_i : in std_logic_vector(31 downto 0);
acam_tstamp2_ok_p_i : in std_logic;
clk_i : in std_logic;
dacapo_c_rst_p_i : in std_logic;
deactivate_chan_i : in std_logic_vector(4 downto 0);
rst_i : in std_logic;
roll_over_incr_recent_i : in std_logic;
clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
roll_over_nb_i : in std_logic_vector(31 downto 0);
utc_i : in std_logic_vector(31 downto 0);
retrig_nb_offset_i : in std_logic_vector(31 downto 0);
utc_p_i : in std_logic;
----------------------------------------------------------------------
tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
tstamp_wr_wb_cyc_o : out std_logic;
tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
tstamp_wr_wb_stb_o : out std_logic;
tstamp_wr_wb_we_o : out std_logic;
tstamp_wr_p_o : out std_logic;
acam_channel_o : out std_logic_vector(2 downto 0);
wr_index_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component irq_generator is
generic
(g_width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0);
irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0);
activate_acq_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
tstamp_wr_p_i : in std_logic;
acam_errflag_r_edge_p_i : in std_logic;
----------------------------------------------------------------------
irq_tstamp_p_o : out std_logic;
irq_acam_err_p_o : out std_logic;
irq_time_p_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component tdc_eic
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_tdc_tstamps_i : in std_logic;
irq_tdc_time_i : in std_logic;
irq_tdc_acam_err_i : in std_logic);
end component tdc_eic;
---------------------------------------------------------------------------------------------------
component dma_eic
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_dma_done_i : in std_logic;
irq_dma_error_i : in std_logic);
end component dma_eic;
---------------------------------------------------------------------------------------------------
component irq_controller
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
----------------------------------------------------------------------
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
irq_p_o : out std_logic);
end component irq_controller;
---------------------------------------------------------------------------------------------------
component clks_rsts_manager
generic
(nb_of_reg : integer := 68);
port
(clk_sys_i : in std_logic;
acam_refclk_p_i : in std_logic;
acam_refclk_n_i : in std_logic;
tdc_125m_clk_p_i : in std_logic;
tdc_125m_clk_n_i : in std_logic;
rst_n_i : in std_logic;
pll_status_i : in std_logic;
pll_sdo_i : in std_logic;
send_dac_word_p_i : in std_logic;
dac_word_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
----------------------------------------------------------------------
tdc_125m_clk_o : out std_logic;
internal_rst_o : out std_logic;
acam_refclk_r_edge_p_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_dac_sync_n_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
pll_status_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component carrier_info
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_info_stat_fmc_pres_i : in std_logic;
carrier_info_stat_p2l_pll_lck_i : in std_logic;
carrier_info_stat_sys_pll_lck_i : in std_logic;
carrier_info_stat_ddr3_cal_done_i : in std_logic;
carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
carrier_info_ctrl_led_green_o : out std_logic;
carrier_info_ctrl_led_red_o : out std_logic;
carrier_info_ctrl_dac_clr_n_o : out std_logic;
carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_info_rst_fmc0_n_o : out std_logic;
carrier_info_rst_fmc0_n_i : in std_logic;
carrier_info_rst_fmc0_n_load_o : out std_logic;
carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0));
end component carrier_info;
---------------------------------------------------------------------------------------------------
component leds_manager is
generic
(g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_i : in std_logic;
utc_p_i : in std_logic;
acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0);
acam_channel_i : in std_logic_vector(5 downto 0);
tstamp_wr_p_i : in std_logic;
----------------------------------------------------------------------
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic);
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component acam_databus_interface
port
(ef1_i : in std_logic;
ef2_i : in std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
clk_i : in std_logic;
rst_i : in std_logic;
adr_i : in std_logic_vector(7 downto 0);
cyc_i : in std_logic;
dat_i : in std_logic_vector(31 downto 0);
stb_i : in std_logic;
we_i : in std_logic;
----------------------------------------------------------------------
adr_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
oe_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
ack_o : out std_logic;
ef1_o : out std_logic;
ef1_meta_o : out std_logic;
ef2_o : out std_logic;
ef2_meta_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0));
----------------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component circular_buffer
port
(clk_i : in std_logic;
tstamp_wr_rst_i : in std_logic;
tstamp_wr_stb_i : in std_logic;
tstamp_wr_cyc_i : in std_logic;
tstamp_wr_we_i : in std_logic;
tstamp_wr_adr_i : in std_logic_vector(7 downto 0);
tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
tdc_mem_wb_rst_i : in std_logic;
tdc_mem_wb_stb_i : in std_logic;
tdc_mem_wb_cyc_i : in std_logic;
tdc_mem_wb_we_i : in std_logic;
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0);
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0);
--------------------------------------------------
tstamp_wr_ack_p_o : out std_logic;
tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
tdc_mem_wb_ack_o : out std_logic;
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
tdc_mem_wb_stall_o : out std_logic);
--------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component blk_mem_circ_buff_v6_4
port
(clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(127 downto 0);
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(9 downto 0);
dinb : in std_logic_vector(31 downto 0);
enb : in std_logic;
web : in std_logic_vector(0 downto 0);
--------------------------------------------------
douta : out std_logic_vector(127 downto 0);
doutb : out std_logic_vector(31 downto 0));
--------------------------------------------------
end component;
end tdc_core_pkg;
--=================================================================================================
-- package body
--=================================================================================================
package body tdc_core_pkg is
end tdc_core_pkg;
--=================================================================================================
-- package end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/top/spec/sdb_meta_pkg.vhd deleted 100644 → 0
View file @ c2a10e64
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- sdb_meta_pkg |
-- |
---------------------------------------------------------------------------------------------------
-- File sdb_meta_pkg.vhd |
-- |
-- Description Sdb meta-information for the FMC TDC design for SPEC. |
-- |
-- Authors Matthieu Cattin (matthieu.cattin@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2013 |
-- Version v1 |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_SDB_REPO_URL : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "http://svn.ohwr.org/fmc-tdc/hdl/spec/ ");
-- Synthesis informations
constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_tdc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => x"00000000",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000134",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20140121",
-- Synthesised by (string, 15 char)
syn_username => "egousiou ");
-- Integration record
constant c_SDB_INTEGRATION : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"593b56e5", -- echo "spec_fmc-tdc-1ns5cha" | md5sum | cut -c1-8
version => x"00050000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140121", -- yyyymmdd
name => "spec_top_fmc_tdc "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
\ No newline at end of file
hdl/top/spec/spec_top_fmc_tdc.ucf deleted 100644 → 0
View file @ c2a10e64
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "tdc_clk_125m_p_i" LOC = "L20";
NET "tdc_clk_125m_p_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_p_i" TNM_NET = "tdc_clk_125m_p_i";
TIMESPEC TStdc_clk_125m_p_i = PERIOD "tdc_clk_125m_p_i" 8 ns HIGH 50%;
NET "tdc_clk_125m_n_i" LOC = "L22";
NET "tdc_clk_125m_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_n_i" TNM_NET = "tdc_clk_125m_n_i";
TIMESPEC TS_tdc_clk_125m_n_i = PERIOD "tdc_clk_125m_n_i" 8 ns HIGH 50%;
NET "p2l_clk_n_i" LOC = M19;
NET "p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" LOC = M20;
NET "p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" TNM_NET = "p2l_clk_p_i";
TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
NET "p2l_clk_n_i" TNM_NET = "p2l_clk_n_i";
TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
#----------------------------------------
# FMC slot
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "acam_refclk_p_i" LOC = "E16";
NET "acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "acam_refclk_n_i" LOC = "F16";
NET "acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_led_trig1_o" LOC = "W18";
NET "tdc_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig2_o" LOC = "B20";
NET "tdc_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig3_o" LOC = "A20";
NET "tdc_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "term_en_1_o" LOC = "Y11";
NET "term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "term_en_2_o" LOC = "AB11";
NET "term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "ef1_i" LOC = "W12";
NET "ef1_i" IOSTANDARD = "LVCMOS25";
NET "ef2_i" LOC = "Y12";
NET "ef2_i" IOSTANDARD = "LVCMOS25";
NET "term_en_3_o" LOC = "R11";
NET "term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "term_en_4_o" LOC = "T11";
NET "term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "term_en_5_o" LOC = "R13";
NET "term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_status_o" LOC = "T14";
NET "tdc_led_status_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig4_o" LOC = "D17";
NET "tdc_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "tdc_led_trig5_o" LOC = "C18";
NET "tdc_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "pll_sclk_o" LOC = "AA16";
NET "pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "pll_dac_sync_o" LOC = "AB16";
NET "pll_dac_sync_o" IOSTANDARD = "LVCMOS25";
NET "pll_cs_o" LOC = "Y17";
NET "pll_cs_o" IOSTANDARD = "LVCMOS25";
NET "cs_n_o" LOC = "AB17";
NET "cs_n_o" IOSTANDARD = "LVCMOS25";
NET "err_flag_i" LOC = "V11";
NET "err_flag_i" IOSTANDARD = "LVCMOS25";
NET "int_flag_i" LOC = "W11";
NET "int_flag_i" IOSTANDARD = "LVCMOS25";
NET "start_dis_o" LOC = "T15";
NET "start_dis_o" IOSTANDARD = "LVCMOS25";
NET "stop_dis_o" LOC = "U15";
NET "stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "pll_sdo_i" LOC = "AB18";
NET "pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "pll_status_i" LOC = "Y18";
NET "pll_status_i" IOSTANDARD = "LVCMOS25";
NET "pll_sdi_o" LOC = "AA18";
NET "pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "start_from_fpga_o" LOC = "W17";
NET "start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[27]" LOC = "AB4";
NET "data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[26]" LOC = "AA4";
NET "data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[25]" LOC = "AB9";
NET "data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[24]" LOC = "Y9";
NET "data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[23]" LOC = "Y10";
NET "data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[22]" LOC = "W10";
NET "data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[21]" LOC = "U10";
NET "data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[20]" LOC = "T10";
NET "data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[19]" LOC = "AB8";
NET "data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[18]" LOC = "AA8";
NET "data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[17]" LOC = "AB7";
NET "data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[16]" LOC = "Y7";
NET "data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[15]" LOC = "V9";
NET "data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[14]" LOC = "U9";
NET "data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[13]" LOC = "AB6";
NET "data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[12]" LOC = "AA6";
NET "data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[11]" LOC = "R8";
NET "data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[10]" LOC = "R9";
NET "data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[9]" LOC = "AB5";
NET "data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[8]" LOC = "Y5";
NET "data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[7]" LOC = "AB12";
NET "data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[6]" LOC = "U8";
NET "data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[5]" LOC = "AA12";
NET "data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[4]" LOC = "T8";
NET "data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[3]" LOC = "W8";
NET "data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[2]" LOC = "V7";
NET "data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[1]" LOC = "Y6";
NET "data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "data_bus_io[0]" LOC = "W6";
NET "data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "address_o[3]" LOC = "AB15";
NET "address_o[3]" IOSTANDARD = "LVCMOS25";
NET "address_o[2]" LOC = "Y15";
NET "address_o[2]" IOSTANDARD = "LVCMOS25";
NET "address_o[1]" LOC = "U12";
NET "address_o[1]" IOSTANDARD = "LVCMOS25";
NET "address_o[0]" LOC = "T12";
NET "address_o[0]" IOSTANDARD = "LVCMOS25";
NET "oe_n_o" LOC = "V13";
NET "oe_n_o" IOSTANDARD = "LVCMOS25";
NET "rd_n_o" LOC = "AB13";
NET "rd_n_o" IOSTANDARD = "LVCMOS25";
NET "wr_n_o" LOC = "Y13";
NET "wr_n_o" IOSTANDARD = "LVCMOS25";
NET "enable_inputs_o" LOC = "C19";
NET "enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "mezz_one_wire_b" LOC = "A19";
NET "mezz_one_wire_b" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
NET "mezz_sys_scl_b" LOC = "F7";
NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
NET "mezz_sys_sda_b" LOC = "F8";
NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "rst_n_a_i" LOC = N20;
NET "rst_n_a_i" IOSTANDARD = "LVCMOS18";
NET "l2p_clk_n_o" LOC = K22;
NET "l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_clk_p_o" LOC = K21;
NET "l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_dframe_o" LOC = U22;
NET "l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "l2p_edb_o" LOC = U20;
NET "l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "l2p_rdy_i" LOC = U19;
NET "l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "l2p_valid_o" LOC = T18;
NET "l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[0]" LOC = R20;
NET "l_wr_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[1]" LOC = T22;
NET "l_wr_rdy_i[1]" IOSTANDARD = "SSTL18_I";
#NET "L_CLKN" LOC = N19;
#NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
#NET "L_CLKP" LOC = P20;
#NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_dframe_i" LOC = J22;
NET "p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "p2l_rdy_o" LOC = J16;
NET "p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "p2l_valid_i" LOC = L19;
NET "p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[0]" LOC = N16;
NET "p_rd_d_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[1]" LOC = P19;
NET "p_rd_d_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[0]" LOC = L15;
NET "p_wr_rdy_o[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[1]" LOC = K16;
NET "p_wr_rdy_o[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[0]" LOC = M22;
NET "p_wr_req_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[1]" LOC = M21;
NET "p_wr_req_i[1]" IOSTANDARD = "SSTL18_I";
NET "rx_error_o" LOC = J17;
NET "rx_error_o" IOSTANDARD = "SSTL18_I";
NET "tx_error_i" LOC = M17;
NET "tx_error_i" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[0]" LOC = B21;
NET "vc_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[1]" LOC = B22;
NET "vc_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[0]" LOC = P16;
NET "l2p_data_o[0]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[1]" LOC = P21;
NET "l2p_data_o[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[2]" LOC = P18;
NET "l2p_data_o[2]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[3]" LOC = T20;
NET "l2p_data_o[3]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[4]" LOC = V21;
NET "l2p_data_o[4]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[5]" LOC = V19;
NET "l2p_data_o[5]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[6]" LOC = W22;
NET "l2p_data_o[6]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[7]" LOC = Y22;
NET "l2p_data_o[7]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[8]" LOC = P22;
NET "l2p_data_o[8]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[9]" LOC = R22;
NET "l2p_data_o[9]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[10]" LOC = T21;
NET "l2p_data_o[10]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[11]" LOC = T19;
NET "l2p_data_o[11]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[12]" LOC = V22;
NET "l2p_data_o[12]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[13]" LOC = V20;
NET "l2p_data_o[13]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[14]" LOC = W20;
NET "l2p_data_o[14]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[15]" LOC = Y21;
NET "l2p_data_o[15]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[0]" LOC = K20;
NET "p2l_data_i[0]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[1]" LOC = H22;
NET "p2l_data_i[1]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[2]" LOC = H21;
NET "p2l_data_i[2]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[3]" LOC = L17;
NET "p2l_data_i[3]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[4]" LOC = K17;
NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[5]" LOC = G22;
NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[7]" LOC = K18;
NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[8]" LOC = K19;
NET "p2l_data_i[8]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[9]" LOC = H20;
NET "p2l_data_i[9]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[10]" LOC = J19;
NET "p2l_data_i[10]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[11]" LOC = E22;
NET "p2l_data_i[11]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[12]" LOC = E20;
NET "p2l_data_i[12]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[13]" LOC = F22;
NET "p2l_data_i[13]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[14]" LOC = F21;
NET "p2l_data_i[14]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[15]" LOC = H19;
NET "p2l_data_i[15]" IOSTANDARD = "SSTL18_I";
NET "irq_p_o" LOC = U16;
NET "irq_p_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
#----------------------------------------
NET "prsnt_m2c_n_i" LOC = AB14;
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# TDC IN FPGA (not used)
#----------------------------------------
NET "tdc_in_fpga_1_i" LOC = V17;
NET "tdc_in_fpga_1_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier Generic Stuff
#----------------------------------------
NET "led_red" LOC = D5;
NET "led_red" IOSTANDARD = "LVCMOS25";
NET "led_green" LOC = E5;
NET "led_green" IOSTANDARD = "LVCMOS25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "button1_i" LOC = C22;
NET "button1_i" IOSTANDARD = "LVCMOS18";
NET "button2_i" LOC = D21;
NET "button2_i" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# SFP
#----------------------------------------
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_b" LOC = G15;
NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_b" LOC = H14;
NET "sfp_rate_select_b" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = A17;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "rst_n_a_i" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clk_62m5_sys" TNM_NET = clk_62m5_sys;
TIMESPEC ts_ignore_crossclock = FROM "clk_62m5_sys" TO "tdc_clk_125m_p_i" 10ns DATAPATHONLY;
TIMESPEC ts_ignore_crossclock2 = FROM "tdc_clk_125m_p_i" TO "clk_62m5_sys" 10ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "clk_125m_pllref_n_i" 10ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "clk_62m5_sys" 10ns DATAPATHONLY;
TIMESPEC ts_x3 = FROM "clk_62m5_sys" TO "U_GTP_ch1_rx_divclk" 10ns DATAPATHONLY;
TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_62m5_sys" 10ns DATAPATHONLY;
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 125 MHz HIGH 50%;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
TIMESPEC TS_RXTS = FROM "rx_ts_trig" TO "FFS" 2 ns DATAPATHONLY;
hdl/top/spec/spec_top_fmc_tdc.vhd deleted 100644 → 0
View file @ c2a10e64
--_________________________________________________________________________________________________
-- |
-- |SPEC TDC| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_top_fmc_tdc |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_top_fmc_tdc.vhd |
-- |
-- Description TDC top level for a SPEC carrier. Figure 1 shows the architecture of the unit. |
-- |
-- For the communication with the PCIe, the ohwr.org GN4124 core is instantiated. |
-- |
-- The TDC mezzanine core is instantiated for the communication with the TDC board. |
-- The VIC core is forwarding the interrupts coming from the TDC mezzanine core to |
-- the GN4124 core. |
-- The carrier_info module provides general information on the SPEC PCB version, PLLs |
-- locking state etc. |
-- The 1-Wire core provides communication with the SPEC Thermometer&UniqueID chip. |
-- All the cores communicate with the GN4124 core through the SDB crossbar. The SDB |
-- crossbar is responsible for managing the acess to the GN4124 core. |
-- |
-- The speed of all the cores (TDC mezzanine, VIC, carrier csr, 1-Wire as well as |
-- the GN4124 core) is 125MHz. |
-- |
-- The 125MHz clock comes from the PLL located on the TDC mezzanine board. |
-- The clks_rsts_manager unit is responsible for automatically configuring the PLL |
-- upon the FPGA startup or after a PCIe reset, using the 20MHz VCXO on the SPEC |
-- carrier board. The clks_rsts_manager is keeping all the rest of the logic under |
-- reset until the PLL gets locked. |
-- |
-- __________________________________________________________________ |
-- ________ | ___ _____ | |
-- | | | ___________________ | | | | | |
-- | PLL |<->| | clks rsts manager | | | | | | |
-- | DAC | | |___________________| | | | | | |
-- | | | ____________________________ | | | | | |
-- | | | | | \ | | | | | |
-- | ACAM |<->| | TDC mezzanine | \ | | | | | |
-- |________| | |--|____________________________| \ | | | G | | |
-- TDC mezz | | \ | | | | | |
-- | | ____________________________ | S | | N | | |
-- | |->| | | | | | | |
-- | | Vector Interrupt Controller| ---- | D | <--> | 4 | | |
-- | |____________________________| | | | | | |
-- | | B | | 1 | | |
-- | ____________________________ | | | | | |
-- | | | | | | 2 | | |
-- SPEC 1Wire <->| | 1-Wire | ---- | | | | | |
-- | |____________________________| | | | 4 | | |
-- | / | | | | | |
-- | ____________________________ / | | | | | |
-- | | | / | | | | | |
-- | | carrier_info | / | | | | | |
-- | |____________________________| | | | | | |
-- | |___| |_____| | |
-- | | |
-- | ______________________________________________ | |
-- SPEC LEDs <->| |___________________LEDs_______________________| | |
-- | | |
-- |__________________________________________________________________| |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2014 |
-- Version v5 (see sdb_meta_pkg) |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v1 GP First version |
-- 06/2012 v2 EG Revamping; Comments added, signals renamed |
-- removed LEDs from top level |
-- new GN4124 core integrated |
-- carrier 1 wire master added |
-- mezzanine I2C master added |
-- mezzanine 1 wire master added |
-- interrupts generator added |
-- changed generation of rst_125m_mezz |
-- DAC reconfiguration+needed regs added |
-- 06/2012 v3 EG Changes for v2 of TDC mezzanine |
-- Several pinout changes, |
-- acam_ref_clk LVDS instead of CMOS, |
-- no PLL_LD only PLL_STATUS |
-- 04/2013 v4 EG added SDB; fixed bugs in data_formatting; added carrier CSR information |
-- 01/2014 v5 EG added VIC and EIC in the TDC mezzanine |
-- |
----------------------------------------------/!\-------------------------------------------------|
-- Note for eva: Remember the design is synthesised with Synplify Premier with DP (tdc_syn.prj) |
-- For PAR use the tdc_par_script.tcl commands in Xilinx ISE! |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
--use work.sdb_meta_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_xilinx_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;
--=================================================================================================
-- Entity declaration for spec_top_fmc_tdc
--=================================================================================================
entity spec_top_fmc_tdc is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- this generic is set to TRUE
-- when instantiated in a test-bench
port
(-- SPEC carrier
clk_125m_pllref_p_i: in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i: in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
dac_din_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
sfp_txp_o : out std_logic; -- SFP
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : in std_logic; -- SFP detect pin
sfp_mod_def1_b : inout std_logic; -- SFP scl
sfp_mod_def2_b : inout std_logic; -- SFP sda
sfp_rate_select_b : inout std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
uart_rxd_i : in std_logic := '1'; -- UART
uart_txd_o : out std_logic;
carrier_scl_b : inout std_logic; -- SPEC EEPROM
carrier_sda_b : inout std_logic;
carrier_onewire_b : inout std_logic; -- SPEC 1-wire
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
-- Interface with GN4124
rst_n_a_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
-- Timing interface with the ACAM on TDC mezzanine
start_from_fpga_o : out std_logic; -- start signal
err_flag_i : in std_logic; -- error flag
int_flag_i : in std_logic; -- interrupt flag
start_dis_o : out std_logic; -- start disable, not used
stop_dis_o : out std_logic; -- stop disable, not used
-- Data interface with the ACAM on TDC mezzanine
data_bus_io : inout std_logic_vector(27 downto 0);
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic; -- chip select for ACAM
oe_n_o : out std_logic; -- output enable for ACAM
rd_n_o : out std_logic; -- read signal for ACAM
wr_n_o : out std_logic; -- write signal for ACAM
ef1_i : in std_logic; -- empty flag iFIFO1
ef2_i : in std_logic; -- empty flag iFIFO2
-- Enable of input Logic on TDC mezzanine
enable_inputs_o : out std_logic; -- enables all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
-- 1-wire interface on TDC mezzanine
mezz_one_wire_b : inout std_logic;
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
end spec_top_fmc_tdc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_top_fmc_tdc is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 5;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- Carrier onewire interface
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 2; -- Interrupt controller
constant c_WB_SLAVE_TDC : integer := 3; -- TDC core configuration
constant c_SLAVE_WRCORE : integer := 4; -- White Rabbit PTP core
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00000000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
3 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
5 => f_sdb_embed_repo_url (c_sdb_repo_url),
6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00052000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- WRabbit clocks
signal pllout_clk_sys, pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref, pllout_clk_fb_dmtd : std_logic;
signal clk_125m_pllref, clk_125m_gtp : std_logic;
signal clk_dmtd : std_logic;
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
-- TDC core clocks and resets
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
signal clk_62m5_sys, clk_125m_mezz : std_logic;
signal rst_125m_mezz_n, rst_125m_mezz : std_logic;
signal acam_refclk_r_edge_p : std_logic;
signal rst_sys, rst_sys_n : std_logic;
-- DAC configuration through PCIe/VME
signal send_dac_word_p : std_logic;
signal dac_word : std_logic_vector(23 downto 0);
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal tdc_slave_in : t_wishbone_slave_in;
signal tdc_slave_out : t_wishbone_slave_out;
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Carrier CSR info
signal gn4124_status : std_logic_vector(31 downto 0);
-- Carrier 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- VIC
signal fmc_eic_irq, irq_to_gn4124 : std_logic;
signal fmc_eic_irq_synch : std_logic_vector (1 downto 0);
-- WRabbit time
signal tm_link_up, tm_time_valid, tm_dac_wr_p : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_dac_value, tm_dac_value_reg : std_logic_vector(23 downto 0);
signal tm_clk_aux_lock_en, tm_clk_aux_locked : std_logic;
-- WRabbit PHY
signal phy_tx_data, phy_rx_data : std_logic_vector(7 downto 0);
signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
signal phy_tx_enc_err, phy_rx_rbclk : std_logic;
signal phy_rx_enc_err, phy_rst, phy_loopen : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
-- DAC configuration through WRabbit
signal dac_hpll_load_p1, dac_dpll_load_p1 : std_logic;
signal dac_hpll_data, dac_dpll_data : std_logic_vector(15 downto 0);
-- EEPROM on mezzanine
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in: std_logic;
signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in: std_logic;
signal tdc_scl_oen, tdc_sda_oen : std_logic;
-- SFP EEPROM on mezzanine
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in: std_logic;
-- Carrier 1-Wire
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
-- aux
signal pll_sclk, pll_sdi, pll_dac_sync : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- 62.5 MHz system clock --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_vcxo_ibuf : IBUFG
port map
(O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_clk_vcxo_gbuf : BUFG
port map
(O => clk_20m_vcxo,
I => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_pll : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_20m_vcxo);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
port map
(O => clk_62m5_sys,
I => pllout_clk_sys);
---------------------------------------------------------------------------------------------------
-- Reset for 62M5 clk domain --
---------------------------------------------------------------------------------------------------
U_Reset_Generator : spec_reset_gen
port map
(clk_sys_i => clk_62m5_sys,
rst_pcie_n_a_i => rst_n_a_i,
rst_button_n_a_i => button1_i,
rst_n_o => rst_sys_n);
-- -- -- -- -- -- -- -- -- --
rst_sys <= not rst_sys_n;
---------------------------------------------------------------------------------------------------
-- 125 MHz clk and Reset for TDC core --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tdc_clks_rsts_mgment : clks_rsts_manager
generic map
(nb_of_reg => 68)
port map
(clk_sys_i => clk_62m5_sys,
acam_refclk_p_i => acam_refclk_p_i,
acam_refclk_n_i => acam_refclk_n_i,
tdc_125m_clk_p_i => tdc_clk_125m_p_i,
tdc_125m_clk_n_i => tdc_clk_125m_n_i,
rst_n_i => rst_n_a_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
send_dac_word_p_i => send_dac_word_p,
dac_word_i => dac_word,
acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
wrabbit_dac_value_i => tm_dac_value,
wrabbit_dac_wr_p_i => tm_dac_wr_p,
internal_rst_o => rst_125m_mezz,
pll_cs_n_o => pll_cs_o,
pll_dac_sync_n_o => pll_dac_sync,
pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk,
tdc_125m_clk_o => clk_125m_mezz,
pll_status_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_mezz_n <= not rst_125m_mezz;
pll_dac_sync_o <= pll_dac_sync;
pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk;
---------------------------------------------------------------------------------------------------
-- 62.5 MHz DMTD clock --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_dmtd_clk_pll : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_dmtd_buf : BUFG
port map
(O => clk_dmtd,
I => pllout_clk_dmtd);
---------------------------------------------------------------------------------------------------
-- 125 MHz clk for White Rabbit core --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_PLL : IBUFGDS
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => true) -- Low power (TRUE) vs. performance (FALSE) setting for referenced
port map
(O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i); -- Diff_n buffer input (connect directly to top-level port)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_GTP : IBUFDS
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => false)
port map
(O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i);
---------------------------------------------------------------------------------------------------
-- White Rabbit Core + PHY --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
generic map
(g_simulation => 0,
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram",
g_dpram_size => 90112/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false)
port map
(clk_sys_i => clk_62m5_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => clk_125m_mezz,
rst_n_i => rst_sys_n,
-- DAC
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
-- PHY
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
-- SPEC LEDs
led_act_o => LED_RED,
led_link_o => LED_GREEN,
-- SFP
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- 1-wire
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
-- WISHBONE
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
-- Timimg info for TDC core
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr_p,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles,
-- not used
btn1_i => '1',
btn2_i => '1',
pps_p_o => open,
-- aux reset
rst_aux_n_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_GTP : wr_gtp_phy_spartan6
generic map
(g_simulation => 0,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map
(gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => '0', -- phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_DAC_ARB : spec_serial_dac_arb
generic map
(g_invert_sclk => false,
g_num_extra_bits => 8)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_sys_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
-- -- -- -- -- --
sfp_tx_disable_o <= '0';
-- dac_clr_n_o <= '1';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for Carrier EEPROM
mezz_sys_scl_b <= '0' when (wrc_scl_out = '0') else 'Z';--tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
mezz_sys_sda_b <= '0' when (wrc_sda_out = '0') else 'Z';--tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
wrc_scl_in <= mezz_sys_scl_b;
wrc_sda_in <= mezz_sys_sda_b;
tdc_scl_in <= mezz_sys_scl_b;
tdc_sda_in <= mezz_sys_sda_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- 0x00000 -> SDB
-- 0x10000 -> Carrier 1-wire master
-- 0x20000 -> Carrier CSR information
-- 0x30000 -> Vector Interrupt Controller
-- 0x40000 -> TDC mezzanine SDB
-- 0x10000 -> TDC core configuration (including ACAM regs)
-- 0x11000 -> TDC Mezzanine 1-wire master
-- 0x12000 -> TDC Mezzanine Embedded Interrupt Controller
-- 0x13000 -> TDC Mezzanine I2C master
-- 0x14000 -> TDC core timestamps retrieval from memory
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_62m5_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
cmp_gn4124_core: gn4124_core
port map
(rst_n_a_i => rst_n_a_i,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
-- P2L Control
p2l_rdy_o => p2l_rdy_o,
p_wr_req_i => p_wr_req_i,
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => l2p_clk_p_o,
l2p_clk_n_o => l2p_clk_n_o,
l2p_data_o => l2p_data_o ,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
l2p_edb_o => l2p_edb_o,
-- L2P Control
l2p_rdy_i => l2p_rdy_i,
l_wr_rdy_i => l_wr_rdy_i,
p_rd_d_rdy_i => p_rd_d_rdy_i,
tx_error_i => tx_error_i,
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
dma_irq_o => open,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_p_o,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_62m5_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
-- DMA: not used
dma_clk_i => clk_62m5_sys,
dma_adr_o => open,
dma_cyc_o => open,
dma_dat_o => open,
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_ack_i => '1',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_reg_clk_i => clk_62m5_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
dma_reg_dat_o => open,
dma_reg_ack_o => open,
dma_reg_stall_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : fmc_tdc_mezzanine
generic map
(g_span => g_span,
g_width => g_width,
values_for_simul => FALSE)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_sys_n,
-- 125M clk and reset
clk_ref_0_i => clk_125m_mezz,
rst_ref_0_i => rst_125m_mezz,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word,
-- ACAM interface
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
-- Input channels enable
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- Input channels to FPGA (not used)
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
-- WISHBONE interface with the GN4124 core
wb_tdc_csr_adr_i => tdc_slave_in.adr,
wb_tdc_csr_dat_i => tdc_slave_in.dat,
wb_tdc_csr_stb_i => tdc_slave_in.stb,
wb_tdc_csr_we_i => tdc_slave_in.we,
wb_tdc_csr_cyc_i => tdc_slave_in.cyc,
wb_tdc_csr_sel_i => tdc_slave_in.sel,
wb_tdc_csr_dat_o => tdc_slave_out.dat,
wb_tdc_csr_ack_o => tdc_slave_out.ack,
wb_tdc_csr_stall_o => tdc_slave_out.stall,
-- White Rabbit
wrabbit_link_up_i => tm_link_up,
wrabbit_time_valid_i => tm_time_valid,
wrabbit_cycles_i => tm_cycles,
wrabbit_utc_i => tm_utc(31 downto 0),
wrabbit_utc_p_o => open, -- for debug
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i => tm_dac_value_reg,
wrabbit_dac_wr_p_i => tm_dac_wr_p,
-- Interrupt line from EIC
wb_irq_o => fmc_eic_irq,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => tdc_scl_in,
i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => tdc_sda_in,
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
one_wire_b => mezz_one_wire_b);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Domains crossing: clk_125m_mezz <-> clk_62m5_sys
cmp_tdc_clk_crossing : xwb_clock_crossing
port map
(slave_clk_i => clk_62m5_sys, -- Slave control port: GNUM interface at 62.5 MHz
slave_rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_TDC),
slave_o => cnx_master_in(c_WB_SLAVE_TDC),
master_clk_i => clk_125m_mezz, -- Master reader port: TDC core at 125 MHz
master_rst_n_i => rst_125m_mezz_n,
master_i => tdc_slave_out,
master_o => tdc_slave_in);
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_62m5_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_eic_irq_synch(1),
irq_master_o => irq_to_gn4124);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Domains crossing: synchronization of the wb_ird_o from 125MHz to 62.5MHz
irq_pulse_synchronizer: process (clk_62m5_sys)
begin
if rising_edge (clk_62m5_sys) then
if rst_sys_n = '0' then
fmc_eic_irq_synch <= (others => '0');
else
fmc_eic_irq_synch <= fmc_eic_irq_synch(0) & fmc_eic_irq;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
---------------------------------------------------------------------------------------------------
-- cmp_carrier_onewire : xwb_onewire_master
-- generic map
-- (g_interface_mode => CLASSIC,
-- g_address_granularity => BYTE,
-- g_num_ports => 1,
-- g_ow_btp_normal => "5.0",
-- g_ow_btp_overdrive => "1.0")
-- port map
-- (clk_sys_i => clk_62m5_sys,
-- rst_n_i => rst_sys_n,
-- slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
-- slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
-- desc_o => open,
-- owr_pwren_o => open,
-- owr_en_o => carrier_owr_en,
-- owr_i => carrier_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
-- carrier_owr_i(0) <= carrier_onewire_b;
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_info : carrier_info
port map
(rst_n_i => rst_sys_n,
clk_sys_i => clk_62m5_sys,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).stall,
carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => '0',
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'),
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
carrier_info_ctrl_reserved_o => open,
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/top/spec/synthesis_descriptor.vhd
View file @ caaf87ad
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
......@@ -42,11 +42,11 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "tdc-spec ",
syn_module_name => "wr_spec_tdc ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"00000000",
syn_date => x"20140617",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
......
hdl/top/spec/with_wrabbit/spec_reset_gen.vhd deleted 100644 → 0
View file @ c2a10e64
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/with_wrabbit/synthesis_descriptor.vhd deleted 100644 → 0
View file @ c2a10e64
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wr_spec_tdc ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"20140617",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/fmc-tdc "
);
end package synthesis_descriptor;
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