Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit caaf87ad authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

top/spec: removed non-WR top level

parent c2a10e64
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 4 additions and 3789 deletions
hdl/top/spec/Manifest.py deleted 100644 → 0
View file @ c2a10e64
files = ["fmc_tdc_wrapper.vhd",
"tdc_core_pkg.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd"
];
modules = {"local" : [ "../../platform/xilinx" ] }
hdl/top/spec/no_wrabbit/spec_reset_gen.vhd deleted 100644 → 0
View file @ c2a10e64
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/no_wrabbit/spec_tdc.ucf deleted 100644 → 0
View file @ c2a10e64
This diff is collapsed.
hdl/top/spec/no_wrabbit/spec_tdc.vhd deleted 100644 → 0
View file @ c2a10e64
This diff is collapsed.
hdl/top/spec/no_wrabbit/synthesis_descriptor.vhd deleted 100644 → 0
View file @ c2a10e64
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec_tdc ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"20140617",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/fmc-tdc "
);
end package synthesis_descriptor;
hdl/top/spec/no_wrabbit/tdc_core_pkg.vhd deleted 100644 → 0
View file @ c2a10e64
This diff is collapsed.
hdl/top/spec/sdb_meta_pkg.vhd deleted 100644 → 0
View file @ c2a10e64
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- sdb_meta_pkg |
-- |
---------------------------------------------------------------------------------------------------
-- File sdb_meta_pkg.vhd |
-- |
-- Description Sdb meta-information for the FMC TDC design for SPEC. |
-- |
-- Authors Matthieu Cattin (matthieu.cattin@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2013 |
-- Version v1 |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_SDB_REPO_URL : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "http://svn.ohwr.org/fmc-tdc/hdl/spec/ ");
-- Synthesis informations
constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_tdc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => x"00000000",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000134",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20140121",
-- Synthesised by (string, 15 char)
syn_username => "egousiou ");
-- Integration record
constant c_SDB_INTEGRATION : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"593b56e5", -- echo "spec_fmc-tdc-1ns5cha" | md5sum | cut -c1-8
version => x"00050000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140121", -- yyyymmdd
name => "spec_top_fmc_tdc "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
\ No newline at end of file
hdl/top/spec/spec_top_fmc_tdc.ucf deleted 100644 → 0
View file @ c2a10e64
This diff is collapsed.
hdl/top/spec/spec_top_fmc_tdc.vhd deleted 100644 → 0
View file @ c2a10e64
This diff is collapsed.
hdl/top/spec/synthesis_descriptor.vhd
View file @ caaf87ad
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
......@@ -42,11 +42,11 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "tdc-spec ",
syn_module_name => "wr_spec_tdc ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"00000000",
syn_date => x"20140617",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
......
hdl/top/spec/with_wrabbit/spec_reset_gen.vhd deleted 100644 → 0
View file @ c2a10e64
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/with_wrabbit/synthesis_descriptor.vhd deleted 100644 → 0
View file @ c2a10e64
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wr_spec_tdc ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"20140617",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/fmc-tdc "
);
end package synthesis_descriptor;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment