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FMC TDC 1ns 5cha - Gateware
Commit 9c3cd122 authored by egousiou's avatar egousiou
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cleanup 

git-svn-id: http://svn.ohwr.org/fmc-tdc@170 85dfdc96-de2c-444c-878d-45b388be74a9
parent 9990db8c
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hdl/wrabbit_tdc/hdl/rtl/circular_buffer.vhd
View file @ 9c3cd122
......@@ -129,7 +129,7 @@ entity circular_buffer is
tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- not used
-- Signals to the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pepelined acknowledge
tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pipelined acknowledge
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- 32 bit words
tdc_mem_wb_stall_o : out std_logic); -- timestamp reading WISHBONE pipelined stall
......
hdl/wrabbit_tdc/hdl/rtl/data_engine.vhd
View file @ 9c3cd122
......@@ -35,15 +35,15 @@
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Date 04/2014 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 06/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 14/2014 v1 EG added state RD_START01 |
-- 04/2014 v1 EG added state RD_START01 |
-- |
---------------------------------------------------------------------------------------------------
......@@ -680,12 +680,12 @@ begin
---------------------------------------------------------------------------------------------------
-- Aquisition of ACAM Timestamps or Reedback Registers --
-- Acquisition of ACAM Timestamps or Reedback Registers --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- data_readback_decoder: after reading accesses to the ACAM (acam_we=0), the process recuperates
-- the ACAM data and according to the acam_adr_o stores them to the corresponding registers.
-- In the case of timestamps aquisition, the acam_tstamp1_ok_p_o, acam_tstamp2_ok_p_o pulses are
-- In the case of timestamps acquisition, the acam_tstamp1_ok_p_o, acam_tstamp2_ok_p_o pulses are
-- generated that when active, indicate a valid timestamp. Note that for timing reasons
-- the signals acam_tstamp1_o, acam_tstamp2_o are not the outputs of flip-flops.
......
hdl/wrabbit_tdc/hdl/rtl/data_formatting.vhd
View file @ 9c3cd122
......@@ -16,26 +16,28 @@
-- Formats in a 128-bit word the |
-- o fine timestamps coming directly from the ACAM |
-- o plus the coarse timing internally measured in the core |
-- o plus the UTC time internally kept in the core |
-- o plus the UTC time, coming from the WRabbit core if synchronization is |
-- established or from the internal local counter |
-- and writes the word to the circular buffer |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2013 |
-- Version v2.1 |
-- Date 04/2014 |
-- Version v3 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2013 v1 EG Fixed bug when timestamop comes on the first retrigger after a new |
-- 04/2013 v1 EG Fixed bug when timestamp comes on the first retrigger after a new |
-- second; fixed bug on rollover that is a bit delayed wrt ACAM IrFlag |
-- 07/2013 v2 EG Cleaner writing with adition of intermediate DFF on the acam_tstamp |
-- 07/2013 v2 EG Cleaner writing with addition of intermediate DFF on the acam_tstamp |
-- calculations |
-- 09/2013 v2.1 EG added wr_index clearing upon dacapo_c_rst_p_i pulse; before only the |
-- dacapo_counter was being reset with the dacapo_c_rst_p_i |
-- 04/2014 v3 EG added logic for channels deactivation |
-- |
---------------------------------------------------------------------------------------------------
......@@ -101,7 +103,7 @@ entity data_formatting is
roll_over_nb_i : in std_logic_vector(31 downto 0);
retrig_nb_offset_i : in std_logic_vector(31 downto 0);
-- Signal from the one_hz_generator unit
-- Signal from the WRabbit core or the one_hz_generator unit
utc_p_i : in std_logic;
......@@ -152,15 +154,14 @@ architecture rtl of data_formatting is
-- coarse time calculations
signal tstamp_on_first_retrig_case1 : std_logic;
signal tstamp_on_first_retrig_case2 : std_logic;
signal coarse_zero : std_logic; -- for debug
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
signal un_previous_roll_over_nb : unsigned(31 downto 0);
signal un_current_retrig_nb_offset, un_current_roll_over_nb : unsigned(31 downto 0);
signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time :unsigned(31 downto 0);
signal un_acam_fine_time : unsigned(31 downto 0);
signal previous_utc : std_logic_vector(31 downto 0);
signal acam_timestamps : unsigned (23 downto 0);
signal coarse_zero : std_logic;
--=================================================================================================
......@@ -173,9 +174,10 @@ begin
---------------------------------------------------------------------------------------------------
-- WISHBONE_master_signals: Generation of the WISHBONE classic signals STB, CYC, WE that initiate
-- writes to the circular_buffer memory. Upon acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i activation
-- the process activates the STB, CYC, WE signals and waits for an ACK; as soon as the ACK arrives
-- (and the tstamps are written in the memory) STB, CYC and WE are deactivated and a new
-- acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i pulse is awaited to initiate a new write cycle.
-- and according to the value of the deactivate_chan_i register, the process activates the
-- STB, CYC, WE signals and waits for an ACK; as soon as the ACK arrives, the tstamps are
-- written in the memory and the STB, CYC and WE are deactivated; then a new acam_tstamp1_ok_p_i or
-- acam_tstamp2_ok_p_i pulse is awaited to initiate a new write cycle.
-- Reminder: timestamps (acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i pulses) can arrive at maximum
-- every 4 clk_i cycles (31.25 MHz).
......@@ -268,7 +270,7 @@ begin
tstamp_wr_p_o <= tstamp_wr_cyc and tstamp_wr_stb and tstamp_wr_we and tstamp_wr_wb_ack_i;
tstamp_wr_wb_adr_o <= std_logic_vector(wr_index);
wr_index_o <= std_logic_vector(dacapo_counter) & std_logic_vector(wr_index) & c_MULTIPLY_BY_SIXTEEN;
-- "& c_MULTIPLY_BY_SIXTEEN" for the convertion to the number of 8-bits-words
-- "& c_MULTIPLY_BY_SIXTEEN" for the conversion to the number of 8-bits-words
-- for the configuration of the DMA
---------------------------------------------------------------------------------------------------
......@@ -367,19 +369,6 @@ begin
end process;
dummy: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' then
acam_timestamps <= (others => '0');
elsif acam_tstamp1_ok_p_i = '1' or acam_tstamp2_ok_p_i = '1' then
acam_timestamps <= acam_timestamps+1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- all the values needed for the calculations have to be converted to unsigned
un_acam_fine_time <= unsigned(fine_time);
......@@ -479,10 +468,11 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- metadata: information about the timestamp
metadata <= std_logic_vector(acam_start_nb(7 downto 0)) & -- std_logic_vector(un_previous_retrig_nb_offset(7 downto 0)) & -- for debugging (24 MSbits)
coarse_zero &--acam_fifo_ef & roll_over_incr_recent_i & "0" & -- for debugging (3 bits)
std_logic_vector(un_retrig_nb_offset(7 downto 0)) & std_logic_vector(roll_over_nb_i(2 downto 0)) & std_logic_vector(un_clk_i_cycles_offset(6 downto 0)) &
acam_slope & roll_over_incr_recent_i & acam_channel; -- 5 LSbits-----------
metadata <= std_logic_vector(acam_start_nb(7 downto 0)) & -- for debug
coarse_zero & std_logic_vector(un_retrig_nb_offset(7 downto 0)) & -- for debug
std_logic_vector(roll_over_nb_i(2 downto 0)) &
std_logic_vector(un_clk_i_cycles_offset(6 downto 0)) & -- for debug
acam_slope & roll_over_incr_recent_i & acam_channel; -- 5 LSbits used for slope and acam_channel
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
full_timestamp(31 downto 0) <= fine_time;
......@@ -495,13 +485,11 @@ begin
---------------------------------------------------------------------------------------------------
-- Outputs --
---------------------------------------------------------------------------------------------------
-- wr_pointer_o <= dacapo_flag & std_logic_vector(wr_index(g_width-6 downto 0)) & x"0";
tstamp_wr_wb_cyc_o <= tstamp_wr_cyc;
tstamp_wr_wb_stb_o <= tstamp_wr_stb;
tstamp_wr_wb_we_o <= tstamp_wr_we;
acam_channel_o <= acam_channel;
acam_channel_o <= acam_channel;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/wrabbit_tdc/hdl/rtl/fmc_tdc_core.vhd
View file @ 9c3cd122
This diff is collapsed.
hdl/wrabbit_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 9c3cd122
......@@ -14,9 +14,11 @@
-- |
-- Description The unit combines |
-- o the TDC core |
-- o the wrabbit_sync unit that is managing the White Rabbit synchronization and |
-- control signals |
-- o the I2C core for the communication with the TDC board EEPROM |
-- o the OneWire core for the communication with the TDC board UniqueID&Thermeter |
-- o the Embedded Ibterrupt Controller core that concentrates several interrupt |
-- o the Embedded Interrupt Controller core that concentrates several interrupt |
-- sources into one WISHBONE interrupt request line. |
-- |
-- For the interconnection between the GN4124/VME core and the different cores (TDC, |
......@@ -32,25 +34,29 @@
-- Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte|
-- addressing |
-- _______________________________ |
-- | FMC TDC mezzanine | |
-- | ________________ ___ | |
-- | | | | | | |
-- ACAM chip <--> | | TDC core | | | | <--> |
-- | |________________| | S | | |
-- | ________________ | | | |
-- | | | | | | |
-- EEPROM chip <--> | | I2C core | | | | <--> |
-- | |________________| | | | |
-- | ________________ | D | | GN4124/VME core |
-- | | | | | | |
-- 1W chip <--> | | 1W core | | | | <--> |
-- | |________________| | | | |
-- | ________________ | | | |
-- | | | | B | | |
-- | | EIC | | | | <--> |
-- | |________________| |___| | |
-- | | |
-- |_______________________________| |
-- | FMC TDC mezzanine | |
-- | | |
-- | ________________ | |
-- | |--| WRabbit_sync | | |
-- | | |________________| | |
-- | | ________________ ___ | |
-- | |->| | | | | |
-- ACAM chip <--> | | TDC core | | | | <--> |
-- | |--|________________| | S | | |
-- | | ________________ | | | |
-- | | | | | | | |
-- EEPROM chip <--> | | | I2C core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | D | | GN4124/VME core |
-- | | | | | | | |
-- 1W chip <--> | | | 1W core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | | | |
-- | | | | | B | | |
-- | |->| EIC | | | | <--> |
-- | |________________| |___| | |
-- | | |
-- |________________________________| |
-- ^ ^ |
-- | 125 MHz rst | |
-- __|________________________|___ |
......@@ -111,12 +117,12 @@ entity fmc_tdc_mezzanine is
values_for_simul : boolean := FALSE);
port
-- TDC core
(-- Closk reset62.5
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
(-- Clock & reset 62M5
clk_sys_i : in std_logic; -- 62.5 MHz clock
rst_sys_n_i : in std_logic; -- reset for 62.5 MHz logic
-- Signals from the clks_rsts_manager unit
clk_ref_0_i : in std_logic;
rst_ref_0_i : in std_logic;
clk_ref_0_i : in std_logic; -- 125 MHz clock
rst_ref_0_i : in std_logic; -- reset for 125 MHz logic
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
......@@ -184,11 +190,7 @@ entity fmc_tdc_mezzanine is
i2c_sda_o : out std_logic;
i2c_sda_i : in std_logic;
-- 1-Wire interface
onewire_b : inout std_logic;
-- For debug: interrupt pulses from TDC core
irq_tstamp_p_o : out std_logic;
irq_time_p_o : out std_logic;
irq_acam_err_p_o : out std_logic);
onewire_b : inout std_logic);
end fmc_tdc_mezzanine;
......@@ -275,7 +277,7 @@ begin
-- 0x11000 -> TDC mezzanine board 1-Wire
-- 0x12000 -> EIC for TDC core
-- 0x13000 -> TDC mezzanine board EEPROM I2C
-- 0x14000 -> TDC core timestamps retreival
-- 0x14000 -> TDC core timestamps retrieval
-- Additional register to help timing
cmp_xwb_reg : xwb_register_link
......@@ -415,7 +417,6 @@ begin
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
---------------------------------------------------------------------------------------------------
cmp_wrabbit_synch: wrabbit_sync
generic map
(g_simulation => false,
......@@ -440,7 +441,7 @@ begin
wrabbit_one_hz_pulse : process(clk_ref_0_i)
begin
if rising_edge(clk_ref_0_i) then
if((wrabbit_clk_aux_locked_i = '1')) then --and g_with_wrabbit_core) then
if((wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core = '1') then
if unsigned(wrabbit_cycles_i) = unsigned(c_SYN_CLK_PERIOD) -1 then
wrabbit_utc_p <= '1';
else
......@@ -507,11 +508,6 @@ begin
cnx_master_in(c_WB_SLAVE_TDC_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_TDC_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_TDC_EIC).int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Only for debug
irq_tstamp_p_o <= irq_tstamp_p;
irq_time_p_o <= irq_time_p;
irq_acam_err_p_o <= irq_acam_err_p;
---------------------------------------------------------------------------------------------------
......@@ -539,10 +535,6 @@ begin
i2c_sda_o <= sys_sda_out;
i2c_scl_oen_o <= sys_scl_oe_n;
i2c_scl_o <= sys_scl_out;
-- i2c_sda_oen_o <= '0';
-- i2c_sda_o <= '0';
-- i2c_scl_oen_o <= '0';
-- i2c_scl_o <= '0';
end rtl;
......
hdl/wrabbit_tdc/hdl/rtl/irq_generator.vhd
View file @ 9c3cd122
......@@ -12,16 +12,16 @@
---------------------------------------------------------------------------------------------------
-- File irq_generator.vhd |
-- |
-- Description Interrupts generator: the unit generates three interrups: |
-- Description Interrupts generator: the unit generates three interrupts: |
-- |
-- o irq_tstamp_p_o is a 1-clk_i-long pulse generated when the amount of |
-- timestamps written in the circular_buffer, since the last interrupt or since |
-- the startup of the aquisition, exceeds the GN4124/VME settable threshold |
-- the startup of the acquisition, exceeds the GN4124/VME settable threshold |
-- irq_tstamp_threshold. |
-- |
-- o irq_time_p_o is a 1-clk_i-long pulse generated when some timestamps have been |
-- written in the circular_buffer (>=1 timestamp) and the amount of time passed |
-- since the last interrupt or since the aquisition startup, exceeds the |
-- since the last interrupt or since the acquisition startup, exceeds the |
-- GN4124/VME settable threshold irq_time_threshold. The threshold is in ms. |
-- |
-- o irq_acam_err_p_o is a 1-clk_i-long pulse generated when the ACAM Hit FIFOS are|
......@@ -91,8 +91,8 @@ entity irq_generator is
-- the ERRflag is configured to follow the full flags of the
-- Hit FIFOs; this would translate to data loss
-- Signal from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- activates tstamps aquisition from ACAM
deactivate_acq_p_i : in std_logic; -- deactivates tstamps aquisition
activate_acq_p_i : in std_logic; -- activates tstamps acquisition from ACAM
deactivate_acq_p_i : in std_logic; -- deactivates tstamps acquisition
-- Signals from the data_formatting unit
tstamp_wr_p_i : in std_logic; -- pulse upon storage of a new timestamp
......@@ -241,7 +241,7 @@ begin
-- last reset. The counter counts up to 255.
tstamps_counter: incr_counter
generic map
(width => 9)--(c_CIRCULAR_BUFF_SIZE'length)) -- 9 digits, counting up to 255
(width => 9) -- 9 digits, counting up to 255
port map
(clk_i => clk_i,
rst_i => tstamps_c_rst,
......
hdl/wrabbit_tdc/hdl/rtl/local_pps_gen.vhd
View file @ 9c3cd122
......@@ -15,6 +15,8 @@
-- Description Generates one pulse every second synchronously with the ACAM reference clock. |
-- The phase with the reference clock can be adjusted (eva: think that is not needed)|
-- It also keeps track of the UTC time based on the local clock. |
-- If there is no White Rabbit synchronization, this unit is the source of UTC timing|
-- in the design.
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
......
hdl/wrabbit_tdc/hdl/rtl/reg_ctrl.vhd
View file @ 9c3cd122
......@@ -18,9 +18,9 @@
-- |
-- Through WISHBONE writes, the unit receives: |
-- o the ACAM configuration registers which are then made available to the |
-- data_engine and acam_databus_interface units to be transfered to the ACAM chip|
-- o the local configuration registers (eg irq_thresholds, channels_enable) that |
-- are then made available to the different units of this design |
-- data_engine and acam_databus_interface units to be transferred to the ACAMchip|
-- o the local configuration registers (eg irq_thresholds, channels_enable, WRabbit|
-- core enable) that are then made available to the different units of the design|
-- o the control register that defines the action to be taken in the core; the |
-- register is decoded and the corresponding signals are made available to the |
-- different units in the design. |
......@@ -34,8 +34,8 @@
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 08/2012 |
-- Version v1 |
-- Date 04/2014 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
......@@ -43,6 +43,7 @@
-- 10/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 08/2012 v1 EG added register reg_adr_pipe0 for slack timing reasons |
-- 04/2014 v2 EG added WRabbit register; added channel deactivation register |
-- |
---------------------------------------------------------------------------------------------------
......@@ -86,7 +87,7 @@ entity reg_ctrl is
-- INPUTS
-- Signals from the clks_rsts_manager unit
(clk_i : in std_logic; -- 125 MHz
rst_i : in std_logic; -- global reset, synched to clk_i
rst_i : in std_logic; -- global reset, synced to clk_i
-- Signals from the GN4124/VME_core unit: WISHBONE for regs transfer
tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0); -- WISHBONE address
......@@ -112,7 +113,7 @@ entity reg_ctrl is
irq_code_i : in std_logic_vector(g_width-1 downto 0); -- TDC core interrupt code word
-- White Rabbit status
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); --
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); -- WRabbit status bits
-- OUTPUTS
......@@ -124,7 +125,7 @@ entity reg_ctrl is
acam_config_o : out config_vector;
-- Signals to the data_engine unit: TDC core functionality
activate_acq_p_o : out std_logic; -- activates tstamps aquisition from ACAM
activate_acq_p_o : out std_logic; -- activates tstamps acquisition from ACAM
deactivate_acq_p_o : out std_logic; -- activates ACAM configuration readings/ writings
acam_wr_config_p_o : out std_logic; -- enables writing to ACAM regs 0-7, 11, 12, 14
acam_rdbk_config_p_o : out std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
......@@ -136,8 +137,8 @@ entity reg_ctrl is
-- Signal to the data_formatting unit
dacapo_c_rst_p_o : out std_logic; -- clears the dacapo counter
deactivate_chan_o : out std_logic_vector(4 downto 0); -- stops registering timestamps from a specific channel
deactivate_chan_o : out std_logic_vector(4 downto 0); -- an active bit stops the registration of timestamps from the specified channel
-- eg: "10010": timestamps from Channel 2 and Channel 5 won't be registered
-- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
......@@ -153,7 +154,7 @@ entity reg_ctrl is
acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0); -- enables all five input channels
-- White Rabbit control
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); --
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); -- WRabbit control register; bit 0 enables the WRabbit core
-- Signal to the acam_timecontrol_interface unit -- eva: i think it s not needed
start_phase_o : out std_logic_vector(g_width-1 downto 0));
......@@ -184,7 +185,8 @@ architecture rtl of reg_ctrl is
--=================================================================================================
begin
reg_adr <= tdc_config_wb_adr_i(7 downto 0); -- we are interested in addresses 0:5000 to 0:50FC
reg_adr <= tdc_config_wb_adr_i(7 downto 0); -- we are interested in addresses 00 to FC
---------------------------------------------------------------------------------------------------
-- WISHBONE ACK to GN4124/VME_core --
......@@ -298,9 +300,11 @@ begin
-- o irq_tstamp_threshold : for the activation of GN4124/VME interrupts based on the number of timestamps
-- o irq_time_threshold : for the activation of GN4124/VME interrupts based on the time elapsed
-- o starting_utc : definition of the current UTC time
-- o starting_utc : definition of the current UTC time
-- o one_hz_phase : eva: think it s not used
-- o start_phase : eva: think it s not used
-- o dac_word : word for the "manual" (non White Rabbit) reconfiguration of the DAC
-- o deactivate_chan : for the deactivation of the registration of timestamps if they come from the specified channel
-- o wrabbit_ctrl_reg : for the activation of the White Rabbit core (bit 0 only used so far)
-- o one_hz_phase : not used
-- o start_phase : not used
TDCcore_config_reg_reception: process (clk_i)
begin
......@@ -310,11 +314,12 @@ begin
starting_utc <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
wrabbit_ctrl_reg <= (others =>'0');
deactivate_chan <= (others =>'0');
irq_tstamp_threshold <= x"00000100"; -- default 256 timestamps: full memory
irq_time_threshold <= x"000000C8"; -- default 200 ms
dac_word <= c_DEFAULT_DAC_WORD; -- default DAC Vout = 1.65
elsif tdc_config_wb_cyc_i = '1' and tdc_config_wb_stb_i = '1' and tdc_config_wb_we_i = '1' then -- WISHBONE writes
if reg_adr = c_STARTING_UTC_ADR then
......@@ -493,6 +498,7 @@ begin
-- White Rabbit regs
wrabbit_status_reg_i when c_WRABBIT_STATUS_ADR,
wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
-- Deactivation of timestamps registration
deactivate_chan when c_DEACT_CHAN_ADR,
-- others
x"C0FFEEEE" when others;
......
hdl/wrabbit_tdc/hdl/rtl/start_retrig_ctrl.vhd
View file @ 9c3cd122
......@@ -4,6 +4,7 @@
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- start_retrig_ctrl |
......@@ -90,14 +91,16 @@
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Date 04/2014 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2014 v1 EG Changed roll_over_counter to add rare case where utc_p_i and |
-- acam_intflag_f_edge_p_i arrive at the same time |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -152,6 +155,7 @@ entity start_retrig_ctrl is
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
end start_retrig_ctrl;
--=================================================================================================
-- architecture declaration
--=================================================================================================
......@@ -166,6 +170,7 @@ architecture rtl of start_retrig_ctrl is
signal retrig_p : std_logic;
signal roll_over_c : unsigned(g_width-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -256,22 +261,14 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- This counter keeps track of the number of overflows of the ACAM counter within one second
-- roll_over_counter: incr_counter
-- generic map
-- (width => g_width)
-- port map
-- (clk_i => clk_i,
-- rst_i => roll_over_c_rst,
-- counter_top_i => x"FFFFFFFF",
-- counter_incr_en_i => acam_intflag_f_edge_p_i,
-- counter_is_full_o => open,
-- counter_o => roll_over_c);
roll_over_counter: process (clk_i)
begin
if rising_edge (clk_i) then
if utc_p_i = '1' and acam_intflag_f_edge_p_i = '0' then
roll_over_c <= x"00000000";
-- the following case covers the rare possibility when utc_p_i and acam_intflag_f_edge_p_i
-- arrive on the exact same moment
elsif utc_p_i = '1' and acam_intflag_f_edge_p_i = '1' then
roll_over_c <= x"00000001";
......@@ -305,9 +302,11 @@ begin
clk_i_cycles_offset_o <= clk_i_cycles_offset;
retrig_nb_offset_o <= retrig_nb_offset;
roll_over_nb_o <= std_logic_vector(roll_over_c);
current_retrig_nb_o <= current_retrig_nb; ----------------
current_retrig_nb_o <= current_retrig_nb; -- for debug
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
......
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