Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC TDC 1ns 5cha - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC TDC 1ns 5cha - Gateware
Commits
7b243fd4
Commit
7b243fd4
authored
Sep 26, 2019
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[hdl] [bugfix] Fix overflow/underflow check in timestamp adder/subtractor
parent
84ffc99f
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
3 additions
and
3 deletions
+3
-3
tdc_ts_addsub.vhd
hdl/rtl/tdc_ts_addsub.vhd
+3
-3
No files found.
hdl/rtl/tdc_ts_addsub.vhd
View file @
7b243fd4
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 201
8-09-10
-- Last update: 201
9-09-26
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -169,9 +169,9 @@ begin -- rtl
unf_coarse
<=
"00"
;
end
if
;
if
(
sums
(
1
)
.
coarse
>=
g_
frac
_range
)
then
if
(
sums
(
1
)
.
coarse
>=
g_
coarse
_range
)
then
ovf_coarse
<=
"10"
;
elsif
(
sums
(
1
)
.
coarse
>=
2
*
g_
frac
_range
)
then
elsif
(
sums
(
1
)
.
coarse
>=
2
*
g_
coarse
_range
)
then
ovf_coarse
<=
"01"
;
else
ovf_coarse
<=
"00"
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment