Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC TDC 1ns 5cha - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC TDC 1ns 5cha - Gateware
Commits
57cd1fbe
Commit
57cd1fbe
authored
Aug 10, 2018
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: replace all syncrhonizers (except the ones for ACAM EF signals) with gc_sync_ffs
parent
4db629ed
Hide whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
133 additions
and
141 deletions
+133
-141
acam_databus_interface.vhd
hdl/rtl/acam_databus_interface.vhd
+5
-3
acam_timecontrol_interface.vhd
hdl/rtl/acam_timecontrol_interface.vhd
+16
-26
clks_rsts_manager.vhd
hdl/rtl/clks_rsts_manager.vhd
+50
-64
fmc_tdc_mezzanine.vhd
hdl/rtl/fmc_tdc_mezzanine.vhd
+4
-2
tdc_core_pkg.vhd
hdl/rtl/tdc_core_pkg.vhd
+2
-2
wrabbit_sync.vhd
hdl/rtl/wrabbit_sync.vhd
+56
-44
No files found.
hdl/rtl/acam_databus_interface.vhd
View file @
57cd1fbe
...
@@ -142,8 +142,6 @@ architecture rtl of acam_databus_interface is
...
@@ -142,8 +142,6 @@ architecture rtl of acam_databus_interface is
signal
ack
,
rd
,
rd_extend
:
std_logic
;
signal
ack
,
rd
,
rd_extend
:
std_logic
;
signal
wr
,
wr_extend
,
wr_remove
:
std_logic
;
signal
wr
,
wr_extend
,
wr_remove
:
std_logic
;
--=================================================================================================
--=================================================================================================
-- architecture begin
-- architecture begin
--=================================================================================================
--=================================================================================================
...
@@ -152,7 +150,11 @@ begin
...
@@ -152,7 +150,11 @@ begin
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Input Synchronizers --
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Do not convert this to gc_sync_ffs, the ACAM readout process depends on it.
-- see also data_engine_fsm_comb process in data_engine.vhd.
-- Because there is a reset, Xilinx will not use shift registers here and the
-- sync chain will be implemented using FFs, no need for a "shreg_extract" attribute.
input_registers
:
process
(
clk_i
)
input_registers
:
process
(
clk_i
)
begin
begin
if
rising_edge
(
clk_i
)
then
if
rising_edge
(
clk_i
)
then
...
...
hdl/rtl/acam_timecontrol_interface.vhd
View file @
57cd1fbe
...
@@ -106,8 +106,6 @@ end acam_timecontrol_interface;
...
@@ -106,8 +106,6 @@ end acam_timecontrol_interface;
--=================================================================================================
--=================================================================================================
architecture
rtl
of
acam_timecontrol_interface
is
architecture
rtl
of
acam_timecontrol_interface
is
signal
int_flag_synch
,
err_flag_synch
:
std_logic_vector
(
2
downto
0
);
signal
acam_intflag_f_edge_p
:
std_logic
;
signal
start_pulse
,
wait_for_utc
,
rst_n
,
wait_for_state_active
:
std_logic
;
signal
start_pulse
,
wait_for_utc
,
rst_n
,
wait_for_state_active
:
std_logic
;
...
@@ -116,34 +114,26 @@ architecture rtl of acam_timecontrol_interface is
...
@@ -116,34 +114,26 @@ architecture rtl of acam_timecontrol_interface is
--=================================================================================================
--=================================================================================================
begin
begin
rst_n
<=
not
(
rst_i
);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- IntFlag and ERRflag Input Synchronizers --
-- IntFlag and ERRflag Input Synchronizers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
rst_n
<=
not
(
rst_i
);
sync_err_flag
:
gc_sync_ffs
port
map
(
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_i
=>
clk_i
,
sync_err_flag
:
process
(
clk_i
)
-- synchronisation registers for ERR external signal
rst_n_i
=>
'1'
,
begin
data_i
=>
err_flag_i
,
if
rising_edge
(
clk_i
)
then
ppulse_o
=>
acam_errflag_r_edge_p_o
,
if
rst_i
=
'1'
then
npulse_o
=>
acam_errflag_f_edge_p_o
);
err_flag_synch
<=
(
others
=>
'0'
);
int_flag_synch
<=
(
others
=>
'0'
);
sync_int_flag
:
gc_sync_ffs
port
map
(
else
clk_i
=>
clk_i
,
err_flag_synch
<=
err_flag_i
&
err_flag_synch
(
2
downto
1
);
rst_n_i
=>
'1'
,
int_flag_synch
<=
int_flag_i
&
int_flag_synch
(
2
downto
1
);
data_i
=>
int_flag_i
,
end
if
;
npulse_o
=>
acam_intflag_f_edge_p_o
);
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
acam_errflag_f_edge_p_o
<=
not
(
err_flag_synch
(
1
))
and
err_flag_synch
(
0
);
acam_errflag_r_edge_p_o
<=
err_flag_synch
(
1
)
and
not
(
err_flag_synch
(
0
));
acam_intflag_f_edge_p
<=
not
(
int_flag_synch
(
1
))
and
int_flag_synch
(
0
);
acam_intflag_f_edge_p_o
<=
acam_intflag_f_edge_p
;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- start_from_fpga_o generation --
-- start_from_fpga_o generation --
...
...
hdl/rtl/clks_rsts_manager.vhd
View file @
57cd1fbe
...
@@ -77,6 +77,8 @@ use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
...
@@ -77,6 +77,8 @@ use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific libraries
-- Specific libraries
library
work
;
library
work
;
use
work
.
tdc_core_pkg
.
all
;
-- definitions of types, constants, entities
use
work
.
tdc_core_pkg
.
all
;
-- definitions of types, constants, entities
use
work
.
gencores_pkg
.
all
;
library
UNISIM
;
library
UNISIM
;
use
UNISIM
.
vcomponents
.
all
;
use
UNISIM
.
vcomponents
.
all
;
...
@@ -161,9 +163,8 @@ architecture rtl of clks_rsts_manager is
...
@@ -161,9 +163,8 @@ architecture rtl of clks_rsts_manager is
signal
send_dac_word_r_edge_p
,
dac_only
:
std_logic
;
signal
send_dac_word_r_edge_p
,
dac_only
:
std_logic
;
signal
pll_cs_n
,
dac_cs_n
:
std_logic
;
signal
pll_cs_n
,
dac_cs_n
:
std_logic
;
-- Synchronizers
-- Synchronizers
signal
pll_status_synch
,
internal_rst_synch
:
std_logic_vector
(
1
downto
0
);
signal
pll_status_synch
,
internal_rst_synch
:
std_logic
;
signal
rst_in_synch
:
std_logic_vector
(
1
downto
0
)
:
=
"11"
;
signal
rst_in_synch
:
std_logic
:
=
'0'
;
signal
acam_refclk_synch
,
send_dac_word_p_synch
:
std_logic_vector
(
2
downto
0
);
-- Clock buffers
-- Clock buffers
signal
tdc_clk_buf
:
std_logic
;
signal
tdc_clk_buf
:
std_logic
;
signal
tdc_clk
,
acam_refclk
:
std_logic
;
signal
tdc_clk
,
acam_refclk
:
std_logic
;
...
@@ -303,29 +304,26 @@ begin
...
@@ -303,29 +304,26 @@ begin
-- Synchronous process rst_n_i_synchronizer: Synchronization of the input reset signal rst_n_i,
-- Synchronous process rst_n_i_synchronizer: Synchronization of the input reset signal rst_n_i,
-- coming from the GN4124/VME interface or a PoR, to the clk_sys_i, using a set of 2 registers.
-- coming from the GN4124/VME interface or a PoR, to the clk_sys_i, using a set of 2 registers.
-- Note that the removal of the reset signal is synchronised.
-- Note that the removal of the reset signal is synchronised.
PoR_synchronizer
:
process
(
clk_sys_i
)
begin
PoR_synchronizer
:
gc_sync_ffs
if
rising_edge
(
clk_sys_i
)
then
port
map
(
rst_in_synch
<=
rst_in_synch
(
0
)
&
not
rst_n_i
;
clk_i
=>
clk_sys_i
,
end
if
;
rst_n_i
=>
'1'
,
end
process
;
data_i
=>
rst_n_i
,
synced_o
=>
rst_in_synch
);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Synchronous process pll_status_synchronizer: Synchronization of the pll_status_i input to the
-- Synchronous process pll_status_synchronizer: Synchronization of the pll_status_i input to the
-- clk_sys_i, using a set of 2 registers.
-- clk_sys_i, using a set of 2 registers.
pll_status_synchronizer
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_in_synch
(
1
)
=
'1'
then
pll_status_synch
<=
(
others
=>
'0'
);
else
pll_status_synch
<=
pll_status_synch
(
0
)
&
pll_status_i
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- --
pll_status_o
<=
pll_status_synch
(
1
);
pll_status_synchronizer
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
'1'
,
data_i
=>
pll_status_i
,
synced_o
=>
pll_status_synch
);
pll_status_o
<=
pll_status_synch
;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Synchronous process rst_generation: Generation of a reset signal for as long as the PLL
-- Synchronous process rst_generation: Generation of a reset signal for as long as the PLL
...
@@ -336,10 +334,10 @@ begin
...
@@ -336,10 +334,10 @@ begin
rst_generation
:
process
(
clk_sys_i
)
rst_generation
:
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
rst_in_synch
(
1
)
=
'1
'
then
if
rst_in_synch
=
'0
'
then
rst
<=
'1'
;
rst
<=
'1'
;
else
else
if
pll_status_synch
(
1
)
=
'1'
then
if
pll_status_synch
=
'1'
then
if
rst_cnt
=
"11111111"
then
if
rst_cnt
=
"11111111"
then
rst
<=
'0'
;
rst
<=
'0'
;
else
else
...
@@ -357,15 +355,15 @@ begin
...
@@ -357,15 +355,15 @@ begin
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Synchronous process internal_rst_synchronizer: Synchronization of the above generated rst signal
-- Synchronous process internal_rst_synchronizer: Synchronization of the above generated rst signal
-- to the 125MHz tdc_clk, using a set of 2 registers.
-- to the 125MHz tdc_clk, using a set of 2 registers.
Internal_rst_synchronizer
:
process
(
tdc_clk
)
begin
if
rising_edge
(
tdc_clk
)
then
internal_rst_synch
<=
internal_rst_synch
(
0
)
&
rst
;
end
if
;
end
process
;
-- -- -- -- -- -- -- --
internal_rst_o
<=
internal_rst_synch
(
1
);
Internal_rst_synchronizer
:
gc_sync_ffs
port
map
(
clk_i
=>
tdc_clk
,
rst_n_i
=>
'1'
,
data_i
=>
rst
,
synced_o
=>
internal_rst_synch
);
internal_rst_o
<=
internal_rst_synch
;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- ACAM Reference Clock --
-- ACAM Reference Clock --
...
@@ -383,19 +381,12 @@ begin
...
@@ -383,19 +381,12 @@ begin
IB
=>
acam_refclk_n_i
);
-- Diff_n buffer input (connect directly to top-level port)
IB
=>
acam_refclk_n_i
);
-- Diff_n buffer input (connect directly to top-level port)
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
acam_refclk_synchronizer
:
process
(
tdc_clk
)
acam_refclk_synchronizer
:
gc_sync_ffs
begin
port
map
(
if
rising_edge
(
tdc_clk
)
then
clk_i
=>
tdc_clk
,
if
internal_rst_synch
(
1
)
=
'1'
then
rst_n_i
=>
'1'
,
acam_refclk_synch
<=
(
others
=>
'0'
);
data_i
=>
acam_refclk
,
else
ppulse_o
=>
acam_refclk_r_edge_p_o
);
acam_refclk_synch
<=
acam_refclk_synch
(
1
downto
0
)
&
acam_refclk
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- --
acam_refclk_r_edge_p_o
<=
(
not
acam_refclk_synch
(
2
))
and
acam_refclk_synch
(
1
);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- DAC configuration --
-- DAC configuration --
...
@@ -403,18 +394,13 @@ begin
...
@@ -403,18 +394,13 @@ begin
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Synchronous process send_dac_word_p_synchronizer: Synchronization of the send_dac_word_p_o
-- Synchronous process send_dac_word_p_synchronizer: Synchronization of the send_dac_word_p_o
-- input to the clk_sys_i, using a set of 3 registers.
-- input to the clk_sys_i, using a set of 3 registers.
send_dac_word_p_synchronizer
:
process
(
clk_sys_i
)
send_dac_word_p_synchronizer
:
gc_sync_ffs
begin
port
map
(
if
rising_edge
(
clk_sys_i
)
then
clk_i
=>
clk_sys_i
,
if
rst_in_synch
(
1
)
=
'1'
then
rst_n_i
=>
'1'
,
send_dac_word_p_synch
<=
(
others
=>
'0'
);
data_i
=>
send_dac_word_p_i
,
else
ppulse_o
=>
send_dac_word_r_edge_p
);
send_dac_word_p_synch
<=
send_dac_word_p_synch
(
1
downto
0
)
&
send_dac_word_p_i
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- --
send_dac_word_r_edge_p
<=
(
not
send_dac_word_p_synch
(
2
))
and
send_dac_word_p_synch
(
1
);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Synchronous process dac_word_reg: selection of the word to be sent to the DAC.
-- Synchronous process dac_word_reg: selection of the word to be sent to the DAC.
...
@@ -423,7 +409,7 @@ begin
...
@@ -423,7 +409,7 @@ begin
dac_word_reg
:
process
(
clk_sys_i
)
dac_word_reg
:
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
rst_in_synch
(
1
)
=
'1
'
then
if
rst_in_synch
=
'0
'
then
dac_word
<=
c_DEFAULT_DAC_WORD
;
dac_word
<=
c_DEFAULT_DAC_WORD
;
elsif
send_dac_word_r_edge_p
=
'1'
then
elsif
send_dac_word_r_edge_p
=
'1'
then
dac_word
<=
dac_word_i
;
dac_word
<=
dac_word_i
;
...
@@ -448,7 +434,7 @@ begin
...
@@ -448,7 +434,7 @@ begin
pll_dac_initialization_seq
:
process
(
clk_sys_i
)
pll_dac_initialization_seq
:
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
rst_in_synch
(
1
)
=
'1
'
or
send_dac_word_r_edge_p
=
'1'
then
if
rst_in_synch
=
'0
'
or
send_dac_word_r_edge_p
=
'1'
then
config_st
<=
config_start
;
config_st
<=
config_start
;
dac_only
<=
'0'
;
dac_only
<=
'0'
;
elsif
wrabbit_dac_wr_p_i
=
'1'
then
elsif
wrabbit_dac_wr_p_i
=
'1'
then
...
@@ -555,7 +541,7 @@ begin
...
@@ -555,7 +541,7 @@ begin
pll_sclk_generator
:
process
(
clk_sys_i
)
-- transitions take place on the falling edge of sclk
pll_sclk_generator
:
process
(
clk_sys_i
)
-- transitions take place on the falling edge of sclk
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
rst_in_synch
(
1
)
=
'1
'
then
if
rst_in_synch
=
'0
'
then
sclk
<=
'0'
;
sclk
<=
'0'
;
sclk_d1
<=
'0'
;
sclk_d1
<=
'0'
;
sclk_d2
<=
'0'
;
sclk_d2
<=
'0'
;
...
@@ -579,7 +565,7 @@ begin
...
@@ -579,7 +565,7 @@ begin
process
(
clk_sys_i
)
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
rst_in_synch
(
1
)
=
'1
'
then
if
rst_in_synch
=
'0
'
then
divider
<=
(
others
=>
'0'
);
divider
<=
(
others
=>
'0'
);
else
else
divider
<=
divider
+
1
;
divider
<=
divider
+
1
;
...
@@ -592,7 +578,7 @@ begin
...
@@ -592,7 +578,7 @@ begin
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
rst_in_synch
(
1
)
=
'1
'
then
if
rst_in_synch
=
'0
'
then
pll_bit_index
<=
15
;
pll_bit_index
<=
15
;
elsif
pll_cs_n
=
'1'
then
elsif
pll_cs_n
=
'1'
then
...
@@ -606,7 +592,7 @@ begin
...
@@ -606,7 +592,7 @@ begin
end
if
;
end
if
;
end
if
;
end
if
;
if
rst_in_synch
(
1
)
=
'1
'
then
if
rst_in_synch
=
'0
'
then
pll_byte_index
<=
nb_of_reg
-1
;
pll_byte_index
<=
nb_of_reg
-1
;
elsif
config_st
=
rest
and
sclk_r_edge
=
'1'
then
elsif
config_st
=
rest
and
sclk_r_edge
=
'1'
then
if
pll_byte_index
=
0
then
if
pll_byte_index
=
0
then
...
@@ -628,7 +614,7 @@ begin
...
@@ -628,7 +614,7 @@ begin
begin
begin
if
rising_edge
(
clk_sys_i
)
then
-- counting of bits that are sent on the falling edges
if
rising_edge
(
clk_sys_i
)
then
-- counting of bits that are sent on the falling edges
if
rst_in_synch
(
1
)
=
'1
'
then
if
rst_in_synch
=
'0
'
then
dac_bit_index
<=
23
;
dac_bit_index
<=
23
;
elsif
dac_cs_n
=
'1'
and
sclk_f_edge
=
'1'
then
elsif
dac_cs_n
=
'1'
and
sclk_f_edge
=
'1'
then
...
@@ -823,4 +809,4 @@ begin
...
@@ -823,4 +809,4 @@ begin
end
rtl
;
end
rtl
;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- architecture ends
-- architecture ends
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @
57cd1fbe
...
@@ -252,6 +252,8 @@ architecture rtl of fmc_tdc_mezzanine is
...
@@ -252,6 +252,8 @@ architecture rtl of fmc_tdc_mezzanine is
8
=>
f_sdb_embed_device
(
c_TDC_FIFO_SDB_DEVICE
,
x"00005400"
)
8
=>
f_sdb_embed_device
(
c_TDC_FIFO_SDB_DEVICE
,
x"00005400"
)
);
);
constant
c_SYNC_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
f_pick
(
g_simulation
,
c_SIM_CLK_PERIOD
,
c_SYN_CLK_PERIOD
);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Signals --
-- Signals --
...
@@ -465,8 +467,8 @@ begin
...
@@ -465,8 +467,8 @@ begin
wrabbit_utc_p
<=
'0'
;
wrabbit_utc_p
<=
'0'
;
else
else
if
wrabbit_clk_aux_locked_i
=
'1'
and
g_with_wrabbit_core
then
if
wrabbit_clk_aux_locked_i
=
'1'
and
g_with_wrabbit_core
then
if
unsigned
(
wrabbit_cycles_i
)
=
(
unsigned
(
c_SYN_CLK_PERIOD
)
-3
)
then
-- so that the end of the puls
e
-- so that the end of the pulse comes exactly upon the UTC chang
e
-- comes exactly upon the UTC change
if
unsigned
(
wrabbit_cycles_i
)
=
unsigned
(
c_SYNC_PERIOD
)
-3
then
wrabbit_utc_p
<=
'1'
;
wrabbit_utc_p
<=
'1'
;
else
else
wrabbit_utc_p
<=
'0'
;
wrabbit_utc_p
<=
'0'
;
...
...
hdl/rtl/tdc_core_pkg.vhd
View file @
57cd1fbe
...
@@ -194,8 +194,8 @@ package tdc_core_pkg is
...
@@ -194,8 +194,8 @@ package tdc_core_pkg is
-- for synthesis: 1 sec = x"07735940" clk_i cycles (1 clk_i cycle = 8ns)
-- for synthesis: 1 sec = x"07735940" clk_i cycles (1 clk_i cycle = 8ns)
constant
c_SYN_CLK_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"07735940"
;
constant
c_SYN_CLK_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"07735940"
;
-- for simulation: 1
msec = x"0001E848
" clk_i cycles (1 clk_i cycle = 8ns)
-- for simulation: 1
00 usec = x"000030d4
" clk_i cycles (1 clk_i cycle = 8ns)
constant
c_SIM_CLK_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000
1000
"
;
constant
c_SIM_CLK_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000
30d4
"
;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
...
...
hdl/rtl/wrabbit_sync.vhd
View file @
57cd1fbe
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-24
-- Created : 2011-08-24
-- Last update: 201
2-11-26
-- Last update: 201
8-08-09
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -112,15 +112,15 @@ architecture rtl of wrabbit_sync is
...
@@ -112,15 +112,15 @@ architecture rtl of wrabbit_sync is
type
t_wrabbit_sync_state
is
(
wrabbit_CORE_OFFLINE
,
wrabbit_WAIT_READY
,
wrabbit_SYNCING
,
wrabbit_SYNCED
);
type
t_wrabbit_sync_state
is
(
wrabbit_CORE_OFFLINE
,
wrabbit_WAIT_READY
,
wrabbit_SYNCING
,
wrabbit_SYNCED
);
signal
wrabbit_state
:
t_wrabbit_sync_state
;
signal
wrabbit_state
:
t_wrabbit_sync_state
;
signal
wrabbit_state_changed
:
std_logic
;
signal
wrabbit_state_changed
:
std_logic
;
signal
wrabbit_state_syncing
,
wrabbit_en
:
std_logic
;
signal
wrabbit_state_syncing
:
std_logic
;
signal
wrabbit_clk_aux_lock_en
:
std_logic
;
signal
wrabbit_clk_aux_lock_en
:
std_logic
;
-- FSM timeout counter
-- FSM timeout counter
signal
tmo_restart
,
tmo_hit
:
std_logic
;
signal
tmo_restart
,
tmo_hit
:
std_logic
;
signal
tmo_cntr
:
unsigned
(
f_log2_size
(
c_wrabbit_STATE_TIMEOUT
)
-1
downto
0
);
signal
tmo_cntr
:
unsigned
(
f_log2_size
(
c_wrabbit_STATE_TIMEOUT
)
-1
downto
0
);
-- synchronizers
-- synchronizers
signal
wrabbit_en
_sync
,
time_valid
:
std_logic_vector
(
1
downto
0
)
;
signal
wrabbit_en
,
time_valid
:
std_logic
;
signal
clk_aux_locked
,
link_up
:
std_logic
_vector
(
1
downto
0
)
;
signal
clk_aux_locked
,
link_up
:
std_logic
;
signal
state_syncing
,
clk_aux_lock_en
:
std_logic
_vector
(
1
downto
0
)
;
signal
state_syncing
,
clk_aux_lock_en
:
std_logic
;
-- aux
-- aux
signal
with_wrabbit_core
:
std_logic
;
signal
with_wrabbit_core
:
std_logic
;
signal
dac_p_c
:
unsigned
(
23
downto
0
);
-- for debug
signal
dac_p_c
:
unsigned
(
23
downto
0
);
-- for debug
...
@@ -130,17 +130,13 @@ begin
...
@@ -130,17 +130,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the wrabbit_reg_i(0) of the reg_ctrl unit to the 62.5 MHz domain
-- Synchronization of the wrabbit_reg_i(0) of the reg_ctrl unit to the 62.5 MHz domain
input_synchronizer
:
process
(
clk_sys_i
)
begin
input_synchronizer
:
gc_sync_ffs
if
rising_edge
(
clk_sys_i
)
then
port
map
(
if
rst_n_sys_i
=
'0'
then
clk_i
=>
clk_sys_i
,
wrabbit_en_sync
<=
(
others
=>
'0'
);
rst_n_i
=>
'1'
,
else
data_i
=>
wrabbit_reg_i
(
0
),
wrabbit_en_sync
<=
wrabbit_en_sync
(
0
)
&
wrabbit_reg_i
(
0
);
synced_o
=>
wrabbit_en
);
end
if
;
end
if
;
end
process
;
wrabbit_en
<=
wrabbit_en_sync
(
1
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FSM timeout counter
-- FSM timeout counter
...
@@ -222,40 +218,56 @@ begin
...
@@ -222,40 +218,56 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the outputs to the 125 MHz domain to be used by the reg_ctrl unit
-- Synchronization of the outputs to the 125 MHz domain to be used by the reg_ctrl unit
outputs_synchronizer
:
process
(
clk_ref_i
)
outputs_synchronizer1
:
gc_sync_ffs
begin
port
map
(
if
rising_edge
(
clk_ref_i
)
then
clk_i
=>
clk_ref_i
,
if
rst_n_ref_i
=
'0'
then
rst_n_i
=>
'1'
,
clk_aux_locked
<=
(
others
=>
'0'
);
data_i
=>
wrabbit_clk_aux_locked_i
,
link_up
<=
(
others
=>
'0'
);
synced_o
=>
clk_aux_locked
);
state_syncing
<=
(
others
=>
'0'
);
clk_aux_lock_en
<=
(
others
=>
'0'
);
outputs_synchronizer2
:
gc_sync_ffs
time_valid
<=
(
others
=>
'0'
);
port
map
(
else
clk_i
=>
clk_ref_i
,
clk_aux_locked
<=
clk_aux_locked
(
0
)
&
wrabbit_clk_aux_locked_i
;
rst_n_i
=>
'1'
,
link_up
<=
link_up
(
0
)
&
wrabbit_link_up_i
;
data_i
=>
wrabbit_link_up_i
,
state_syncing
<=
state_syncing
(
0
)
&
wrabbit_state_syncing
;
synced_o
=>
link_up
);
clk_aux_lock_en
<=
clk_aux_lock_en
(
0
)
&
wrabbit_clk_aux_lock_en
;
time_valid
<=
time_valid
(
0
)
&
wrabbit_time_valid_i
;
outputs_synchronizer3
:
gc_sync_ffs
end
if
;
port
map
(
end
if
;
clk_i
=>
clk_ref_i
,
end
process
;
rst_n_i
=>
'1'
,
data_i
=>
wrabbit_state_syncing
,
synced_o
=>
state_syncing
);
outputs_synchronizer4
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_i
,
rst_n_i
=>
'1'
,
data_i
=>
wrabbit_clk_aux_lock_en
,
synced_o
=>
clk_aux_lock_en
);
outputs_synchronizer5
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_i
,
rst_n_i
=>
'1'
,
data_i
=>
wrabbit_time_valid_i
,
synced_o
=>
time_valid
);
with_wrabbit_core
<=
'1'
when
g_with_wrabbit_core
else
'0'
;
with_wrabbit_core
<=
'1'
when
g_with_wrabbit_core
else
'0'
;
wrabbit_synched_o
<=
clk_aux_locked
(
1
)
and
with_wrabbit_core
;
wrabbit_synched_o
<=
clk_aux_locked
and
with_wrabbit_core
;
wrabbit_clk_aux_lock_en_o
<=
clk_aux_lock_en
(
1
)
and
with_wrabbit_core
;
wrabbit_clk_aux_lock_en_o
<=
clk_aux_lock_en
and
with_wrabbit_core
;
wrabbit_state_syncing
<=
'1'
when
((
wrabbit_state
=
wrabbit_SYNCING
or
wrabbit_state
=
wrabbit_SYNCED
)
and
with_wrabbit_core
=
'1'
)
else
'0'
;
wrabbit_state_syncing
<=
'1'
when
((
wrabbit_state
=
wrabbit_SYNCING
or
wrabbit_state
=
wrabbit_SYNCED
)
and
with_wrabbit_core
=
'1'
)
else
'0'
;
wrabbit_reg_o
(
0
)
<=
'1'
;
-- reserved
wrabbit_reg_o
(
0
)
<=
'1'
;
-- reserved
wrabbit_reg_o
(
1
)
<=
with_wrabbit_core
;
wrabbit_reg_o
(
1
)
<=
with_wrabbit_core
;
wrabbit_reg_o
(
2
)
<=
link_up
(
1
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
2
)
<=
link_up
and
with_wrabbit_core
;
wrabbit_reg_o
(
3
)
<=
state_syncing
(
1
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
3
)
<=
state_syncing
and
with_wrabbit_core
;
wrabbit_reg_o
(
4
)
<=
clk_aux_locked
(
1
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
4
)
<=
clk_aux_locked
and
with_wrabbit_core
;
wrabbit_reg_o
(
5
)
<=
time_valid
(
1
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
5
)
<=
time_valid
and
with_wrabbit_core
;
wrabbit_reg_o
(
6
)
<=
wrabbit_reg_i
(
0
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
6
)
<=
wrabbit_reg_i
(
0
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
7
)
<=
clk_aux_locked
(
1
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
7
)
<=
clk_aux_locked
and
with_wrabbit_core
;
wrabbit_reg_o
(
8
)
<=
time_valid
(
1
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
8
)
<=
time_valid
and
with_wrabbit_core
;
wrabbit_reg_o
(
9
)
<=
clk_aux_lock_en
(
1
)
and
with_wrabbit_core
;
wrabbit_reg_o
(
9
)
<=
clk_aux_lock_en
and
with_wrabbit_core
;
wrabbit_reg_o
(
15
downto
10
)
<=
(
others
=>
'0'
)
when
with_wrabbit_core
=
'1'
else
std_logic_vector
(
dac_p_c
(
5
downto
0
));
wrabbit_reg_o
(
15
downto
10
)
<=
(
others
=>
'0'
)
when
with_wrabbit_core
=
'1'
else
std_logic_vector
(
dac_p_c
(
5
downto
0
));
wrabbit_reg_o
(
31
downto
16
)
<=
(
others
=>
'0'
)
when
with_wrabbit_core
=
'1'
else
wrabbit_dac_value_i
(
15
downto
0
);
wrabbit_reg_o
(
31
downto
16
)
<=
(
others
=>
'0'
)
when
with_wrabbit_core
=
'1'
else
wrabbit_dac_value_i
(
15
downto
0
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment