fmc_tdc_core: fix 131us timestamp error

4bbd2889 · Tomasz Wlostowski · b10c63a4 · 4bbd2889 · 4bbd2889
Commit 4bbd2889 authored Sep 07, 2018 by Tomasz Wlostowski
Hide whitespace changes
Inline Side-by-side

Showing with 9 additions and 4 deletions

data_formatting.vhd hdl/rtl/data_formatting.vhd +7 -3

fmc_tdc_core.vhd hdl/rtl/fmc_tdc_core.vhd +2 -1

No files found.
--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
@@ -94,6 +94,7 @@ entity data_formatting is
     clk_i_cycles_offset_i   : in std_logic_vector(31 downto 0);
     roll_over_nb_i          : in std_logic_vector(31 downto 0);
     retrig_nb_offset_i      : in std_logic_vector(31 downto 0);
+     current_retrig_nb_i     : in std_logic_vector(31 downto 0);
     -- Signal from the WRabbit core or the one_hz_generator unit
     utc_p_i : in std_logic;
@@ -138,6 +139,7 @@ architecture rtl of data_formatting is
  signal un_acam_fine_time                                    : unsigned(31 downto 0);
  signal previous_utc                                         : std_logic_vector(31 downto 0);
  signal timestamp_valid_int : std_logic;
+  signal timestamp_valid_int_d : std_logic;
 --=================================================================================================
 --                                       architecture begin
@@ -152,6 +154,7 @@ begin
        timestamp_valid_int <= '0';
      else
        timestamp_valid_int <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
+        timestamp_valid_int_d <= timestamp_valid_int;
      end if;
    end if;
  end process;
@@ -200,13 +203,13 @@ begin
        acam_channel        <= "0" & acam_tstamp1_i(27 downto 26);
        acam_fine_timestamp <= acam_tstamp1_i(16 downto 0);
        acam_slope          <= acam_tstamp1_i(17);
-        acam_start_nb       <= unsigned(acam_tstamp1_i(25 downto 18))-1;
+        acam_start_nb       <= unsigned(acam_tstamp1_i(25 downto 18));
      elsif acam_tstamp2_ok_p_i = '1' then
        acam_channel        <= "1" & acam_tstamp2_i(27 downto 26);
        acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
        acam_slope          <= acam_tstamp2_i(17);
-        acam_start_nb       <= unsigned(acam_tstamp2_i(25 downto 18))-1;
+        acam_start_nb       <= unsigned(acam_tstamp2_i(25 downto 18));
      end if;
    end if;
  end process;
@@ -290,7 +293,8 @@ begin
          un_retrig_nb_offset    <= unsigned(retrig_nb_offset_i);
          utc                    <= utc_i;
          coarse_zero            <= '0';
-          if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
+          if acam_start_nb = 255 and unsigned(current_retrig_nb_i) = 0 then
+          ccase <= "010";
            un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i)-1, 8);
          else
            un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i), 8);

--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
@@ -499,7 +499,7 @@ begin
 ---------------------------------------------------------------------------------------------------
 --                                       DATA FORMATTING                                         --
 ---------------------------------------------------------------------------------------------------
-  data_formatting_block : data_formatting
+  data_formatting_block : entity work.data_formatting
    port map
    (clk_i                   => clk_tdc_i,
     rst_i                   => rst_tdc_i,
@@ -511,6 +511,7 @@ begin
     clk_i_cycles_offset_i   => clk_i_cycles_offset,
     roll_over_nb_i          => roll_over_nb,
     retrig_nb_offset_i      => retrig_nb_offset,
+     current_retrig_nb_i => current_retrig_nb,
     utc_p_i                 => utc_p,
     utc_i                   => utc,
     timestamp_o             => timestamp,