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FMC TDC 1ns 5cha - Gateware
Commit 45f22114 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fmc_tdc_wrapper: added 125 MHz FMC clock output

parent dce05010
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Showing with 6 additions and 2 deletions
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_wrapper.vhd
View file @ 45f22114
......@@ -214,7 +214,9 @@ entity fmc_tdc_wrapper is
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out;
irq_o : out std_logic
irq_o : out std_logic;
clk_125m_tdc_o: out std_logic
); -- Mezzanine presence (active low)
end fmc_tdc_wrapper;
......@@ -289,6 +291,7 @@ begin
pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk;
clk_125m_tdc_o <= clk_125m_mezz;
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
......
hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
View file @ 45f22114
......@@ -1070,7 +1070,8 @@ package tdc_core_pkg is
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out;
irq_o : out std_logic);
irq_o : out std_logic;
clk_125m_tdc_o: out std_logic);
end component fmc_tdc_wrapper;
component fmc_tdc_direct_readout is
......
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