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FMC TDC 1ns 5cha - Gateware
Commits
44e72646
Commit
44e72646
authored
Sep 11, 2018
by
Tomasz Wlostowski
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rtl: replace Sockit onewire master with a hardware DS18xx interface, clean up core top level
parent
fc5df2b2
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8 changed files
with
502 additions
and
163 deletions
+502
-163
Manifest.py
hdl/rtl/Manifest.py
+4
-1
build_wb.sh
hdl/rtl/build_wb.sh
+1
-0
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+39
-37
fmc_tdc_mezzanine.vhd
hdl/rtl/fmc_tdc_mezzanine.vhd
+58
-50
tdc_core_pkg.vhd
hdl/rtl/tdc_core_pkg.vhd
+68
-75
tdc_onewire_wb.vhd
hdl/rtl/tdc_onewire_wb.vhd
+168
-0
tdc_onewire_wbgen2_pkg.vhd
hdl/rtl/tdc_onewire_wbgen2_pkg.vhd
+100
-0
tdc_onewire_wb.wb
hdl/rtl/wbgen/tdc_onewire_wb.wb
+64
-0
No files found.
hdl/rtl/Manifest.py
View file @
44e72646
...
...
@@ -30,7 +30,10 @@ files = [
"tdc_buffer_control_regs.vhd"
,
"tdc_buffer_control_regs_wbgen2_pkg.vhd"
,
"tdc_ts_addsub.vhd"
,
"tdc_ts_sub.vhd"
,
"wbgen2_eic_nomask.vhd"
,
"dma_eic.vhd"
"dma_eic.vhd"
,
"tdc_onewire_wb.vhd"
,
"tdc_onewire_wbgen2_pkg.vhd"
];
hdl/rtl/build_wb.sh
View file @
44e72646
#!/bin/bash
wbgen2
-V
timestamp_fifo_wb.vhd
-H
record_full
-p
timestamp_fifo_wbgen2_pkg.vhd
-K
timestamp_fifo_regs.vh
-s
defines
-C
timestamp_fifo_regs.h
-D
wbgen/timestamp_fifo_wb.html wbgen/timestamp_fifo_wb.wb
wbgen2
-V
tdc_onewire_wb.vhd
-H
record_full
-p
tdc_onewire_wbgen2_pkg.vhd
-K
timestamp_onewire_regs.vh
-s
defines
-C
tdc_onewire_regs.h wbgen/tdc_onewire_wb.wb
#wbgen2 -V tdc_buffer_control_regs.vhd -H record_full -p tdc_buffer_control_regs_wbgen2_pkg.vhd -K tdc_buffer_control_regs.vh -s defines -C tdc_buffer_control_regs.h wbgen/tdc_buffer_control_regs.wb
#don't do this, latest wbgen is buggy
...
...
hdl/rtl/fmc_tdc_core.vhd
View file @
44e72646
...
...
@@ -211,9 +211,9 @@ entity fmc_tdc_core is
cfg_slave_i
:
in
t_wishbone_slave_in
;
cfg_slave_o
:
out
t_wishbone_slave_out
;
ts_offset_i
:
in
t_tdc_timestamp_array
(
4
downto
0
);
reset_seq_i
:
in
std_logic_vector
(
4
downto
0
);
raw_enable_i
:
in
std_logic_vector
(
4
downto
0
);
ts_offset_i
:
in
t_tdc_timestamp_array
(
4
downto
0
);
reset_seq_i
:
in
std_logic_vector
(
4
downto
0
);
raw_enable_i
:
in
std_logic_vector
(
4
downto
0
);
timestamp_o
:
out
t_tdc_timestamp_array
(
4
downto
0
);
timestamp_valid_o
:
out
std_logic_vector
(
4
downto
0
);
timestamp_ready_i
:
in
std_logic_vector
(
4
downto
0
);
...
...
@@ -234,7 +234,7 @@ architecture rtl of fmc_tdc_core is
signal
acm_adr
:
std_logic_vector
(
7
downto
0
);
signal
acm_cyc
,
acm_stb
,
acm_we
,
acm_ack
:
std_logic
;
signal
acm_dat_r
,
acm_dat_w
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
acam_ef1
,
acam_ef2
,
acam_ef1_meta
,
acam_ef2_meta
:
std_logic
;
signal
acam_ef1
,
acam_ef2
:
std_logic
;
signal
acam_errflag_f_edge_p
,
acam_errflag_r_edge_p
:
std_logic
;
signal
acam_intflag_f_edge_p
:
std_logic
;
signal
acam_tstamp1
,
acam_tstamp2
:
std_logic_vector
(
g_width
-1
downto
0
);
...
...
@@ -265,7 +265,7 @@ architecture rtl of fmc_tdc_core is
signal
acam_tstamp_channel
:
std_logic_vector
(
2
downto
0
);
signal
raw_timestamp_valid
:
std_logic
;
signal
raw_timestamp
:
t_
raw_
acam_timestamp
;
signal
raw_timestamp
:
t_acam_timestamp
;
signal
final_timestamp_valid
:
std_logic_vector
(
4
downto
0
);
signal
final_timestamp_ready
:
std_logic_vector
(
4
downto
0
);
...
...
@@ -276,13 +276,12 @@ architecture rtl of fmc_tdc_core is
signal
channel_enable_sys
:
std_logic_vector
(
4
downto
0
);
signal
rst_sys
,
rst_tdc
:
std_logic
;
signal
core_status
:
std_logic_vector
(
31
downto
0
);
signal
core_status
:
std_logic_vector
(
31
downto
0
);
signal
gen_fake_ts_enable
:
std_logic
;
signal
gen_fake_ts_enable
:
std_logic
;
signal
gen_fake_ts_channel
:
std_logic_vector
(
2
downto
0
);
signal
gen_fake_ts_period
:
std_logic_vector
(
27
downto
0
);
signal
gen_fake_ts_period
:
std_logic_vector
(
27
downto
0
);
--=================================================================================================
-- architecture begin
...
...
@@ -298,7 +297,7 @@ begin
core_status
(
0
)
<=
'1'
when
g_with_dma_readout
else
'0'
;
core_status
(
1
)
<=
'1'
when
g_with_fifo_readout
else
'0'
;
core_status
(
31
downto
2
)
<=
(
others
=>
'0'
);
reg_control_block
:
entity
work
.
reg_ctrl
generic
map
(
g_span
=>
g_span
,
...
...
@@ -341,9 +340,9 @@ begin
send_dac_word_p_o
=>
send_dac_word_p_o
,
dac_word_o
=>
dac_word_o
,
one_hz_phase_o
=>
pulse_delay
,
gen_fake_ts_period_o
=>
gen_fake_ts_period
,
gen_fake_ts_enable_o
=>
gen_fake_ts_enable
,
gen_fake_ts_channel_o
=>
gen_fake_ts_channel
gen_fake_ts_period_o
=>
gen_fake_ts_period
,
gen_fake_ts_enable_o
=>
gen_fake_ts_enable
,
gen_fake_ts_channel_o
=>
gen_fake_ts_channel
);
process
(
clk_tdc_i
)
...
...
@@ -438,9 +437,7 @@ begin
rd_n_o
=>
rd_n_o
,
wr_n_o
=>
wr_n_o
,
ef1_o
=>
acam_ef1
,
ef1_meta_o
=>
acam_ef1_meta
,
ef2_o
=>
acam_ef2
,
ef2_meta_o
=>
acam_ef2_meta
,
clk_i
=>
clk_tdc_i
,
rst_i
=>
rst_tdc
,
adr_i
=>
acm_adr
,
...
...
@@ -473,7 +470,7 @@ begin
---------------------------------------------------------------------------------------------------
-- DATA ENGINE --
---------------------------------------------------------------------------------------------------
data_engine_block
:
data_engine
data_engine_block
:
entity
work
.
data_engine
generic
map
(
g_simulation
=>
g_simulation
)
port
map
...
...
@@ -487,9 +484,7 @@ begin
clk_i
=>
clk_tdc_i
,
rst_i
=>
rst_tdc
,
acam_ef1_i
=>
acam_ef1
,
acam_ef1_meta_i
=>
acam_ef1_meta
,
acam_ef2_i
=>
acam_ef2
,
acam_ef2_meta_i
=>
acam_ef2_meta
,
activate_acq_p_i
=>
activate_acq_p
,
deactivate_acq_p_i
=>
deactivate_acq_p
,
acam_wr_config_p_i
=>
load_acam_config
,
...
...
@@ -527,12 +522,12 @@ begin
clk_i_cycles_offset_i
=>
clk_i_cycles_offset
,
roll_over_nb_i
=>
roll_over_nb
,
retrig_nb_offset_i
=>
retrig_nb_offset
,
current_retrig_nb_i
=>
current_retrig_nb
,
current_retrig_nb_i
=>
current_retrig_nb
,
utc_p_i
=>
utc_p
,
utc_i
=>
utc
,
gen_fake_ts_period_i
=>
gen_fake_ts_period
,
gen_fake_ts_enable_i
=>
gen_fake_ts_enable
,
gen_fake_ts_channel_i
=>
gen_fake_ts_channel
,
gen_fake_ts_period_i
=>
gen_fake_ts_period
,
gen_fake_ts_enable_i
=>
gen_fake_ts_enable
,
gen_fake_ts_channel_i
=>
gen_fake_ts_channel
,
timestamp_o
=>
raw_timestamp
,
timestamp_valid_o
=>
raw_timestamp_valid
);
...
...
@@ -545,14 +540,14 @@ begin
clk_sys_i
=>
clk_sys_i
,
rst_sys_n_i
=>
rst_sys_n_i
,
enable_i
=>
channel_enable_sys
,
ts_i
=>
raw_timestamp
,
ts_valid_i
=>
raw_timestamp_valid
,
ts_o
=>
final_timestamp
,
ts_valid_o
=>
final_timestamp_valid
,
ts_ready_i
=>
final_timestamp_ready
,
ts_offset_i
=>
ts_offset_i
,
reset_seq_i
=>
reset_seq_i
,
enable_i
=>
channel_enable_sys
,
ts_i
=>
raw_timestamp
,
ts_valid_i
=>
raw_timestamp_valid
,
ts_o
=>
final_timestamp
,
ts_valid_o
=>
final_timestamp_valid
,
ts_ready_i
=>
final_timestamp_ready
,
ts_offset_i
=>
ts_offset_i
,
reset_seq_i
=>
reset_seq_i
,
raw_enable_i
=>
raw_enable_i
);
...
...
@@ -570,7 +565,7 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC LEDs --
---------------------------------------------------------------------------------------------------
TDCboard_leds
:
leds_manager
TDCboard_leds
:
entity
work
.
leds_manager
generic
map
(
g_width
=>
32
,
g_simulation
=>
g_simulation
)
...
...
@@ -578,9 +573,16 @@ begin
(
clk_i
=>
clk_tdc_i
,
rst_i
=>
rst_tdc
,
utc_p_i
=>
local_utc_p
,
acam_inputs_en_i
=>
acam_inputs_en
,
acam_channel_i
=>
acam_channel
,
tstamp_wr_p_i
=>
final_timestamp_valid
(
0
),
tstamp_wr1_p_i
=>
final_timestamp_valid
(
0
),
tstamp_wr2_p_i
=>
final_timestamp_valid
(
1
),
tstamp_wr3_p_i
=>
final_timestamp_valid
(
2
),
tstamp_wr4_p_i
=>
final_timestamp_valid
(
3
),
tstamp_wr5_p_i
=>
final_timestamp_valid
(
4
),
term_en_5_i
=>
acam_inputs_en
(
4
),
term_en_4_i
=>
acam_inputs_en
(
3
),
term_en_3_i
=>
acam_inputs_en
(
2
),
term_en_2_i
=>
acam_inputs_en
(
1
),
term_en_1_i
=>
acam_inputs_en
(
0
),
tdc_led_status_o
=>
tdc_led_status_o
,
tdc_led_trig1_o
=>
tdc_led_trig1_o
,
tdc_led_trig2_o
=>
tdc_led_trig2_o
,
...
...
@@ -595,7 +597,7 @@ begin
---------------------------------------------------------------------------------------------------
start_dis_o
<=
'0'
;
U_Sync_ChannelEnable
:
entity
work
.
gc_sync_register
U_Sync_ChannelEnable
:
entity
work
.
gc_sync_register
generic
map
(
g_width
=>
5
)
port
map
(
...
...
@@ -603,7 +605,7 @@ begin
rst_n_a_i
=>
rst_sys_n_i
,
d_i
=>
channel_enable_tdc
,
q_o
=>
channel_enable_sys
);
channel_enable_tdc
<=
acam_inputs_en
(
20
downto
16
);
channel_enable_o
<=
channel_enable_sys
;
...
...
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @
44e72646
...
...
@@ -99,18 +99,18 @@ use IEEE.numeric_std.all;
use
work
.
tdc_core_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
TDC_OW_wbgen2_pkg
.
all
;
--=================================================================================================
-- Entity declaration for fmc_tdc_mezzanine
--=================================================================================================
entity
fmc_tdc_mezzanine
is
generic
(
g_with_wrabbit_core
:
boolean
:
=
false
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
g_simulation
:
boolean
:
=
false
;
g_use_dma_readout
:
boolean
:
=
true
;
(
g_with_wrabbit_core
:
boolean
:
=
false
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
g_simulation
:
boolean
:
=
false
;
g_use_dma_readout
:
boolean
:
=
true
;
g_use_fake_timestamps_for_sim
:
boolean
:
=
false
);
port
-- TDC core
...
...
@@ -189,8 +189,8 @@ entity fmc_tdc_mezzanine is
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
;
sim_timestamp_i
:
in
t_tdc_timestamp
:
=
c_dummy_timestamp
;
sim_timestamp_valid_i
:
in
std_logic
:
=
'0'
;
sim_timestamp_i
:
in
t_tdc_timestamp
:
=
c_dummy_timestamp
;
sim_timestamp_valid_i
:
in
std_logic
:
=
'0'
;
sim_timestamp_ready_o
:
out
std_logic
);
...
...
@@ -228,7 +228,7 @@ architecture rtl of fmc_tdc_mezzanine is
-- WISHBONE crossbar layout
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_MASTERS
-1
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
c_ONEWIRE_SDB_DEVICE
,
x"00001000"
),
(
0
=>
f_sdb_embed_device
(
c_
TDC_
ONEWIRE_SDB_DEVICE
,
x"00001000"
),
1
=>
f_sdb_embed_device
(
c_TDC_CONFIG_SDB_DEVICE
,
x"00002000"
),
2
=>
f_sdb_embed_device
(
c_TDC_EIC_DEVICE
,
x"00003000"
),
3
=>
f_sdb_embed_device
(
c_I2C_SDB_DEVICE
,
x"00004000"
),
...
...
@@ -269,15 +269,15 @@ architecture rtl of fmc_tdc_mezzanine is
signal
timestamp
:
t_tdc_timestamp_array
(
4
downto
0
);
signal
timestamp_valid
,
timestamp_ready
,
timestamp_stb
:
std_logic_vector
(
4
downto
0
);
signal
tdc_timestamp
:
t_tdc_timestamp_array
(
4
downto
0
);
signal
tdc_timestamp_valid
,
tdc_timestamp_ready
:
std_logic_vector
(
4
downto
0
);
signal
tdc_timestamp
:
t_tdc_timestamp_array
(
4
downto
0
);
signal
tdc_timestamp_valid
,
tdc_timestamp_ready
:
std_logic_vector
(
4
downto
0
);
signal
channel_enable
:
std_logic_vector
(
4
downto
0
);
signal
irq_threshold
,
irq_timeout
:
std_logic_vector
(
9
downto
0
);
signal
tick_1ms
:
std_logic
;
signal
counter_1ms
:
unsigned
(
17
downto
0
);
signal
ts_offset
:
t_tdc_timestamp_array
(
4
downto
0
);
signal
reset_seq
:
std_logic_vector
(
4
downto
0
);
signal
ts_offset
:
t_tdc_timestamp_array
(
4
downto
0
);
signal
reset_seq
:
std_logic_vector
(
4
downto
0
);
signal
raw_enable
:
std_logic_vector
(
4
downto
0
);
function
f_wb_shift_address_word
(
w
:
t_wishbone_master_out
)
return
t_wishbone_master_out
is
...
...
@@ -292,6 +292,10 @@ architecture rtl of fmc_tdc_mezzanine is
return
r
;
end
f_wb_shift_address_word
;
signal
regs_ow_out
:
t_TDC_OW_out_registers
;
signal
regs_ow_in
:
t_TDC_OW_in_registers
;
--=================================================================================================
-- architecture begin
--=================================================================================================
...
...
@@ -380,9 +384,10 @@ begin
timestamp_ready_i
=>
tdc_timestamp_ready
,
raw_enable_i
=>
raw_enable
,
ts_offset_i
=>
ts_offset
,
reset_seq_i
=>
reset_seq
,
ts_offset_i
=>
ts_offset
,
reset_seq_i
=>
reset_seq
,
irq_threshold_o
=>
irq_threshold
,
irq_timeout_o
=>
irq_timeout
,
channel_enable_o
=>
channel_enable
...
...
@@ -390,34 +395,34 @@ begin
gen_use_fake_timestamps
:
if
g_use_fake_timestamps_for_sim
generate
gen_use_fake_timestamps
:
if
g_use_fake_timestamps_for_sim
generate
process
(
sim_timestamp_i
,
sim_timestamp_valid_i
)
begin
timestamp_valid
<=
(
others
=>
'0'
);
timestamp_valid
<=
(
others
=>
'0'
);
for
i
in
0
to
4
loop
if
unsigned
(
sim_timestamp_i
.
channel
)
=
i
then
timestamp
(
i
)
<=
sim_timestamp_i
;
timestamp_valid
(
i
)
<=
sim_timestamp_valid_i
;
timestamp
(
i
)
<=
sim_timestamp_i
;
timestamp_valid
(
i
)
<=
sim_timestamp_valid_i
;
end
if
;
end
loop
;
end
process
;
timestamp_ready
<=
(
others
=>
'1'
);
end
generate
gen_use_fake_timestamps
;
gen_use_real_timestamps
:
if
not
g_use_fake_timestamps_for_sim
generate
timestamp
<=
tdc_timestamp
;
timestamp_valid
<=
tdc_timestamp_valid
;
gen_use_real_timestamps
:
if
not
g_use_fake_timestamps_for_sim
generate
timestamp
<=
tdc_timestamp
;
timestamp_valid
<=
tdc_timestamp_valid
;
tdc_timestamp_ready
<=
timestamp_ready
;
end
generate
gen_use_real_timestamps
;
gen_fifos
:
for
i
in
0
to
4
generate
...
...
@@ -436,9 +441,9 @@ begin
irq_timeout_i
=>
irq_timeout
,
timestamp_i
=>
timestamp
,
timestamp_valid_i
=>
timestamp_stb
,
ts_offset_o
=>
ts_offset
(
i
),
reset_seq_o
=>
reset_seq
(
i
),
raw_enable_o
=>
raw_enable
(
i
));
ts_offset_o
=>
ts_offset
(
i
),
reset_seq_o
=>
reset_seq
(
i
),
raw_enable_o
=>
raw_enable
(
i
));
timestamp_stb
(
i
)
<=
timestamp_valid
(
i
)
and
timestamp_ready
(
i
);
end
generate
gen_fifos
;
...
...
@@ -450,7 +455,8 @@ begin
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
enable_i
=>
channel_enable
,
enable_i
=>
channel_enable
,
raw_mode_i
=>
raw_enable
,
ts_i
=>
timestamp
,
ts_valid_i
=>
timestamp_valid
,
ts_ready_o
=>
timestamp_ready
,
...
...
@@ -538,26 +544,15 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board UniqueID&Thermometer OneWire --
---------------------------------------------------------------------------------------------------
cmp_fmc_onewire
:
xwb_onewire_master
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_num_ports
=>
1
,
g_ow_btp_normal
=>
"5.0"
,
g_ow_btp_overdrive
=>
"1.0"
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_ONEWIRE
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_ONEWIRE
),
desc_o
=>
open
,
owr_pwren_o
=>
open
,
owr_en_o
=>
mezz_owr_en
,
owr_i
=>
mezz_owr_i
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
onewire_b
<=
'0'
when
mezz_owr_en
(
0
)
=
'1'
else
'Z'
;
mezz_owr_i
(
0
)
<=
onewire_b
;
U_Onewire
:
entity
work
.
tdc_onewire_wb
port
map
(
rst_n_i
=>
rst_sys_n_i
,
clk_sys_i
=>
clk_sys_i
,
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_ONEWIRE
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_ONEWIRE
),
regs_i
=>
regs_ow_in
,
regs_o
=>
regs_ow_out
);
---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
...
...
@@ -624,6 +619,19 @@ begin
i2c_scl_oen_o
<=
sys_scl_oe_n
;
i2c_scl_o
<=
sys_scl_out
;
U_OnewireIF
:
gc_ds182x_interface
generic
map
(
g_CLOCK_FREQ_KHZ
=>
62500
,
g_USE_INTERNAL_PPS
=>
true
)
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
pps_p_i
=>
'0'
,
onewire_b
=>
onewire_b
,
id_o
(
63
downto
32
)
=>
regs_ow_in
.
tdc_ow_id_h_i
,
id_o
(
31
downto
0
)
=>
regs_ow_in
.
tdc_ow_id_l_i
,
temper_o
=>
regs_ow_in
.
tdc_ow_temp_i
,
id_read_o
=>
regs_ow_in
.
tdc_ow_csr_valid_i
);
end
rtl
;
----------------------------------------------------------------------------------------------------
...
...
hdl/rtl/tdc_core_pkg.vhd
View file @
44e72646
...
...
@@ -61,15 +61,48 @@ use work.gencores_pkg.all;
package
tdc_core_pkg
is
type
t_raw_acam_timestamp
is
record
slope
:
std_logic
;
channel
:
std_logic_vector
(
2
downto
0
);
n_bins
:
std_logic_vector
(
16
downto
0
);
coarse
:
std_logic_vector
(
31
downto
0
);
tai
:
std_logic_vector
(
31
downto
0
);
seq
:
std_logic_vector
(
27
downto
0
);
seconds
:
std_logic_vector
(
31
downto
0
);
-- 32
acam_bins
:
std_logic_vector
(
16
downto
0
);
-- 32 + 17 = 49
acam_start_nb
:
std_logic_vector
(
7
downto
0
);
roll_over_incr_recent
:
std_logic
;
clk_i_cycles_offset
:
std_logic_vector
(
7
downto
0
);
-- 60 + 8 = 68
roll_over_nb
:
std_logic_vector
(
15
downto
0
);
-- 68 + 16 = 84
retrig_nb_offset
:
std_logic_vector
(
8
downto
0
);
-- 84 + 9 = 93
current_retrig_nb
:
std_logic_vector
(
8
downto
0
);
-- 93 + 9 = 102
channel
:
std_logic_vector
(
2
downto
0
);
-- 102 + 3 = 105
slope
:
std_logic
;
-- 105 + 1 = 106
seq
:
std_logic_vector
(
23
downto
0
);
-- 106 + 22 = 128
-- (raw mode data)
end
record
;
type
t_acam_timestamp
is
record
raw
:
t_raw_acam_timestamp
;
tai
:
std_logic_vector
(
31
downto
0
);
coarse
:
std_logic_vector
(
31
downto
0
);
n_bins
:
std_logic_vector
(
16
downto
0
);
channel
:
std_logic_vector
(
2
downto
0
);
slope
:
std_logic
;
meta
:
std_logic_vector
(
31
downto
0
);
end
record
;
constant
c_dummy_raw_acam_timestamp
:
t_raw_acam_timestamp
:
=
(
x"00000000"
,
"00000000000000000"
,
x"00"
,
'0'
,
x"00"
,
x"0000"
,
"000000000"
,
"000000000"
,
"000"
,
'0'
,
"000000000000000000000000"
);
type
t_tdc_timestamp
is
record
raw
:
t_raw_acam_timestamp
;
slope
:
std_logic
;
...
...
@@ -78,10 +111,11 @@ package tdc_core_pkg is
coarse
:
std_logic_vector
(
31
downto
0
);
tai
:
std_logic_vector
(
31
downto
0
);
seq
:
std_logic_vector
(
31
downto
0
);
meta
:
std_logic_vector
(
31
downto
0
);
end
record
;
constant
c_dummy_timestamp
:
t_tdc_timestamp
:
=
(
(
'0'
,
"000"
,
"00000000000000000"
,
x"00000000"
,
x"00000000"
,
x"0000000"
),
'0'
,
"000"
,
x"
000"
,
x"00000000"
,
x"00000000"
,
x"00000000"
);
(
c_dummy_raw_acam_timestamp
,
'0'
,
"000"
,
x"000"
,
x"00000
000"
,
x"00000000"
,
x"00000000"
,
x"00000000"
);
type
t_tdc_timestamp_array
is
array
(
integer
range
<>
)
of
t_tdc_timestamp
;
...
...
@@ -98,7 +132,7 @@ package tdc_core_pkg is
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Devices sdb description
constant
c_ONEWIRE_SDB_DEVICE
:
t_sdb_device
:
=
constant
c_
TDC_
ONEWIRE_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
...
...
@@ -109,10 +143,10 @@ package tdc_core_pkg is
addr_last
=>
x"0000000000000007"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"0000
0
602"
,
-- "WB-Onewire.Control " | md5sum | cut -c1-8
device_id
=>
x"0000
6
602"
,
-- "WB-Onewire.Control " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"201
21116
"
,
name
=>
"
WB-Onewire.Control
"
)));
date
=>
x"201
80910
"
,
name
=>
"
TDC-Onewire-Regs
"
)));
constant
c_SPEC_INFO_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
...
...
@@ -634,47 +668,6 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component
data_engine
generic
(
g_simulation
:
boolean
);
port
(
acam_ack_i
:
in
std_logic
;
acam_dat_i
:
in
std_logic_vector
(
31
downto
0
);
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_ef1_i
:
in
std_logic
;
acam_ef1_meta_i
:
in
std_logic
;
acam_ef2_i
:
in
std_logic
;
acam_ef2_meta_i
:
in
std_logic
;
activate_acq_p_i
:
in
std_logic
;
deactivate_acq_p_i
:
in
std_logic
;
acam_wr_config_p_i
:
in
std_logic
;
acam_rdbk_config_p_i
:
in
std_logic
;
acam_rdbk_status_p_i
:
in
std_logic
;
acam_rdbk_ififo1_p_i
:
in
std_logic
;
acam_rdbk_ififo2_p_i
:
in
std_logic
;
acam_rdbk_start01_p_i
:
in
std_logic
;
acam_rst_p_i
:
in
std_logic
;
acam_config_i
:
in
config_vector
;
start_from_fpga_i
:
in
std_logic
;
----------------------------------------------------------------------
state_active_p_o
:
out
std_logic
;
acam_adr_o
:
out
std_logic_vector
(
7
downto
0
);
acam_cyc_o
:
out
std_logic
;
acam_dat_o
:
out
std_logic_vector
(
31
downto
0
);
acam_stb_o
:
out
std_logic
;
acam_we_o
:
out
std_logic
;
acam_config_rdbk_o
:
out
config_vector
;
acam_ififo1_o
:
out
std_logic_vector
(
31
downto
0
);
acam_ififo2_o
:
out
std_logic_vector
(
31
downto
0
);
acam_start01_o
:
out
std_logic_vector
(
31
downto
0
);
acam_tstamp1_o
:
out
std_logic_vector
(
31
downto
0
);
acam_tstamp1_ok_p_o
:
out
std_logic
;
acam_tstamp2_o
:
out
std_logic_vector
(
31
downto
0
);
acam_tstamp2_ok_p_o
:
out
std_logic
);
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
reg_ctrl
is
...
...
@@ -851,28 +844,6 @@ package tdc_core_pkg is
end
component
carrier_info
;
---------------------------------------------------------------------------------------------------
component
leds_manager
is
generic
(
g_width
:
integer
:
=
32
;
g_simulation
:
boolean
:
=
FALSE
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
utc_p_i
:
in
std_logic
;
acam_inputs_en_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_channel_i
:
in
std_logic_vector
(
5
downto
0
);
tstamp_wr_p_i
:
in
std_logic
;
----------------------------------------------------------------------
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
);
----------------------------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
acam_databus_interface
...
...
@@ -974,6 +945,10 @@ package tdc_core_pkg is
function
f_pick
(
cond
:
boolean
;
if_true
:
std_logic_vector
;
if_false
:
std_logic_vector
)
return
std_logic_vector
;
function
f_pack_raw_acam_timestamp
(
ts
:
t_raw_acam_timestamp
)
return
std_logic_vector
;
end
tdc_core_pkg
;
...
...
@@ -990,7 +965,25 @@ package body tdc_core_pkg is
return
if_false
;
end
if
;
end
f_pick
;
function
f_pack_raw_acam_timestamp
(
ts
:
t_raw_acam_timestamp
)
return
std_logic_vector
is
variable
rv
:
std_logic_vector
(
127
downto
0
);
begin
rv
(
31
downto
0
)
:
=
ts
.
seconds
;
rv
(
48
downto
32
)
:
=
ts
.
acam_bins
(
16
downto
0
);
rv
(
56
downto
49
)
:
=
ts
.
acam_start_nb
;
rv
(
57
)
:
=
ts
.
roll_over_incr_recent
;
rv
(
65
downto
58
)
:
=
ts
.
clk_i_cycles_offset
;
rv
(
81
downto
66
)
:
=
ts
.
roll_over_nb
;
rv
(
90
downto
82
)
:
=
ts
.
retrig_nb_offset
;
rv
(
99
downto
91
)
:
=
ts
.
current_retrig_nb
;
rv
(
102
downto
100
)
:
=
ts
.
channel
;
rv
(
103
)
:
=
ts
.
slope
;
rv
(
127
downto
104
)
:
=
ts
.
seq
;
return
rv
;
end
f_pack_raw_acam_timestamp
;
end
tdc_core_pkg
;
--=================================================================================================
-- package end
...
...
hdl/rtl/tdc_onewire_wb.vhd
0 → 100644
View file @
44e72646
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC Onewire Master
---------------------------------------------------------------------------------------
-- File : tdc_onewire_wb.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_onewire_wb.wb
-- Created : Tue Sep 11 11:16:49 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_onewire_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
TDC_OW_wbgen2_pkg
.
all
;
entity
tdc_onewire_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
;
regs_i
:
in
t_TDC_OW_in_registers
;
regs_o
:
out
t_TDC_OW_out_registers
);
end
tdc_onewire_wb
;
architecture
syn
of
tdc_onewire_wb
is
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
wrdata_reg
<=
slave_i
.
dat
;
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
regs_o
.
tdc_ow_csr_valid_load_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
regs_o
.
tdc_ow_csr_valid_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
regs_o
.
tdc_ow_csr_valid_load_o
<=
'0'
;
end
if
;
else
if
((
slave_i
.
cyc
=
'1'
)
and
(
slave_i
.
stb
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
if
(
slave_i
.
we
=
'1'
)
then
regs_o
.
tdc_ow_csr_valid_load_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
regs_i
.
tdc_ow_csr_valid_i
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
if
(
slave_i
.
we
=
'1'
)
then
end
if
;
rddata_reg
(
15
downto
0
)
<=
regs_i
.
tdc_ow_temp_i
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
if
(
slave_i
.
we
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
tdc_ow_id_h_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11"
=>
if
(
slave_i
.
we
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
tdc_ow_id_l_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
slave_o
.
dat
<=
rddata_reg
;
-- Temperature & ID valid
regs_o
.
tdc_ow_csr_valid_o
<=
wrdata_reg
(
0
);
-- Temperature
-- Unique ID (32 highest bits)
-- Unique ID (32 lowest bits)
rwaddr_reg
<=
slave_i
.
adr
(
3
downto
2
);
slave_o
.
stall
<=
(
not
ack_sreg
(
0
))
and
(
slave_i
.
stb
and
slave_i
.
cyc
);
slave_o
.
err
<=
'0'
;
slave_o
.
rty
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o
.
ack
<=
ack_sreg
(
0
);
end
syn
;
hdl/rtl/tdc_onewire_wbgen2_pkg.vhd
0 → 100644
View file @
44e72646
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC Onewire Master
---------------------------------------------------------------------------------------
-- File : tdc_onewire_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_onewire_wb.wb
-- Created : Tue Sep 11 11:16:49 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_onewire_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
TDC_OW_wbgen2_pkg
is
-- Input registers (user design -> WB slave)
type
t_TDC_OW_in_registers
is
record
tdc_ow_csr_valid_i
:
std_logic
;
tdc_ow_temp_i
:
std_logic_vector
(
15
downto
0
);
tdc_ow_id_h_i
:
std_logic_vector
(
31
downto
0
);
tdc_ow_id_l_i
:
std_logic_vector
(
31
downto
0
);
end
record
;
constant
c_TDC_OW_in_registers_init_value
:
t_TDC_OW_in_registers
:
=
(
tdc_ow_csr_valid_i
=>
'0'
,
tdc_ow_temp_i
=>
(
others
=>
'0'
),
tdc_ow_id_h_i
=>
(
others
=>
'0'
),
tdc_ow_id_l_i
=>
(
others
=>
'0'
)
);
-- Output registers (WB slave -> user design)
type
t_TDC_OW_out_registers
is
record
tdc_ow_csr_valid_o
:
std_logic
;
tdc_ow_csr_valid_load_o
:
std_logic
;
end
record
;
constant
c_TDC_OW_out_registers_init_value
:
t_TDC_OW_out_registers
:
=
(
tdc_ow_csr_valid_o
=>
'0'
,
tdc_ow_csr_valid_load_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_TDC_OW_in_registers
)
return
t_TDC_OW_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
component
tdc_onewire_wb
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
;
regs_i
:
in
t_TDC_OW_in_registers
;
regs_o
:
out
t_TDC_OW_out_registers
);
end
component
;
end
package
;
package
body
TDC_OW_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
tmp
(
i
):
=
'0'
;
else
tmp
(
i
):
=
x
(
i
);
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_TDC_OW_in_registers
)
return
t_TDC_OW_in_registers
is
variable
tmp
:
t_TDC_OW_in_registers
;
begin
tmp
.
tdc_ow_csr_valid_i
:
=
f_x_to_zero
(
left
.
tdc_ow_csr_valid_i
)
or
f_x_to_zero
(
right
.
tdc_ow_csr_valid_i
);
tmp
.
tdc_ow_temp_i
:
=
f_x_to_zero
(
left
.
tdc_ow_temp_i
)
or
f_x_to_zero
(
right
.
tdc_ow_temp_i
);
tmp
.
tdc_ow_id_h_i
:
=
f_x_to_zero
(
left
.
tdc_ow_id_h_i
)
or
f_x_to_zero
(
right
.
tdc_ow_id_h_i
);
tmp
.
tdc_ow_id_l_i
:
=
f_x_to_zero
(
left
.
tdc_ow_id_l_i
)
or
f_x_to_zero
(
right
.
tdc_ow_id_l_i
);
return
tmp
;
end
function
;
end
package
body
;
hdl/rtl/wbgen/tdc_onewire_wb.wb
0 → 100644
View file @
44e72646
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "TDC Onewire Master";
prefix="TDC_OW";
hdl_entity="tdc_onewire_wb";
reg {
name = "Status Register";
prefix = "CSR";
field {
name = "Temperature & ID valid";
prefix = "VALID";
description = "read 1: the values in the TEMP, ID_H, ID_L registers contain a valid readout from the DS18xx chip";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Board Temperature";
prefix = "TEMP";
field {
name = "Temperature";
size = 16;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Board Unique ID (MSW)";
prefix = "ID_H";
field {
name = "Unique ID (32 highest bits)";
size = 32;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Board Unique ID (LSW)";
prefix = "ID_L";
field {
name = "Unique ID (32 lowest bits)";
size = 32;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
};
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