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FMC TDC 1ns 5cha - Gateware
Commit 227e4d01 authored by egousiou's avatar egousiou
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svec tdc slack issues solved 

git-svn-id: http://svn.ohwr.org/fmc-tdc@106 85dfdc96-de2c-444c-878d-45b388be74a9
parent d1bbe993
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hdl/spec/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise
View file @ 227e4d01
......@@ -23,9 +23,29 @@
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_circ_buff_v6_4.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7640980108902946276" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4819290180276573634" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6718039799359289506" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_1.gise
View file @ 227e4d01
......@@ -26,6 +26,27 @@
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_1.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="165936098113533828" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7071533197450788902" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="8814703242142704070" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_2.gise
View file @ 227e4d01
......@@ -26,6 +26,27 @@
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_2.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4883055629214282022" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="851143268618168456" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4914921300466099352" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/spec/src/ip_cores/mem_core/blk_mem_gen_v6_3.gise
View file @ 227e4d01
......@@ -26,6 +26,27 @@
<file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_3.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1373529468" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1373529468">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8846568913394521400" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5369246660214451990" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1373982765" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-197801769365351158" xil_pn:start_ts="1373982765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/svec/hdl/ip_cores/common/Manifest.py 0 → 100644
View file @ 227e4d01
files = [ "gencores_pkg.vhd",
"gc_crc_gen.vhd",
"gc_moving_average.vhd",
"gc_extend_pulse.vhd",
"gc_delay_gen.vhd",
"gc_dual_pi_controller.vhd",
"gc_reset.vhd",
"gc_serial_dac.vhd",
"gc_sync_ffs.vhd",
"gc_arbitrated_mux.vhd",
"gc_pulse_synchronizer.vhd",
"gc_frequency_meter.vhd",
"gc_dual_clock_ram.vhd",
"gc_wfifo.vhd"];
hdl/svec/hdl/ip_cores/common/gc_crc_gen.vhd
View file @ 227e4d01
......@@ -72,8 +72,7 @@ entity gc_crc_gen is
-- word when 0)
g_dual_width : integer range 0 to 1 := 0;
-- if true, match_o output is registered, otherwise it's driven combinatorially
g_registered_match_output : boolean := true;
g_registered_crc_output : boolean := true);
g_registered_match_output : boolean := true);
port (
clk_i : in std_logic; -- clock
rst_i : in std_logic; -- reset, active high
......@@ -81,8 +80,7 @@ entity gc_crc_gen is
half_i : in std_logic; -- 1: input word has g_half_width bits
-- 0: input word has g_data_width bits
data_i : in std_logic_vector(g_data_width - 1 downto 0); -- data input
restart_i : in std_logic := '0';
data_i : in std_logic_vector(g_data_width - 1 downto 0); -- data input
match_o : out std_logic; -- CRC match flag: 1 - CRC matches
......@@ -102,39 +100,32 @@ architecture rtl of gc_crc_gen is
return v_result;
end;
function f_reverse_bytes (a : in std_logic_vector)
return std_logic_vector is
variable tmp : std_logic_vector(a'length-1 downto 0);
variable v_result : std_logic_vector(a'length-1 downto 0);
begin
tmp := a;
for i in tmp'range loop
v_result(i) := tmp(((tmp'length/8-1) - i/8)*8 + (i mod 8));
end loop;
return v_result;
end;
constant msb : integer := g_polynomial'length - 1;
constant init_msb : integer := g_init_value'length - 1;
constant p : std_logic_vector(msb downto 0) := g_polynomial;
constant dw : integer := g_data_width;
constant pw : integer := g_polynomial'length;
type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
signal crca : fb_array;
signal da, ma : dmsb_array;
signal crc : std_logic_vector(msb downto 0);
signal arst, srst : std_logic;
signal data_i2 : std_logic_vector(g_data_width-1 downto 0);
signal en_d0 : std_logic;
signal crc_cur, crc_next : std_logic_vector(g_polynomial'length-1 downto 0);
constant msb : integer := g_polynomial'length - 1;
constant init_msb : integer := g_init_value'length - 1;
constant p : std_logic_vector(msb downto 0) := g_polynomial;
constant dw : integer := g_data_width;
constant pw : integer := g_polynomial'length;
type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
signal crca : fb_array;
signal da, ma : dmsb_array;
signal crc, zero : std_logic_vector(msb downto 0);
signal arst, srst : std_logic;
signal a, b : std_logic_vector(g_polynomial'length - 1 downto 0);
signal data_i2 : std_logic_vector(15 downto 0);
signal en_d0 : std_logic;
signal half_d0 : std_logic;
signal crc_tmp : std_logic_vector(31 downto 0);
signal crc_int : std_logic_vector(31 downto 0);
begin
a <= g_init_value;
b <= g_polynomial;
-- Parameter checking: Invalid generics will abort simulation/synthesis
PCHK1 : if msb /= init_msb generate
process
......@@ -163,9 +154,8 @@ begin
end process;
end generate PCHK3;
data_i2 <= f_reverse_bytes(data_i);
crc_cur <= g_init_value when restart_i = '1' else crc;
data_i2(15 downto 0) <= (data_i(7 downto 0) & data_i(15 downto 8));
-- data_i2(15 downto 0) <= f_reverse_vector(data_i(15 downto 0));
-- Generate vector of each data bit
CA : for i in 1 to dw generate -- data bits
......@@ -176,7 +166,7 @@ begin
-- Generate vector of each CRC MSB
MS0 : for i in 1 to msb generate
ma(1)(i) <= crc_cur(msb);
ma(1)(i) <= crc(msb);
end generate MS0;
MSP : for i in 2 to dw generate
MSU : for j in 1 to msb generate
......@@ -185,8 +175,8 @@ begin
end generate MSP;
-- Generate feedback matrix
crca(1)(0) <= da(1)(1) xor crc_cur(msb);
crca(1)(msb downto 1) <= crc_cur(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
crca(1)(0) <= da(1)(1) xor crc(msb);
crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
FB : for i in 2 to dw generate
crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb);
crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
......@@ -203,11 +193,18 @@ begin
arst <= rst_i;
end generate AR;
-- CRC process
crc_tmp <= f_reverse_vector(not crc);
crc_int <= crc_tmp(7 downto 0) & crc_tmp(15 downto 8) & crc_tmp(23 downto 16) & crc_tmp(31 downto 24);
zero <= (others => '0');
crc_o <= crc_int;
CRCP : process (clk_i, arst)
begin
if arst = '1' then -- async. reset
crc <= g_init_value;
half_d0 <= '0';
elsif rising_edge(clk_i) then
if srst = '1' then -- sync. reset
crc <= g_init_value;
......@@ -222,30 +219,6 @@ begin
end if;
end process;
p_crc_next : process(crc, half_i, crca)
begin
if(g_registered_crc_output) then
crc_next <= f_reverse_bytes(f_reverse_vector(not crc));
else
if(half_i = '1' and g_dual_width = 1) then
crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_half_width)));
else
crc_next <= f_reverse_bytes(f_reverse_vector(not crca(g_data_width)));
end if;
end if;
end process;
p_crc_output : process(crc_next, crc, en_i)
begin
if(g_registered_crc_output) then
crc_o <= crc_next;
elsif(en_i = '1') then
crc_o <= crc_next;
else
crc_o <= f_reverse_bytes(f_reverse_vector(not crc));
end if;
end process;
gen_reg_match_output : if(g_registered_match_output) generate
match_gen : process (clk_i, arst)
......@@ -261,7 +234,7 @@ begin
en_d0 <= en_i;
if(en_d0 = '1') then
if crc_next = g_residue then
if crc_int = g_residue then
match_o <= '1';
else
match_o <= '0';
......@@ -274,7 +247,7 @@ begin
end generate gen_reg_match_output;
gen_comb_match_output : if (not g_registered_match_output) generate
match_o <= '1' when crc_next = g_residue else '0';
match_o <= '1' when crc_int = g_residue else '0';
end generate gen_comb_match_output;
end rtl;
hdl/svec/hdl/ip_cores/common/gc_dual_clock_ram.vhd 0 → 100644
View file @ 227e4d01
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Read during write has an undefined result
entity gc_dual_clock_ram is
generic(
addr_width : natural := 4;
data_width : natural := 32);
port(
-- write port
w_clk_i : in std_logic;
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(addr_width-1 downto 0);
w_data_i : in std_logic_vector(data_width-1 downto 0);
-- read port
r_clk_i : in std_logic;
r_en_i : in std_logic;
r_addr_i : in std_logic_vector(addr_width-1 downto 0);
r_data_o : out std_logic_vector(data_width-1 downto 0));
end gc_dual_clock_ram;
architecture rtl of gc_dual_clock_ram is
type ram_t is array(2**addr_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal ram : ram_t := (others => (others => '0'));
-- Tell synthesizer we do not care about read during write behaviour
attribute ramstyle : string;
attribute ramstyle of ram : signal is "no_rw_check";
begin
write : process(w_clk_i)
begin
if rising_edge(w_clk_i) then
if w_en_i = '1' then
ram(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
end if;
end process;
read : process(r_clk_i)
begin
if rising_edge(r_clk_i) then
if r_en_i = '1' then
r_data_o <= ram(to_integer(unsigned(r_addr_i)));
end if;
end if;
end process;
end rtl;
hdl/svec/hdl/ip_cores/common/gc_extend_pulse.vhd
View file @ 227e4d01
......@@ -46,7 +46,6 @@ use ieee.NUMERIC_STD.all;
library work;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity gc_extend_pulse is
......@@ -65,7 +64,7 @@ end gc_extend_pulse;
architecture rtl of gc_extend_pulse is
signal cntr : unsigned(f_log2_size(g_width)-1 downto 0);
signal cntr : unsigned(31 downto 0);
signal extended_int : std_logic;
begin -- rtl
......
hdl/svec/hdl/ip_cores/common/gc_sync_ffs.vhd
View file @ 227e4d01
......@@ -58,11 +58,6 @@ end gc_sync_ffs;
architecture behavioral of gc_sync_ffs is
signal sync0, sync1, sync2 : std_logic;
attribute shreg_extract : string;
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute shreg_extract of sync2 : signal is "no";
begin
......
hdl/svec/hdl/ip_cores/common/gc_wfifo.vhd
View file @ 227e4d01
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity gc_wfifo is
generic(
......@@ -34,10 +31,6 @@ entity gc_wfifo is
end gc_wfifo;
architecture rtl of gc_wfifo is
-- Quartus 11 sometimes goes crazy and infers an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
subtype counter is unsigned(addr_width downto 0);
type counter_shift is array(sync_depth downto 0) of counter;
......@@ -52,7 +45,11 @@ architecture rtl of gc_wfifo is
signal r_idx_shift_a : counter_shift; -- r_idx_gray in a_clk
signal w_idx_shift_r : counter_shift; -- w_idx_gray in r_clk
signal qb : std_logic_vector(data_width-1 downto 0);
attribute altera_attribute : string;
-- Quartus 11 sometimes goes crazy and infers an altshift_taps! Stop it.
attribute altera_attribute of r_idx_shift_w : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
attribute altera_attribute of r_idx_shift_a : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
attribute altera_attribute of w_idx_shift_r : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
function bin2gray(a : unsigned) return unsigned is
variable o : unsigned(a'length downto 0);
......@@ -97,41 +94,25 @@ architecture rtl of gc_wfifo is
end if;
end full;
begin
ram : generic_simple_dpram
generic map(
g_data_width => data_width,
g_size => 2**addr_width,
g_addr_conflict_resolution => "dont_care",
g_dual_clock => gray_code)
port map(
clka_i => w_clk_i,
wea_i => w_en_i,
aa_i => index(w_idx_bnry),
da_i => w_data_i,
clkb_i => r_clk_i,
ab_i => index(r_idx_bnry),
qb_o => qb);
ram : gc_dual_clock_ram
generic map(addr_width => addr_width, data_width => data_width)
port map(w_clk_i => w_clk_i, w_en_i => w_en_i, w_addr_i => index(w_idx_bnry), w_data_i => w_data_i,
r_clk_i => r_clk_i, r_en_i => r_en_i, r_addr_i => index(r_idx_bnry), r_data_o => r_data_o);
read : process(r_clk_i)
variable idx : counter;
begin
if rising_edge(r_clk_i) then
if r_rst_n_i = '0' then
idx := (others => '0');
r_data_o <= qb;
elsif r_en_i = '1' then
idx := r_idx_bnry + 1;
r_data_o <= qb;
else
idx := r_idx_bnry;
--r_data_o <= r_data_o; --implied
end if;
r_idx_bnry <= idx;
r_idx_gray <= bin2gray(idx);
if sync_depth > 0 then
w_idx_shift_r(sync_depth downto 1) <= w_idx_shift_r(sync_depth-1 downto 0);
end if;
w_idx_shift_r(sync_depth downto 1) <= w_idx_shift_r(sync_depth-1 downto 0);
end if;
end process;
w_idx_shift_r(0) <= w_idx_gray;
......@@ -150,9 +131,7 @@ begin
end if;
w_idx_bnry <= idx;
w_idx_gray <= bin2gray(idx);
if sync_depth > 0 then
r_idx_shift_w(sync_depth downto 1) <= r_idx_shift_w(sync_depth-1 downto 0);
end if;
r_idx_shift_w(sync_depth downto 1) <= r_idx_shift_w(sync_depth-1 downto 0);
end if;
end process;
r_idx_shift_w(0) <= r_idx_gray;
......@@ -171,12 +150,9 @@ begin
end if;
a_idx_bnry <= idx;
a_idx_gray <= bin2gray(idx);
if sync_depth > 0 then
r_idx_shift_a(sync_depth downto 1) <= r_idx_shift_a(sync_depth-1 downto 0);
end if;
r_idx_shift_a(sync_depth downto 1) <= r_idx_shift_a(sync_depth-1 downto 0);
end if;
end process;
r_idx_shift_a(0) <= r_idx_gray;
a_rdy_o <= not full(a_idx_gray, r_idx_shift_a(sync_depth));
end rtl;
hdl/svec/hdl/ip_cores/common/gencores_pkg.vhd
View file @ 227e4d01
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2009-09-01
-- Last update: 2012-10-04
-- Last update: 2012-03-12
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -68,17 +68,15 @@ package gencores_pkg is
g_half_width : integer range 2 to 256 := 8;
g_sync_reset : integer range 0 to 1 := 1;
g_dual_width : integer range 0 to 1 := 0;
g_registered_match_output : boolean := true;
g_registered_crc_output : boolean := true);
g_registered_match_output : boolean := true);
port (
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
half_i : in std_logic;
restart_i : in std_logic := '0';
data_i : in std_logic_vector(g_data_width - 1 downto 0);
match_o : out std_logic;
crc_o : out std_logic_vector(g_polynomial'length - 1 downto 0));
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
half_i : in std_logic;
data_i : in std_logic_vector(g_data_width - 1 downto 0);
match_o : out std_logic;
crc_o : out std_logic_vector(g_polynomial'length - 1 downto 0));
end component;
component gc_moving_average
......@@ -190,7 +188,25 @@ package gencores_pkg is
q_valid_o : out std_logic;
q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0));
end component;
-- Read during write has an undefined result
component gc_dual_clock_ram is
generic(
addr_width : natural := 4;
data_width : natural := 32);
port(
-- write port
w_clk_i : in std_logic;
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(addr_width-1 downto 0);
w_data_i : in std_logic_vector(data_width-1 downto 0);
-- read port
r_clk_i : in std_logic;
r_en_i : in std_logic;
r_addr_i : in std_logic_vector(addr_width-1 downto 0);
r_data_o : out std_logic_vector(data_width-1 downto 0));
end component;
-- A 'Wes' FIFO. Generic FIFO using inferred memory.
-- Supports clock domain crossing
-- Should be safe from fast->slow or reversed
......@@ -235,33 +251,6 @@ package gencores_pkg is
rstn_o : out std_logic_vector(g_clocks-1 downto 0));
end component;
component gc_rr_arbiter
generic (
g_size : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
req_i : in std_logic_vector(g_size-1 downto 0);
grant_o : out std_logic_vector(g_size-1 downto 0);
grant_comb_o : out std_logic_vector(g_size-1 downto 0));
end component;
component gc_word_packer
generic (
g_input_width : integer;
g_output_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_input_width-1 downto 0);
d_valid_i : in std_logic;
d_req_o : out std_logic;
flush_i : in std_logic := '0';
q_o : out std_logic_vector(g_output_width-1 downto 0);
q_valid_o : out std_logic;
q_req_i : in std_logic);
end component;
procedure f_rr_arbitrate (
signal req : in std_logic_vector;
signal pre_grant : in std_logic_vector;
......
hdl/svec/hdl/ip_cores/genrams/.gitignore 0 → 100644
View file @ 227e4d01
coregen_ip
\ No newline at end of file
hdl/svec/hdl/ip_cores/genrams/Manifest.py 0 → 100644
View file @ 227e4d01
#############################
## Xilinx Coregen stuff
#############################
import os as __os
import shutil as __shutil
files = ["genram_pkg.vhd", "memory_loader_pkg.vhd", "generic_shiftreg_fifo.vhd"]
def __copy_vhdls(cg_dir, dest_dir):
f = open(cg_dir+"/analyze_order.txt","r")
text = f.readlines();
f.close()
flist = [];
for fname in text:
f = fname.rstrip('\n')
__shutil.copy(cg_dir+"/"+f, dest_dir)
flist.append(f.split('/').pop())
return flist
def __import_coregen_module(path, name, work_dir):
__os.mkdir(work_dir+"/"+name);
flist = __copy_vhdls(path+"/"+name, work_dir+"/"+name)
f=open(work_dir+"/"+name+"/Manifest.py","w")
f.write("files = [\n")
first=True
for fname in flist:
if not first:
f.write(",\n")
else:
first = False
f.write("\""+fname+"\"")
f.write("]\n");
f.write("library = \"" + name + "\"\n")
f.close()
def __import_coregen_files():
xilinx_dir = __os.getenv("XILINX");
if xilinx_dir == None:
print("[genrams] FATAL ERROR: XILINX environment variable not set. It must provide the path to ISE_DS directory in ISE installation folder (follow Xilinx instructions).")
__os.exit(-1)
coregen_path = xilinx_dir + "/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/"
if not __os.path.isdir(coregen_path):
print("[genrams]: FATAL ERROR: XILINX environment variable seems to be set incorrectly. It must point to ISE_DS directory in the ISE installation folder. For example: XILINX=/opt/Xilinx/ISE_DS")
__os.exit(-1)
work_dir = __manifest + "/coregen_ip";
if __os.path.isdir(work_dir):
return
print("[genrams] creating workdir " + work_dir)
__os.mkdir(work_dir);
print("[genrams] copying ISE files...")
__import_coregen_module(coregen_path, "blk_mem_gen_v4_1", work_dir);
__import_coregen_module(coregen_path, "fifo_generator_v6_1", work_dir);
##############################
## "Normal" manifest ##
##############################
#print ("[genrams] action = " + action + ", target = " + target, ", syn_device = ", syn_device[0:4].upper())
if (target == "altera"):
modules = {"local" : "altera"}
elif (target == "xilinx" and action == "synthesis" and syn_device[0:4].upper()=="XC6S"):
__import_coregen_files()
modules = {"local" : ["xilinx", "xilinx/spartan6", "coregen_ip/blk_mem_gen_v4_1", "coregen_ip/fifo_generator_v6_1"]}
elif (target == "xilinx" and action == "synthesis" and syn_device[0:4].upper()=="XC6V"):
__import_coregen_files()
modules = {"local" : ["xilinx", "xilinx/virtex6", "coregen_ip/blk_mem_gen_v4_1", "coregen_ip/fifo_generator_v6_1"]}
elif (target == "xilinx" and action == "simulation"):
modules = {"local" : ["xilinx", "xilinx/spartan6", "xilinx/sim_stub"]}
else:
modules = {"local" : "altera"}
hdl/svec/hdl/ip_cores/genrams/generic_shiftreg_fifo.vhd
View file @ 227e4d01
......@@ -72,20 +72,13 @@ end generic_shiftreg_fifo;
architecture rtl of generic_shiftreg_fifo is
component gc_shiftreg
generic (
g_size : integer);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
signal pointer : integer range 0 to g_size-1 := 0;
signal srl_addr : std_logic_vector(f_log2_size(g_size)-1 downto 0) := (others => '0');
constant c_srl_length : integer := g_size; -- set to srl 'type' 16 or 32 bit length
type t_srl_array is array (c_srl_length - 1 downto 0) of std_logic_vector (g_data_width - 1 downto 0);
signal fifo_store : t_srl_array;
signal pointer : integer range 0 to c_srl_length - 1;
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal pointer_almost_full : std_logic;
......@@ -99,20 +92,21 @@ begin
do_write <= '1' when (rd_i = '1' and we_i = '1')
or (we_i = '1' and pointer_full = '0') else '0';
-- data store SRL's
p_data_srl : process(clk_i)
begin
if rising_edge(clk_i) then
-- if rst_n_i = '0'then
-- for i in 0 to c_srl_length-1 loop
-- fifo_store(i) <= (others => '0');
-- end loop; -- i
if do_write = '1' then
fifo_store <= fifo_store(fifo_store'left - 1 downto 0) & d_i;
end if;
end if;
end process;
gen_sregs : for i in 0 to g_data_width-1 generate
U_SRLx : gc_shiftreg
generic map (
g_size => g_size)
port map (
clk_i => clk_i,
en_i => do_write,
d_i => d_i(i),
q_o => q_o(i),
a_i => srl_addr);
end generate gen_sregs;
srl_addr <= std_logic_vector(to_unsigned(pointer, srl_addr'length));
q_o <= fifo_store(pointer);
p_empty_logic : process(clk_i)
begin
......@@ -143,9 +137,7 @@ begin
p_gen_address : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pointer <= 0;
elsif valid_count = '1' then
if valid_count = '1' then
if we_i = '1' then
pointer <= pointer + 1;
else
......@@ -156,9 +148,9 @@ begin
end process;
-- Detect when pointer is zero and maximum
pointer_zero <= '1' when pointer = 0 else '0';
pointer_full <= '1' when pointer = g_size - 1 else '0';
pointer_almost_full <= '1' when pointer_full = '1' or pointer = g_size - 2 else '0';
pointer_zero <= '1' when pointer = 0 else '0';
pointer_full <= '1' when pointer = c_srl_length - 1 else '0';
pointer_almost_full <= '1' when pointer_full = '1' or pointer = c_srl_length - 2 else '0';
-- assign internal signals to outputs
......
hdl/svec/hdl/ip_cores/genrams/genram_pkg.vhd
View file @ 227e4d01
......@@ -46,14 +46,18 @@ package genram_pkg is
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
-- Generic RAM initialized with nothing.
constant c_generic_ram_nothing : t_generic_ram_init(-1 downto 0, -1 downto 0) :=
(others => (others => '0'));
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "none";
g_addr_conflict_resolution : string := "dont_care") ;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -64,33 +68,14 @@ package genram_pkg is
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_simple_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width -1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width -1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
......
hdl/svec/hdl/ip_cores/genrams/memory_loader_pkg.vhd
View file @ 227e4d01
......@@ -147,15 +147,14 @@ package body memory_loader_pkg is
variable data_tmp : unsigned(mem_width-1 downto 0);
variable data_int : integer;
begin
if(file_name = "" or file_name = "none") then
if(file_name = "") then
mem := (others => (others => '0'));
return mem;
end if;
file_open(status, f_in, file_name, read_mode);
if(status = open_ok) then
else
if(status /= open_ok) then
if(fail_if_notfound) then
report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
else
......@@ -203,4 +202,4 @@ package body memory_loader_pkg is
end memory_loader_pkg;
\ No newline at end of file
end memory_loader_pkg;
hdl/svec/hdl/ip_cores/genrams/xilinx/Manifest.py 0 → 100644
View file @ 227e4d01
files = [
"generic_dpram.vhd",
"generic_dpram_sameclock.vhd",
"generic_dpram_dualclock.vhd",
"generic_spram.vhd"
]
hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram.vhd
View file @ 227e4d01
......@@ -46,6 +46,7 @@ entity generic_dpram is
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
);
......@@ -83,6 +84,7 @@ architecture syn of generic_dpram is
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_init_value : t_generic_ram_init;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
......@@ -106,6 +108,7 @@ architecture syn of generic_dpram is
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_init_value : t_generic_ram_init;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
......@@ -133,6 +136,7 @@ begin
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_init_value => g_init_value,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
......@@ -159,6 +163,7 @@ begin
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_init_value => g_init_value,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
......
hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd
View file @ 227e4d01
......@@ -45,6 +45,7 @@ entity generic_dpram_dualclock is
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_fail_if_file_not_found : boolean := true
);
......@@ -100,7 +101,11 @@ architecture syn of generic_dpram_dualclock is
function f_file_contents return t_meminit_array is
begin
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
if g_init_value'length > 0 then
return g_init_value;
else
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end if;
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
......@@ -123,8 +128,7 @@ begin
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
process (clka_i)
......@@ -160,8 +164,7 @@ begin
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
process(clka_i)
begin
......
hdl/svec/hdl/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd
View file @ 227e4d01
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-09
-- Last update: 2012-03-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -44,6 +44,7 @@ entity generic_dpram_sameclock is
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_fail_if_file_not_found : boolean := true
);
......@@ -99,9 +100,13 @@ architecture syn of generic_dpram_sameclock is
function f_file_contents return t_meminit_array is
begin
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
if g_init_value'length > 0 then
return g_init_value;
else
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end if;
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
......@@ -112,17 +117,6 @@ architecture syn of generic_dpram_sameclock is
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
function f_check_bounds(x : integer; minx : integer; maxx : integer) return integer is
begin
if(x < minx) then
return minx;
elsif(x > maxx) then
return maxx;
else
return x;
end if;
end f_check_bounds;
begin
wea_rep <= (others => wea_i);
......@@ -131,20 +125,19 @@ begin
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
process (clk_i)
begin
if rising_edge(clk_i) then
qa_o <= ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1));
qb_o <= ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1));
qa_o <= ram(to_integer(unsigned(aa_i)));
qb_o <= ram(to_integer(unsigned(ab_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(f_check_bounds(to_integer(unsigned(aa_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
if(s_we_b(i) = '1') then
ram(f_check_bounds(to_integer(unsigned(ab_i)), 0, g_size-1))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
......@@ -154,8 +147,7 @@ begin
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
process(clk_i)
begin
......
hdl/svec/hdl/ip_cores/genrams/xilinx/generic_spram.vhd
View file @ 227e4d01
......@@ -86,9 +86,7 @@ architecture syn of generic_spram is
begin
assert (g_init_file = "" or g_init_file = "none")
report "generic_spram: Memory initialization files not supported yet. Sorry :("
severity failure;
assert (g_init_file = "") report "generic_spram: Memory initialization files not supported yet. Sorry :(" severity failure;
gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "write_first") generate
......@@ -117,8 +115,7 @@ begin
end generate gen_with_byte_enable_writefirst;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
......@@ -158,8 +155,7 @@ begin
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
process(clk_i)
begin
......
hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/Manifest.py 0 → 100644
View file @ 227e4d01
files = ["dummy.vhd"]
library = "fifo_generator_v6_1"
\ No newline at end of file
hdl/svec/hdl/ip_cores/genrams/xilinx/sim_stub/dummy.vhd 0 → 100644
View file @ 227e4d01
entity xilinx_dummy_sim is
end xilinx_dummy_sim;
\ No newline at end of file
hdl/svec/hdl/ip_cores/genrams/xilinx/spartan6/Manifest.py 0 → 100644
View file @ 227e4d01
files =["generic_async_fifo.vhd", "generic_sync_fifo.vhd"];
\ No newline at end of file
hdl/svec/hdl/ip_cores/genrams/xilinx/virtex6/Manifest.py 0 → 100644
View file @ 227e4d01
files =["generic_async_fifo.vhd", "generic_sync_fifo.vhd"];
\ No newline at end of file
hdl/svec/hdl/ip_cores/wishbone/Manifest.py 0 → 100644
View file @ 227e4d01
def __helper():
dirs = [
"wb_async_bridge",
"wb_onewire_master",
"wb_i2c_master",
"wb_bus_fanout",
"wb_dpram",
"wb_gpio_port",
"wb_simple_timer",
"wb_uart",
"wb_vic",
"wb_spi",
"wb_crossbar",
"wb_lm32",
"wb_slave_adapter",
"wb_xilinx_fpga_loader",
"wb_clock_crossing",
"wb_dma",
"wb_serial_lcd",
"wb_simple_pwm",
"wbgen2"
]
if (target == "altera"): dirs.extend(["wb_pcie"]);
return dirs
modules = { "local" : __helper() };
files = ["wishbone_pkg.vhd"];
hdl/svec/hdl/ip_cores/wishbone/wb_crossbar/Manifest.py 0 → 100644
View file @ 227e4d01
files = [
"sdb_rom.vhd",
"xwb_crossbar.vhd",
"xwb_sdb_crossbar.vhd" ];
hdl/svec/hdl/ip_cores/wishbone/wb_i2c_master/Manifest.py 0 → 100644
View file @ 227e4d01
files= ["i2c_master_bit_ctrl.vhd",
"i2c_master_byte_ctrl.vhd",
"i2c_master_top.vhd",
"wb_i2c_master.vhd",
"xwb_i2c_master.vhd"];
hdl/svec/hdl/ip_cores/wishbone/wb_onewire_master/Manifest.py 0 → 100644
View file @ 227e4d01
files = ["wb_onewire_master.vhd",
"xwb_onewire_master.vhd",
"sockit_owm.v"];
hdl/svec/hdl/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
View file @ 227e4d01
......@@ -116,7 +116,7 @@ begin -- rtl
sl_stall_o <= slave_out.stall;
sl_dat_o <= slave_out.dat;
sl_int_o <= slave_out.int;
gen_master_use_struct : if (g_master_use_struct) generate
master_in <= master_i;
......@@ -133,12 +133,6 @@ begin -- rtl
end generate gen_master_use_slv;
master_o <= master_out;
ma_adr_o <= master_out.adr;
ma_dat_o <= master_out.dat;
ma_sel_o <= master_out.sel;
ma_cyc_o <= master_out.cyc;
ma_stb_o <= master_out.stb;
ma_we_o <= master_out.we;
p_gen_address : process(slave_in, master_out)
begin
......
hdl/svec/hdl/ip_cores/wishbone/wb_spi/Manifest.py 0 → 100644
View file @ 227e4d01
files = [ "spi_clgen.v",
"spi_shift.v",
"spi_top.v",
"wb_spi.vhd",
"xwb_spi.vhd" ];
hdl/svec/hdl/rtl/acam_databus_interface.vhd
View file @ 227e4d01
......@@ -14,8 +14,8 @@
-- |
-- Description The unit interfaces with the ACAM chip pins for the configuration of the registers|
-- and the aquisition of the timestamps. |
-- The ACAM proprietary interface is converted to a WISHBONE classic interface, |
-- through which the unit communicates with the data_engine unit. |
-- The ACAM proprietary interface is converted to a WISHBONE classic interface, with |
-- which the unit communicates with the data_engine unit. |
-- The WISHBONE master is implemented in the data_engine and the slave in this unit. |
-- |
-- ___________ ____________ ___________ |
......@@ -78,13 +78,13 @@ entity acam_databus_interface is
port
-- INPUTS
-- Signals from the clks_rsts_manager unit
-- Signals from the clk_rst_manager unit
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- global reset, synched to clk_i
rst_i : in std_logic; -- global reset
-- Signals from the ACAM chip
ef1_i : in std_logic; -- FIFO1 empty flag
ef2_i : in std_logic; -- FIFO2 empty flag
ef2_i : in std_logic; -- FIFO1 empty flag
data_bus_io : inout std_logic_vector(27 downto 0);
......@@ -92,27 +92,27 @@ entity acam_databus_interface is
cyc_i : in std_logic; -- WISHBONE cycle
stb_i : in std_logic; -- WISHBONE strobe
we_i : in std_logic; -- WISHBONE write enable
adr_i : in std_logic_vector(7 downto 0); -- address of ACAM to write to/ read from (only 4 LSB are output)
dat_i : in std_logic_vector(31 downto 0); -- data to load to ACAM (only 28 LSB are output)
adr_i : in std_logic_vector(7 downto 0); -- address of Acam to write to/ read from (only 4 LSB are output)
dat_i : in std_logic_vector(31 downto 0); -- data to load to Acam (only 28 LSB are output)
-- OUTPUTS
-- signals internal to the chip: interface with other modules
ef1_o : out std_logic; -- ACAM FIFO1 empty flag (bouble registered with clk_i)
ef1_synch1_o : out std_logic; -- ACAM FIFO1 empty flag (after 1 clk_i register)
ef2_o : out std_logic; -- ACAM FIFO2 empty flag (bouble registered with clk_i)
ef2_synch1_o : out std_logic; -- ACAM FIFO2 empty flag (after 1 clk_i register)
ef1_o : out std_logic; -- acam FIFO1 empty flag (bouble registered with clk_i)
ef1_synch1_o : out std_logic; -- acam FIFO1 empty flag (after 1 clk_i register)
ef2_o : out std_logic; -- acam FIFO2 empty flag (bouble registered with clk_i)
ef2_synch1_o : out std_logic; -- acam FIFO2 empty flag (after 1 clk_i register)
-- Signals to ACAM interface
adr_o : out std_logic_vector(3 downto 0); -- ACAM address
cs_n_o : out std_logic; -- ACAM chip select, active low
oe_n_o : out std_logic; -- ACAM output enble, active low
rd_n_o : out std_logic; -- ACAM read enable, active low
wr_n_o : out std_logic; -- ACAM write enable, active low
adr_o : out std_logic_vector(3 downto 0); -- acam address
cs_n_o : out std_logic; -- acam chip select, active low
oe_n_o : out std_logic; -- acam output enble, active low
rd_n_o : out std_logic; -- acam read enable, active low
wr_n_o : out std_logic; -- acam write enable, active low
-- Signals to the data_engine unit
ack_o : out std_logic; -- WISHBONE ack
dat_o : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & 0 & 0 & 28 bits ACAM data_bus_io
dat_o : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & 0 & 0 & 28 bits acam data_bus_io
end acam_databus_interface;
......@@ -320,7 +320,7 @@ output_registers: process (clk_i)
cs <= ((stb_i and cyc_i) or cs_extend) and not(ack);
rd <= ((stb_i and cyc_i and not(we_i)) or rd_extend) and not(ack);
wr <= ((stb_i and cyc_i and we_i) or wr_extend) and not(wr_remove) and not(ack);
-- the wr signal has to be removed to respect the ACAM specs
-- the wr signal has to be removed to respect the Acam specs
data_bus_io <= dat_i(27 downto 0) when we_i='1' else (others =>'Z');
adr_o <= adr_i(3 downto 0);
......
hdl/svec/hdl/rtl/acam_timecontrol_interface.vhd
View file @ 227e4d01
......@@ -12,30 +12,7 @@
---------------------------------------------------------------------------------------------------
-- File acam_timecontrol_interface.vhd |
-- |
-- Description Interface with the ACAM chip pins for the timing issues. |
-- o The unit is responsible for delivering to the ACAM, the Start pulse, upon the |
-- activation-of-the-aquisition command (activate_acq_p_i) coming through the |
-- Control Register bit 0, from the PCIe/VME interface. |
-- All ACAM timestamps will be referring to this Start pulse (a timestamp is the |
-- time difference between this pulse and a pulse arriving to any of the channels).|
-- Since though in this application we are only interested in calculating timestamp|
-- differences, the exact arrival of this Start pulse is not actually significant. |
-- Note that the timestamps subtraction takes place on the software level of this |
-- TDC application. |
-- Start : ______|-|_______________________________________________________ |
-- Stop Ch1 : _______________|-|______________________________________________ |
-- Stop Ch2 : _________________________________|-|____________________________ |
-- ACAM tstamp1: <--------> |
-- ACAM tstamp2: <-------------------------> |
-- Tstamps diff: <---------------->
-- o The unit is also receiving the ACAM signal int_flag_i, which is following |
-- the ACAM Start# MSB (configuration set through the ACAM register 12); |
-- it makes it synchronous to the clk_i and makes it availabe to the |
-- start_retrig_ctrl unit. |
-- o Finally, the unit is receiving the the ACAM signal err_flag_i, which is |
-- following the ACAM Full Flags of the Hit FIFOs(configuration set through the |
-- ACAM register 11); it detects a rising edge and makes it available to the |
-- irq_generator unit. |
-- Description interface with the acam chip pins for control and timing |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
......@@ -85,31 +62,28 @@ use work.tdc_core_pkg.all; -- definitions of types, constants, entities
entity acam_timecontrol_interface is
port
-- INPUTS
-- Signals from the clks_rsts_manager unit
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- global reset, synched to clk_i
acam_refclk_r_edge_p_i : in std_logic; -- pulse upon ACAM RefClk rising edge
-- Signals from the clk_rst_manager unit
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- reset
acam_refclk_r_edge_p_i : in std_logic; -- pulse upon ACAM RefClk rising edge
-- Signals from the ACAM chip
int_flag_i : in std_logic; -- ACAM interrupt flag, active HIGH; through ACAM config
-- reg 12 it is set to the MSB of Start#
err_flag_i : in std_logic; -- ACAM error flag, active HIGH; through ACAM config
-- reg 11 is set to report for any HitFIFOs full flags
err_flag_i : in std_logic; -- ACAM error flag, active HIGH; through ACAM config
-- reg 11 is set to report for any HitFIFOs full flags
int_flag_i : in std_logic; -- ACAM interrupt flag, active HIGH; through ACAM config
-- reg 12 it is set to the MSB of Start#
-- Signals from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- signal from PCIe/VME to send the Start pulse
-- and to start retrieving the ACAM timestamps
window_delay_i : in std_logic_vector(31 downto 0); -- eva: think not used
activate_acq_p_i : in std_logic; -- signal from PCIe to start following the ACAM chip
-- for tstamps aquisition
window_delay_i : in std_logic_vector(31 downto 0); -- eva: don t know yet:s
-- OUTPUTS
-- Signals to the ACAM chip
start_from_fpga_o : out std_logic; -- Start pulse, to which all timestamps will be refering to;
-- note though that in this application we are only interested
-- in time differences, therefore the exact arrival of this
-- pulse is not significant.
start_from_fpga_o : out std_logic;
-- Signals to the start_retrig_ctrl unit
-- Signals to the
acam_errflag_r_edge_p_o : out std_logic; -- ACAM ErrFlag rising edge
acam_errflag_f_edge_p_o : out std_logic; -- ACAM ErrFlag falling edge
acam_intflag_f_edge_p_o : out std_logic);-- ACAM IntFlag falling edge
......@@ -168,9 +142,8 @@ begin
acam_intflag_f_edge_p_o <= not(int_flag_synch(1)) and int_flag_synch(0);
---------------------------------------------------------------------------------------------------
-- Start Pulse Generation --
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
-- Generation of the start pulse and the enable window:
-- the start pulse originates from an internal signal at the same time, the StartDis is de-asserted.
......@@ -209,8 +182,8 @@ begin
total_delay <= std_logic_vector(unsigned(window_delay_i)+constant_delay);
start_pulse_from_fpga: process (clk_i) -- start pulse in the middle of the
begin -- de-assertion window of StartDisable
start_pulse_from_fpga: process (clk_i) -- start pulse in the middle of the
begin -- de-assertion window of StartDisable
if rising_edge (clk_i) then
if rst_i ='1' then
start_from_fpga_o <= '0';
......@@ -225,6 +198,7 @@ begin
end process;
-- Synchronization of the activate_acq_p with the acam_refclk_p_i
ready_to_trigger: process (clk_i)
begin
......@@ -244,8 +218,8 @@ begin
actual_trigger_received: process (clk_i) -- signal needed to exclude the generation of
begin -- the start_from_fpga_o after a general rst_i
actual_trigger_received: process (clk_i) -- signal needed to exclude the generation of
begin -- the start_from_fpga_o after a general rst_i
if rising_edge (clk_i) then
if rst_i ='1' then
start_trig_received <= '0';
......
hdl/svec/hdl/rtl/circular_buffer.vhd
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hdl/svec/hdl/rtl/data_formatting.vhd
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hdl/svec/hdl/rtl/fmc_tdc_core.vhd
View file @ 227e4d01
......@@ -134,7 +134,7 @@ entity fmc_tdc_core is
tdc_mem_wb_we_i : in std_logic; -- WISHBONE pipelined write enable
tdc_mem_wb_cyc_i : in std_logic; -- WISHBONE pipelined cycle
tdc_mem_wb_ack_o : out std_logic; -- WISHBONE pipelined acknowledge
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- WISHBONE classic data out
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- WISHBONE pipelined data out
tdc_mem_wb_stall_o : out std_logic); -- WISHBONE pipelined stall
end fmc_tdc_core;
......@@ -175,6 +175,7 @@ architecture rtl of fmc_tdc_core is
signal circ_buff_class_data_wr, circ_buff_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -502,6 +503,7 @@ begin
rst_i => rst_i,
one_hz_p_i => one_hz_p,
acam_inputs_en_i => acam_inputs_en,
fordebug_i => acam_tstamp1_ok_p,
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
......
hdl/svec/hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 227e4d01
......@@ -130,10 +130,9 @@ architecture rtl of fmc_tdc_mezzanine is
constant c_NUM_WB_MASTERS : integer := 5;
constant c_WB_SLAVE_TDC_CORE_CONFIG : integer := 0; -- TDC core configuration registers
constant c_WB_SLAVE_TDC_ONEWIRE : integer := 1; -- TDC mezzanine board UnidueID&Thermometer 1-wire
constant c_WB_SLAVE_TSTAMP_MEM : integer := 2; -- Access to TDC core timestamps memory
constant c_WB_SLAVE_DUMMY : integer := 2; -- Dummy for debugging
constant c_WB_SLAVE_TDC_SYS_I2C : integer := 3; -- TDC mezzanine board system EEPROM I2C
constant c_WB_SLAVE_DUMMY : integer := 4; -- Dummy for debugging
constant c_WB_SLAVE_TSTAMP_MEM : integer := 4; -- Access to TDC core timestamps memory
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
......@@ -143,11 +142,11 @@ architecture rtl of fmc_tdc_mezzanine is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001100"),
2 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE, x"00001200"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001300"),
4 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00001400"));
(0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00011000"),
2 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00012000"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00013000"),
4 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE, x"00014000"));
---------------------------------------------------------------------------------------------------
-- Signals --
......
hdl/svec/hdl/rtl/leds_manager.vhd
View file @ 227e4d01
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hdl/svec/hdl/rtl/one_hz_gen.vhd
View file @ 227e4d01
......@@ -13,7 +13,7 @@
-- File one_hz_gen.vhd |
-- |
-- Description Generates one pulse every second synchronously with the acam reference clock. |
-- The phase with the reference clock can be adjusted [eva still don t know why??] |
-- The phase with the reference clock can be adjusted. still don t know why?? |
-- It also keeps track of the UTC time based on the local clock. |
-- |
-- |
......@@ -66,16 +66,16 @@ entity one_hz_gen is
(g_width : integer := 32);
port
-- INPUTS
-- Signals from the clks_rsts_manager unit
(clk_i : in std_logic; -- 125 MHZ clk
rst_i : in std_logic; -- global reset, synched to clk_i
acam_refclk_r_edge_p_i : in std_logic; -- rising edge on 31.25MHz ACAM reference clk
clk_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clk_i periods for 1s
-- Signals from the clk_rst_manager unit
(clk_i : in std_logic;
rst_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
clk_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s
-- Signals from the reg_ctrl unit
load_utc_p_i : in std_logic; -- enables loading of the local UTC time with starting_utc_i value
starting_utc_i : in std_logic_vector(g_width-1 downto 0); -- value coming from the PCIe/VME interface
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clk_i periods phase delay
starting_utc_i : in std_logic_vector(g_width-1 downto 0); -- value coming from the PCIe
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
-- with respect to reference clock
-- OUTPUTS
......@@ -92,7 +92,7 @@ end one_hz_gen;
--=================================================================================================
architecture rtl of one_hz_gen is
constant constant_delay : unsigned(g_width-1 downto 0) := x"00000004"; --maybe put in package..maybe not needed
constant constant_delay : unsigned(g_width-1 downto 0) := x"00000004"; --maybe put in package--maybe not needed
signal local_utc : unsigned(g_width-1 downto 0);
signal one_hz_p_pre : std_logic;
signal one_hz_p_post : std_logic;
......@@ -147,9 +147,9 @@ begin
-- Load UTC time --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- utc_counter: generation of a 1-clk-long pulse every second
-- utc_counter: generation of a 1 clk-long pulse every second
utc_counter: process (clk_i) -- maybe use an already existing counter???
utc_counter: process (clk_i)--maybe use an already existing counter???
begin
if rising_edge (clk_i) then
if rst_i ='1' then
......
hdl/svec/hdl/rtl/reg_ctrl.vhd
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hdl/svec/hdl/rtl/start_retrig_ctrl.vhd
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hdl/svec/hdl/rtl/tdc_core_pkg.vhd
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hdl/svec/hdl/rtl/top_tdc.vhd
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hdl/svec/ucf/svec_tdc.ucf
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hdl/svec/xilinx/top_tdc.twr
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hdl/svec/xilinx/xilinxprj_svec_tdc.xise
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