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FMC TDC 1ns 5cha - Gateware
Commit 1eb8f326 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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parent 9fb0d486
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hdl/top/svec/wr_svec_tdc.vhd
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......@@ -196,8 +196,8 @@ entity wr_svec_tdc is
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : inout std_logic;
VME_DTACK_n_o : inout std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_RETRY_n_o : inout std_logic;
VME_RETRY_OE_o : inout std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
......@@ -205,7 +205,7 @@ entity wr_svec_tdc is
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACK_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_IACKOUT_n_o : inout std_logic;
VME_DTACK_OE_o : inout std_logic;
VME_DATA_DIR_o : inout std_logic;
VME_DATA_OE_N_o : inout std_logic;
......@@ -500,11 +500,47 @@ architecture rtl of wr_svec_tdc is
signal led_tdc2_ef, led_vme_access : std_logic;
signal wrabbit_led_red, wrabbit_led_green : std_logic;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_62m5_sys,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
---------------------------------------------------------------------------------------------------
-- 62.5 MHz system clock --
---------------------------------------------------------------------------------------------------
......@@ -911,6 +947,37 @@ begin
VME_ADDR_DIR_o <= VME_ADDR_DIR_int;
VME_DATA_DIR_o <= VME_DATA_DIR_int;
TRIG0(31 downto 1) <= VME_ADDR_b;
TRIG1(31 downto 0) <= VME_DATA_b;
TRIG2(5 downto 0) <= VME_AM_i;
trig2(7 downto 6) <= VME_DS_n_i;
trig2(13 downto 8) <= VME_GA_i;
trig2(14) <= VME_DTACK_n_o;
trig2(15) <= VME_DTACK_oe_o;
trig2(16) <= VME_LWORD_n_b;
trig2(17) <= VME_WRITE_n_i;
trig2(18) <= VME_AS_n_i;
trig2(19) <= VME_DATA_DIR_o;
trig2(20) <= VME_DATA_OE_N_o;
trig2(21) <= VME_addr_DIR_o;
trig2(22) <= VME_addr_OE_N_o;
trig2(23) <= VME_BERR_o;
trig2(24) <= VME_IACKIN_n_i;
trig2(25) <= VME_IACK_n_i;
trig2(26) <= VME_IACKOUT_n_o;
trig2(27) <= VME_RETRY_n_o;
trig2(28) <= VME_RETRY_OE_o;
trig3(0) <= cnx_slave_in(c_MASTER_VME).cyc;
trig3(1) <= cnx_slave_in(c_MASTER_VME).stb;
trig3(2) <= cnx_slave_in(c_MASTER_VME).we;
trig3(3) <= cnx_slave_out(c_MASTER_VME).ack;
trig3(4) <= cnx_slave_out(c_MASTER_VME).stall;
trig3(5) <= cnx_slave_out(c_MASTER_VME).err;
trig3(6) <= cnx_slave_out(c_MASTER_VME).rty;
---------------------------------------------------------------------------------------------------
-- TDC BOARDS --
......
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