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FMC TDC 1ns 5cha - Gateware
Commit 01b71db2 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/testbench: demonstrate DMA to system RAM and continuous acquisition on the SPEC

parent e8673e88
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hdl/testbench/spec/main.sv
View file @ 01b71db2
......@@ -12,22 +12,34 @@
`include "gn4124_bfm.svh"
`include "acam_model.svh"
// don't use the ACAM model, we're testing the readout here
`undef USE_ACAM_MODEL
import tdc_core_pkg::*;
`define SPEC_CSR_BASE 'h0000
// Base addresses of the cores (relative to the beginning of gn4124 BAR0)
`define BASE_SPEC_CSR 'h0000
`define BASE_GENNUM_DMA 'h00c0
`define BASE_VIC 'h0100
`define BASE_TDC_CORE 'h20000
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
// Offsets of TDC core subcomponents
`define OFFSET_TDC_CORE_CFG 'h2000
`define OFFSET_TDC_FIFO1 'h5000
`define OFFSET_TDC_EIC 'h3000
`define OFFSET_TDC_BUFFER_CONTROLLER 'h6000
`define TDC_CORE_BASE 'h20000
`define TDC_CORE_CFG_BASE 'h2000
`define FIFO1_BASE 'h5000
`define TDC_EIC_BASE 'h3000
`define TDC_DMA_BASE 'h6000
// VIC IRQ line assignemnts
`define VIC_IRQ_GENNUM_DMA 2
`define VIC_IRQ_TDC_CORE 6
// base address of the Gennum BAR with system RAM
`define BASE_HOST_MEM 'h20000000
`define TDC_EIC_BUFFER0 (5)
// internal TDC timestamp structure
typedef struct {
uint32_t tai;
uint32_t coarse;
......@@ -39,22 +51,33 @@ typedef struct {
typedef fmc_tdc_timestamp_t fmc_tdc_timestamp_queue_t[$];
// generates a stream of fake (random) timestamps. They are stored in an internal
// queue so that later they can be compared against the values read out over DMA.
class FakeTimestampGenerator;
protected fmc_tdc_timestamp_queue_t m_queue;
protected int m_seq, m_channel;
protected int m_enabled;
function new(int channel);
m_channel = channel;
m_seq = 0;
m_enabled = 0;
endfunction // new
function int is_enabled();
return m_enabled;
endfunction // is_enabled
task automatic enable(int e);
m_enabled = e;
endtask // enable
function automatic fmc_tdc_timestamp_queue_t get_queue();
return m_queue;
endfunction // get_queue
// produces a signle fake timestamp. Returns it and also stores in the local queue for further
// verification
function automatic t_tdc_timestamp generate_hw_timestamp( int slope = 0);
fmc_tdc_timestamp_t ts;
t_tdc_timestamp ts_hw;
......@@ -81,123 +104,348 @@ class FakeTimestampGenerator;
endclass // FakeTimestampGenerator
// Base interface class for a Device (with an assigned base address) connected to a particular bus.
class IBusDevice;
class FmcTdcDriver;
CBusAccessor m_acc;
uint64_t m_base;
uint64_t m_base;
function new ( CBusAccessor acc, uint64_t base );
m_acc =acc;
m_base = base;
endfunction // new
virtual task write32( uint32_t addr, uint32_t val );
// $display("write32 addr %x val %x", m_base + addr, val);
m_acc.write(m_base +addr, val);
endtask // write
virtual task read32( uint32_t addr, output uint32_t val );
automatic uint64_t val64;
m_acc.read(m_base + addr, val64);
val = val64;
endtask // write
endclass // BusDevice
protected const uint32_t BASE_DMA = 'h6000;
protected const uint32_t TDC_CHANNEL_BUFFER_SIZE_BYTES = 'h1000;
protected const int dma_buf_ddr_burst_size_default = 16;
// Driver for the VIC.
class VICDriver extends IBusDevice;
function new(CBusAccessor bus, uint64_t base);
super.new(bus, base);
endfunction // new
fmc_tdc_timestamp_queue_t m_queues[5];
task automatic init();
int i;
for(i=0;i<32;i++)
write32(`BASE_VIC_IVT_RAM + i * 4, i);
write32(`ADDR_VIC_CTL, `VIC_CTL_ENABLE);
endtask // init
// new
function new(CBusAccessor acc, uint64_t base, bit use_dma);
m_acc = acc;
m_base = base;
endfunction
task automatic enable_irqs(uint32_t mask);
write32(`ADDR_VIC_IER, mask);
endtask // enable_irqs
task automatic disable_irqs(uint32_t mask);
write32(`ADDR_VIC_IDR, mask);
endtask // enable_irqs
task automatic get_pending_irq(output uint32_t id);
read32(`ADDR_VIC_VAR, id);
endtask // get_pending_irqs
task automatic clear_pending_irq(uint32_t mask);
write32(`ADDR_VIC_EOIR, mask);
endtask // get_pending_irqs
endclass // VICDriver
// abstract interface implementing an interrupt handler. Used by IrqLine module
// to redirect IRQ events to an appropriate handler function/class.
virtual class IrqHandler;
pure virtual task irq(int id);
endclass // IrqHandler
// Trivial driver for the Gennum DMA
class GennumDMA extends IBusDevice;
protected bit m_dma_pending;
protected time m_t_start, m_t_end;
protected uint32_t m_last_size;
function new(CBusAccessor bus, uint64_t base);
super.new(bus, base);
m_dma_pending = 0;
endfunction // new
// executes a Local-to-Host DMA transfer.
task automatic dma_to_host( uint32_t addr_card, uint32_t addr_host, uint32_t size);
// DMA transfer
$display("[Info] Start GN4124 DMA: card=0x%x host=0x%x size=%d", addr_card,addr_host,size);
write32(`ADDR_DMA_CSTART, addr_card); // dma start addr (card address space)
write32(`ADDR_DMA_HSTARTL, addr_host); // host addr
write32(`ADDR_DMA_HSTARTH, 'h00000000);
write32(`ADDR_DMA_LEN, size); // length
write32(`ADDR_DMA_NEXTL, 'h00000000); // next (we don't use chained transfers for the moment)
write32(`ADDR_DMA_NEXTH, 'h00000000);
write32(`ADDR_DMA_ATTRIB, 'h00000000); // attrib: pcie -> host
write32(`ADDR_DMA_CTRL, 'h00000001); // xfer start
m_t_start = $time;
m_last_size = size;
m_dma_pending = 1;
endtask // dma_to_host
// IRQ handler for the DMA complete interrupt
task automatic irq_dma_complete();
// strange, we got an IRQ without a pending DMA xfer?
if ( !m_dma_pending )
$display("[Error] GN4124 DMA irq without a pending transfer");
write32(`ADDR_DMA_STAT, (1<<2) ); // clear pending IRQ
m_t_end = $time;
$display("[Info] GN4124 DMA transfer complete, %d bytes took %.0f us",
m_last_size, real'(m_t_end - m_t_start) / real'(1us) );
m_dma_pending = 0;
endtask // on_dma_complete
function bit is_dma_pending();
return m_dma_pending;
endfunction // is_dma_pending
endclass // GennumDMA
// writel
task automatic writel(uint32_t addr, uint32_t value);
m_acc.write(addr + m_base ,value);
//$display("[Info] writel %x: %x", addr+m_base, value);
endtask
// Main SPEC TDC driver. Mostly a copy-paste (+ systemverilog translation) of the
// relevant fmc-tdc driver code.
class FmcTdcSPECDriver extends IBusDevice;
protected GennumDMA m_gennum_dma;
protected VICDriver m_vic;
protected int m_using_dma;
// readl
task automatic readl( uint32_t addr, ref uint32_t value );
automatic uint64_t rv;
m_acc.read(addr + m_base , rv);
//$display("[Info] readl %x: %x", addr+m_base, rv);
value = rv;
endtask // readl
// size of the DDR channel buffer
protected const uint32_t TDC_CHANNEL_BUFFER_SIZE_BYTES = 'h100000;
protected const int dma_buf_ddr_burst_size_default = 16;
fmc_tdc_timestamp_queue_t m_queues[5];
// buffer descriptor, as in the driver
typedef struct
{
uint32_t addr[2];
uint32_t active_buffer;
uint32_t size;
uint32_t host_mem_addr;
int total_timestamps;
} tdc_dma_buffer_t;
protected tdc_dma_buffer_t m_buffers[5];
// Gennum DMA IRQ handler - just forward to the Gennum driver
task automatic irq_gennum_dma();
$display("[Info] Handling GN4124 DMA IRQ");
m_gennum_dma.irq_dma_complete();
endtask // irq_gennum_dma
// TDC Core IRQ handler
task automatic irq_tdc_core();
uint32_t isr;
int i;
$display("[Info] Handling TDC Buffer IRQ");
read32(`OFFSET_TDC_EIC + `ADDR_TDC_EIC_EIC_ISR, isr);
// check DMA interrupts, call handler for the buffer(s) for which IRQ(s)
// is/are pending
for(int i = 0; i < 5; i++)
if( isr & ( 1<< (`TDC_EIC_EIC_ISR_TDC_DMA1_OFFSET + i) ) )
irq_dma_buffer(i);
endtask // irq_tdc_core
// IRQ handler for a single DMA buffer
task automatic irq_dma_buffer(int channel);
uint32_t count;
int transfer_buffer;
// tell the TDC to start putting samples in the other buffer so that
// continuous acquisition can be possible
buffer_switch(channel, transfer_buffer);
// Once the buffer is switched, read how many samples we ahve in the previous
// buffer
buffer_get_count(channel , count );
$display("DMA Buffer IRQ: %d, count %d", channel, count);
if( m_gennum_dma.is_dma_pending() )
begin
$error("[Error] Trying to trigger DMA transfer while previous transfer is still pending");
return;
end
// each timestamp is 16 bytes, trigger the gennum DMA xfer
m_gennum_dma.dma_to_host( m_buffers[channel].addr[transfer_buffer],
m_buffers[channel].host_mem_addr, count * 16 );
m_buffers[channel].host_mem_addr += count + 16;
m_buffers[channel].total_timestamps += count;
endtask // irq_dma_buffer
function int get_ts_count(int channel);
return m_buffers[channel].total_timestamps;
endfunction // get_ts_count
function VICDriver get_vic();
return m_vic;
endfunction // get_vic
function new(CBusAccessor bus);
super.new(bus, `BASE_TDC_CORE );
// create the necessary sub-peripherals (VIC and GN4124)
m_vic = new (bus, `BASE_VIC );
m_gennum_dma = new (bus, `BASE_GENNUM_DMA);
m_using_dma = 0;
endfunction // new
task automatic buffer_get_count(int channel, output uint32_t count);
uint32_t base = `OFFSET_TDC_BUFFER_CONTROLLER + ('h40 * channel);
read32( base + `ADDR_TDC_BUF_CUR_COUNT, count );
endtask // buffer_get_count
task automatic buffer_burst_disable(int channel);
uint32_t tmp;
uint32_t base = BASE_DMA + ('h40 * channel);
uint32_t base = `OFFSET_TDC_BUFFER_CONTROLLER + ('h40 * channel);
readl( base + `ADDR_TDC_BUF_CSR, tmp );
read32( base + `ADDR_TDC_BUF_CSR, tmp );
tmp &= ~`TDC_BUF_CSR_ENABLE;
writel(base + `ADDR_TDC_BUF_CSR, tmp );
write32(base + `ADDR_TDC_BUF_CSR, tmp );
endtask // buffer_burst_disable
task automatic buffer_burst_enable(int channel);
uint32_t tmp;
uint32_t base = BASE_DMA + ('h40 * channel);
uint32_t base = `OFFSET_TDC_BUFFER_CONTROLLER + ('h40 * channel);
readl( base + `ADDR_TDC_BUF_CSR, tmp );
read32( base + `ADDR_TDC_BUF_CSR, tmp );
tmp |= `TDC_BUF_CSR_ENABLE;
writel( base + `ADDR_TDC_BUF_CSR, tmp );
write32( base + `ADDR_TDC_BUF_CSR, tmp );
endtask // buffer_burst_disable
task automatic buffer_burst_size_set(int channel, int size);
uint32_t tmp;
uint32_t base = BASE_DMA + ('h40 * channel);
readl( base + `ADDR_TDC_BUF_CSR, tmp );
uint32_t base = `OFFSET_TDC_BUFFER_CONTROLLER + ('h40 * channel);
read32( base + `ADDR_TDC_BUF_CSR, tmp );
tmp &= ~`TDC_BUF_CSR_BURST_SIZE;
tmp |= size << `TDC_BUF_CSR_BURST_SIZE_OFFSET;
write32( base + `ADDR_TDC_BUF_CSR, tmp );
endtask // buffer_burst_size_set
task automatic buffer_irq_timeout_set(int channel, int tmo);
uint32_t tmp;
uint32_t base = `OFFSET_TDC_BUFFER_CONTROLLER + ('h40 * channel);
writel( base + `ADDR_TDC_BUF_CSR, tmp );
read32( base + `ADDR_TDC_BUF_CSR, tmp );
tmp &= ~`TDC_BUF_CSR_IRQ_TIMEOUT;
tmp |= tmo << `TDC_BUF_CSR_IRQ_TIMEOUT_OFFSET;
write32( base + `ADDR_TDC_BUF_CSR, tmp );
endtask // buffer_burst_size_set
task automatic buffer_switch(int channel, output int transfer_buffer);
uint32_t csr;
uint32_t base = `OFFSET_TDC_BUFFER_CONTROLLER + ('h40 * channel);
uint32_t base_cur;
read32( base + `ADDR_TDC_BUF_CSR, csr );
csr |= `TDC_BUF_CSR_SWITCH_BUFFERS;
write32( base + `ADDR_TDC_BUF_CSR, csr );
/*
* It waits until all pending DDR memory transactions from the active
* buffer are committed to the memory.
* This is almost instant (e.g. < 1us), but we never know with
* the PCs going ever faster
*/
forever begin
read32( base + `ADDR_TDC_BUF_CSR, csr );
if( csr & `TDC_BUF_CSR_DONE )
break;
end
/* clear CSR.DONE flag (write 1) */
read32( base + `ADDR_TDC_BUF_CSR, csr );
csr |= `TDC_BUF_CSR_DONE;
write32( base + `ADDR_TDC_BUF_CSR, csr );
typedef struct
{
uint32_t addr[2];
uint32_t active_buffer;
uint32_t size;
} tdc_dma_buffer_t;
/*
* we have two buffers in the hardware: the current one and the 'next'
* one. From the point of view of this interrupt handler, the current
* one is to be read out and switched to the 'next' buffer.,
*/
transfer_buffer = m_buffers[channel].active_buffer;
base_cur = m_buffers[channel].addr [ m_buffers[channel].active_buffer ];
protected tdc_dma_buffer_t m_buffers[5];
m_buffers[channel].active_buffer = 1 - m_buffers[channel].active_buffer;
/* update the pointer to the next buffer */
write32( base + `ADDR_TDC_BUF_NEXT_BASE, base_cur);
write32( base + `ADDR_TDC_BUF_NEXT_SIZE, m_buffers[channel].size | `TDC_BUF_NEXT_SIZE_VALID );
endtask // buffer_switch
task automatic configure_buffers();
int channel;
uint32_t rv, val;
for(channel=0;channel<5;channel++)
begin
uint32_t base = BASE_DMA + ('h40 * channel);
uint32_t base = `OFFSET_TDC_BUFFER_CONTROLLER + ('h40 * channel);
m_buffers[channel].active_buffer = 0;
m_buffers[channel].host_mem_addr = `BASE_HOST_MEM + channel * 'h1000000; // reserve a lot of host memory for each channel
m_buffers[channel].total_timestamps = 0;
m_buffers[channel].size = TDC_CHANNEL_BUFFER_SIZE_BYTES;
buffer_burst_disable(channel);
/* Buffer 1 */
m_buffers[channel].addr[0] = TDC_CHANNEL_BUFFER_SIZE_BYTES * (2 * channel);
writel ( base + `ADDR_TDC_BUF_CUR_BASE, m_buffers[channel].addr[0] );
write32 ( base + `ADDR_TDC_BUF_CUR_BASE, m_buffers[channel].addr[0] );
val = (m_buffers[channel].size << `TDC_BUF_CUR_SIZE_SIZE_OFFSET);
val |= `TDC_BUF_CUR_SIZE_VALID;
writel( base + `ADDR_TDC_BUF_CUR_SIZE, val );
write32( base + `ADDR_TDC_BUF_CUR_SIZE, val );
/* Buffer 2 */
m_buffers[channel].addr[1] = TDC_CHANNEL_BUFFER_SIZE_BYTES * (2 * channel + 1);
writel ( base + `ADDR_TDC_BUF_NEXT_BASE, m_buffers[channel].addr[1] );
write32 ( base + `ADDR_TDC_BUF_NEXT_BASE, m_buffers[channel].addr[1] );
val = (m_buffers[channel].size << `TDC_BUF_NEXT_SIZE_SIZE_OFFSET);
val |= `TDC_BUF_NEXT_SIZE_VALID;
writel( base + `ADDR_TDC_BUF_NEXT_SIZE, val );
write32 ( base + `ADDR_TDC_BUF_NEXT_SIZE, val );
buffer_burst_size_set(channel, dma_buf_ddr_burst_size_default);
buffer_irq_timeout_set(channel, 3);
buffer_burst_enable(channel);
$display("[buf] Config channel %d: base = %x buf[0] = 0x%08x, buf[1] = 0x%08x, %d timestamps per buffer",
$display("[Info] Config channel %d: base = %x buf[0] = 0x%08x, buf[1] = 0x%08x, %d timestamps per buffer",
channel, base, m_buffers[channel].addr[0],
m_buffers[channel].addr[1],
m_buffers[channel].size );
readl( base + `ADDR_TDC_BUF_CSR, val);
read32( base + `ADDR_TDC_BUF_CSR, val);
end // for (channel=0;channel<5;channel++)
......@@ -208,9 +456,15 @@ class FmcTdcDriver;
task automatic init();
uint32_t d;
// we need at least these 2 IRQs to test DMA transfers:
$display("[Info] Init VIC");
m_vic.init();
m_vic.enable_irqs( (1<<`VIC_IRQ_GENNUM_DMA) | (1<<`VIC_IRQ_TDC_CORE ) );
$display("[Info] TDC core base addr: %x", m_base);
readl('h0, d);
read32('h0, d);
if( d != 'h5344422d )
begin
$error("[Error!] Can't read the SDB signature, reading: %x.", d);
......@@ -222,51 +476,55 @@ class FmcTdcDriver;
$display("[Info] Found the SDB signature: %x", d);
end
// Configure the EIC for an interrupt on FIFO
writel(`TDC_EIC_BASE + `ADDR_TDC_EIC_EIC_IER, 'h1F);
// Configure the VIC
writel(`VIC_BASE + `ADDR_VIC_IER, 'h7f);
writel(`VIC_BASE + `ADDR_VIC_CTL, 'h1);
// Configure the TDC
$display("[Info] Setting up TDC core..");
writel(`ADDR_TDC_CORE_CSR_UTC+`TDC_CORE_CFG_BASE, 1234); // set UTC
writel(`ADDR_TDC_CORE_CSR_CTRL+`TDC_CORE_CFG_BASE, 1<<9); // load UTC
writel(`ADDR_TDC_CORE_CSR_IRQ_TSTAMP_THRESH+`TDC_CORE_CFG_BASE, 2); // FIFO threshold = 2 ts
writel(`ADDR_TDC_CORE_CSR_IRQ_TIME_THRESH+`TDC_CORE_CFG_BASE, 2); // FIFO threshold = 2 ms
writel('h20bc, ((-1)<<1)); // test?
$display("[Info] TDC acquisition started");
write32(`ADDR_TDC_CORE_CSR_UTC+`OFFSET_TDC_CORE_CFG, 1234); // set UTC
write32(`ADDR_TDC_CORE_CSR_CTRL+`OFFSET_TDC_CORE_CFG, 1<<9); // load UTC
write32(`ADDR_TDC_CORE_CSR_IRQ_TSTAMP_THRESH+`OFFSET_TDC_CORE_CFG, 2); // FIFO threshold = 2 ts
write32(`ADDR_TDC_CORE_CSR_IRQ_TIME_THRESH+`OFFSET_TDC_CORE_CFG, 2); // FIFO threshold = 2 ms
write32('h20bc, ((-1)<<1)); // test?
endtask // init
task start_acquisition();
writel(`ADDR_TDC_CORE_CSR_ENABLE+`TDC_CORE_CFG_BASE, 'h1f0000); // enable all ACAM inputs
writel(`ADDR_TDC_CORE_CSR_CTRL+`TDC_CORE_CFG_BASE, (1<<0)); // start acquisition
task automatic start_acquisition( int use_dma );
m_using_dma = use_dma;
if( use_dma )
begin
// allocate memory ranges for DDR acquisition buffers for each channel
configure_buffers();
// Configure the EIC for an interrupt on DMA buffer
write32(`OFFSET_TDC_EIC + `ADDR_TDC_EIC_EIC_IER, 'h1F << 5);
$display("[Info] Starting acquisition in DMA mode");
end else begin
write32(`OFFSET_TDC_EIC + `ADDR_TDC_EIC_EIC_IER, 'h1F); // enable FIFO irq
// fixme: FIFO mode not supported
end
write32(`ADDR_TDC_CORE_CSR_ENABLE+`OFFSET_TDC_CORE_CFG, 'h1f0000); // enable all ACAM inputs
write32(`ADDR_TDC_CORE_CSR_CTRL+`OFFSET_TDC_CORE_CFG, (1<<0)); // start acquisition
endtask // start_acquisition
// update
task automatic update();
// fixme: likely doesn't work
task automatic readout_fifo();
automatic uint32_t csr, t[4];
for(int i = 0; i < 1; i++) //(int i = 0; i < 5; i++)
begin
automatic uint32_t FIFObase = `FIFO1_BASE + i * 'h100;
automatic uint32_t FIFObase = `OFFSET_TDC_FIFO1 + i * 'h100;
automatic fmc_tdc_timestamp_t ts, ts1, ts2;
readl(FIFObase + `ADDR_TSF_FIFO_CSR, csr);
read32(FIFObase + `ADDR_TSF_FIFO_CSR, csr);
//$display("!!!csr %x: %x", FIFObase + `ADDR_TSF_FIFO_CSR, csr);
if( ! (csr & `TSF_FIFO_CSR_EMPTY ) ) begin
//$display("!!!FIFO not empty!!! csr %x; empty: %x", csr, `TSF_FIFO_CSR_EMPTY);
readl(FIFObase + `ADDR_TSF_FIFO_R0, t[0]);
readl(FIFObase + `ADDR_TSF_FIFO_R1, t[1]);
readl(FIFObase + `ADDR_TSF_FIFO_R2, t[2]);
readl(FIFObase + `ADDR_TSF_FIFO_R3, t[3]);
read32(FIFObase + `ADDR_TSF_FIFO_R0, t[0]);
read32(FIFObase + `ADDR_TSF_FIFO_R1, t[1]);
read32(FIFObase + `ADDR_TSF_FIFO_R2, t[2]);
read32(FIFObase + `ADDR_TSF_FIFO_R3, t[3]);
ts.tai = t[0];
ts.coarse = t[1];
......@@ -281,6 +539,12 @@ class FmcTdcDriver;
end // for (int i = 0; i < 5; i++)
endtask // update
task automatic readout_dma();
endtask // readout_dma
function int poll();
//$display("[Info] m_queues[0].size: %d", m_queues[0].size());
return (m_queues[0].size() > 2);
......@@ -290,43 +554,74 @@ class FmcTdcDriver;
return m_queues[0].pop_front();
endfunction // get
/*
// update DMA i/f
task automatic update_dma();
automatic uint32_t DMA_CH_base = `TDC_DMA_BASE + 'h100;
automatic uint32_t dma_pos, dma_len;
// read position?
//readl(`DMA_CH_base + `POS, dma_pos); position in DDR /////
$display("<%t> Start DMA, position in DDR: %.8x", $realtime, dma_pos);
// read length?
//readl(`DMA_CH_base + `POS, dma_len); position in DDR /////
$display("<%t> Start DMA, position in DDR: %.8x", $realtime, dma_len);
endclass // FmcTdcDriver
// DMA transfer
writel(`DMA_BASE + `ADDR_DMA_CSTART, dma_pos); // dma start addr
// Master IRQ dispatcher for the SPEC - TDC
class FmcTdcSPECIrqHandler extends IrqHandler;
FmcTdcSPECDriver m_driver;
function new ( FmcTdcSPECDriver drv );
m_driver = drv;
endfunction
writel(`DMA_BASE + `ADDR_DMA_HSTARTL, 'h00001000); // host addr
writel(`DMA_BASE + `ADDR_DMA_HSTARTH, 'h00000000);
// this gets called by IrqLine when the gn_gpio(0) is asserted.
task irq(int id);
uint32_t irq_id;
VICDriver vic = m_driver.get_vic();
// read the pending IRQ ID from the VIC
vic.get_pending_irq(irq_id);
$display("[Info] VIC got irq %d", irq_id);
// dispatch it to the right handler
case(irq_id)
`VIC_IRQ_GENNUM_DMA:
m_driver.irq_gennum_dma();
`VIC_IRQ_TDC_CORE:
m_driver.irq_tdc_core();
default:
$error("[Error] spurious VIC irq %d", irq_id);
endcase // case (irq_id)
// clear IRQ
vic.clear_pending_irq(irq_id);
endtask // irq
endclass // IrqHandler
// length =
writel(`DMA_BASE + `ADDR_DMA_LEN, dma_len); // length
writel(`DMA_BASE + `ADDR_DMA_NEXTL, 'h00000000); // next
writel(`DMA_BASE + `ADDR_DMA_NEXTH, 'h00000000);
// module that observes an interrupt line and if it's asserted
// calls a handler (IrqHandler object) set through set_handler() method.
module IRQLine (
input irq_i
);
writel(`DMA_BASE + `ADDR_DMA_ATTRIB, 'h00000000); // attrib: pcie -> host
IrqHandler m_handler;
task set_handler(IrqHandler h);
m_handler = h;
endtask // set_handler
writel(`DMA_BASE + `ADDR_DMA_ATTRIB, 'h00000001); // xfer start
initial forever
begin
if(!irq_i)
@(posedge irq_i);
if(irq_i)
begin
while(irq_i && m_handler)
begin
m_handler.irq(0);
#5us; // give some grace...
end
end else
#100ns;
end
endmodule // IRQLine
//wait (DUT.inst_spec_base.irqs[2]);
$display("<%t> END DMA", $realtime);
writel(`DMA_BASE + `ADDR_DMA_STAT, 'h04); // clear DMA IRQ
writel(`VIC_BASE + `ADDR_DMA_NEXTH, 'h0);
endtask // update_dma
*/
endclass // FmcTdcDriver
//////////////// main ////////////////
......@@ -420,6 +715,8 @@ module main;
// GN4124 model instantiation
IGN4124PCIMaster Host ();
wire [1:0] gn_gpio;
// TDC core instantiation
......@@ -428,82 +725,81 @@ module main;
.g_simulation(1),
.g_use_fake_timestamps_for_sim(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
.clk_125m_gtp_p_i(clk_125m),
.clk_125m_gtp_n_i(~clk_125m),
.fmc0_tdc_clk_125m_p_i(clk_125m),
.fmc0_tdc_clk_125m_n_i(~clk_125m),
.fmc0_tdc_acam_refclk_p_i(clk_acam),
.fmc0_tdc_acam_refclk_n_i(~clk_acam),
.clk_20m_vcxo_i(clk_20m),
.fmc0_tdc_pll_status_i(1'b1),
.fmc0_tdc_ef1_i(tdc_ef1),
.fmc0_tdc_ef2_i(tdc_ef2),
.fmc0_tdc_err_flag_i(tdc_err_flag),
.fmc0_tdc_int_flag_i(tdc_int_flag),
.fmc0_tdc_rd_n_o(tdc_rd_n),
.fmc0_tdc_wr_n_o(tdc_wr_n),
.fmc0_tdc_oe_n_o(tdc_oe_n),
.fmc0_tdc_cs_n_o(tdc_cs_n),
.fmc0_tdc_data_bus_io(tdc_data),
.fmc0_tdc_address_o(tdc_addr),
.fmc0_tdc_start_from_fpga_o(tdc_start),
.fmc0_tdc_start_dis_o(tdc_start_dis),
.fmc0_tdc_stop_dis_o(tdc_stop_dis[1]),
//`GENNUM_WIRE_SPEC_BTRAIN_REF(Host)
.gn_rst_n_i (Host.rst_n),
.gn_p2l_clk_n_i (Host.p2l_clk_n),
.gn_p2l_clk_p_i (Host.p2l_clk_p),
.gn_p2l_rdy_o (Host.p2l_rdy),
.gn_p2l_dframe_i (Host.p2l_dframe),
.gn_p2l_valid_i (Host.p2l_valid),
.gn_p2l_data_i (Host.p2l_data),
.gn_p_wr_req_i (Host.p_wr_req),
.gn_p_wr_rdy_o (Host.p_wr_rdy),
.gn_rx_error_o (Host.rx_error),
.gn_l2p_clk_n_o (Host.l2p_clk_n),
.gn_l2p_clk_p_o (Host.l2p_clk_p),
.gn_l2p_dframe_o (Host.l2p_dframe),
.gn_l2p_valid_o (Host.l2p_valid),
.gn_l2p_edb_o (Host.l2p_edb),
.gn_l2p_data_o (Host.l2p_data),
.gn_l2p_rdy_i (Host.l2p_rdy),
.gn_l_wr_rdy_i (Host.l_wr_rdy),
.gn_p_rd_d_rdy_i (Host.p_rd_d_rdy),
.gn_tx_error_i (Host.tx_error),
.gn_vc_rdy_i (Host.vc_rdy),
.gn_gpio_b (),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n),
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
.clk_125m_gtp_p_i(clk_125m),
.clk_125m_gtp_n_i(~clk_125m),
.fmc0_tdc_clk_125m_p_i(clk_125m),
.fmc0_tdc_clk_125m_n_i(~clk_125m),
.fmc0_tdc_acam_refclk_p_i(clk_acam),
.fmc0_tdc_acam_refclk_n_i(~clk_acam),
.clk_20m_vcxo_i(clk_20m),
.fmc0_tdc_pll_status_i(1'b1),
.fmc0_tdc_ef1_i(tdc_ef1),
.fmc0_tdc_ef2_i(tdc_ef2),
.fmc0_tdc_err_flag_i(tdc_err_flag),
.fmc0_tdc_int_flag_i(tdc_int_flag),
.fmc0_tdc_rd_n_o(tdc_rd_n),
.fmc0_tdc_wr_n_o(tdc_wr_n),
.fmc0_tdc_oe_n_o(tdc_oe_n),
.fmc0_tdc_cs_n_o(tdc_cs_n),
.fmc0_tdc_data_bus_io(tdc_data),
.fmc0_tdc_address_o(tdc_addr),
.fmc0_tdc_start_from_fpga_o(tdc_start),
.fmc0_tdc_start_dis_o(tdc_start_dis),
.fmc0_tdc_stop_dis_o(tdc_stop_dis[1] ),
//`GENNUM_WIRE_SPEC_BTRAIN_REF(Host)
.gn_rst_n_i (Host.rst_n),
.gn_p2l_clk_n_i (Host.p2l_clk_n),
.gn_p2l_clk_p_i (Host.p2l_clk_p),
.gn_p2l_rdy_o (Host.p2l_rdy),
.gn_p2l_dframe_i (Host.p2l_dframe),
.gn_p2l_valid_i (Host.p2l_valid),
.gn_p2l_data_i (Host.p2l_data),
.gn_p_wr_req_i (Host.p_wr_req),
.gn_p_wr_rdy_o (Host.p_wr_rdy),
.gn_rx_error_o (Host.rx_error),
.gn_l2p_clk_n_o (Host.l2p_clk_n),
.gn_l2p_clk_p_o (Host.l2p_clk_p),
.gn_l2p_dframe_o (Host.l2p_dframe),
.gn_l2p_valid_o (Host.l2p_valid),
.gn_l2p_edb_o (Host.l2p_edb),
.gn_l2p_data_o (Host.l2p_data),
.gn_l2p_rdy_i (Host.l2p_rdy),
.gn_l_wr_rdy_i (Host.l_wr_rdy),
.gn_p_rd_d_rdy_i (Host.p_rd_d_rdy),
.gn_tx_error_i (Host.tx_error),
.gn_vc_rdy_i (Host.vc_rdy),
.gn_gpio_b (gn_gpio),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n),
.sim_timestamp_valid_i(sim_ts_valid),
.sim_timestamp_ready_o(sim_ts_ready),
.sim_timestamp_i(sim_ts)
);
);
// DDR3 model instantiation
ddr3 #
......@@ -533,6 +829,12 @@ module main;
);
`ifndef USE_ACAM_MODEL
// loop that produces fake timestamps. We're not using ACAM here, instead
// the sim_ts inputs (simulation only) of the SPEC top level are routed directly
// to the acquisition core. This speeds up the simulation and also allows to check
// the data integrity of acquisition alone without bothering with all the math associated
// with conversion of the data coming from the ACAM chip.
FakeTimestampGenerator fakeTsGen;
initial
......@@ -541,7 +843,9 @@ module main;
forever begin
repeat(100) @(posedge DUT.clk_sys_62m5);
while(!fakeTsGen.is_enabled())
repeat(100) @(posedge DUT.clk_sys_62m5);
sim_ts <= fakeTsGen.generate_hw_timestamp(0);
sim_ts_valid <= 1;
......@@ -550,6 +854,10 @@ module main;
@(posedge DUT.clk_sys_62m5);
sim_ts_valid <= 0;
@(posedge DUT.clk_sys_62m5);
// wait for some idle time, don't bomb the design with too many timestamps ;-)
repeat(100) @(posedge DUT.clk_sys_62m5);
end
end // initial begin
......@@ -557,6 +865,12 @@ module main;
`endif
IRQLine
irq_line_gennum_master
(
.irq_i(gn_gpio[0])
);
assign tdc_stop_dis[4] = tdc_stop_dis[1];
assign tdc_stop_dis[3] = tdc_stop_dis[1];
......@@ -565,34 +879,60 @@ module main;
// initial
initial begin
CBusAccessor acc;
FmcTdcDriver drv;
uint64_t d;
acc = Host.get_accessor();
#5us;
CBusAccessor acc;
FmcTdcSPECDriver drv;
FmcTdcSPECIrqHandler irq_handler;
int i;
uint64_t d;
acc = Host.get_accessor();
drv = new (acc);
irq_handler = new(drv);
$display("Waiting for the DDR3 controller to bootstrap...");
#4us;
// fixme: poll SPEC reigsters...
$display("DDR3 calibration complete");
// connect the Gennum IRQ line to FMC TDC Driver interrupt routing
irq_line_gennum_master.set_handler( irq_handler );
// un-reset the DDR controller
$error("unreset");
// acc.write( `SPEC_CSR_BASE + `ADDR_SPEC_BASE_REGS_CSR, 0);
// init the board
drv.init();
#500us;
// start acquisition
drv.start_acquisition( 1 );
// fixme: poll SPEC reigsters...
$display("DDR3 calibration complete");
`ifndef USE_ACAM_MODEL
fakeTsGen.enable(1); // generate a bunch of fake timestamps
`endif
// test read
acc.read('h2208c, d);
// let it run for a while
#20us;
// device instantiation
drv = new (acc, `TDC_CORE_BASE, 0 );
drv.init();
drv.configure_buffers();
drv.start_acquisition();
`ifndef USE_ACAM_MODEL
fakeTsGen.enable(0);
`endif
#50us; // fixme: check if all dma xfers are done instead of dumb wait
// Read back. The verification of DDR timestamps against the ones in the queue of FakeTimestampGenerator is left to the reader ;-)
$display("[Info] Channel 0 got %d timestamps", drv.get_ts_count(0) );
$display("HOST MEM DUMP: ");
for(i=0;i<drv.get_ts_count(0) * 4; i++)
begin
uint64_t rv;
Host.host_mem_read(i*8, rv);
$display("hostMem[0x%08x]=0x%016x", i*8, rv);
end
/*
......@@ -600,7 +940,7 @@ module main;
fork
forever begin
drv.update();
drv.readout_fifo();
if(drv.poll()) begin
fmc_tdc_timestamp_t ts1, ts2;
uint64_t timestmp1, timestmp2, diff;
......@@ -628,6 +968,7 @@ module main;
tdc_stop[1] <= 0;
end
join
*/
end
endmodule // main
......
hdl/testbench/spec/wave.do
View file @ 01b71db2
......@@ -38,7 +38,7 @@ add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrab
add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_value_i
add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_wr_p_i
add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/slave_i
add wave -noupdate -group Mezz -expand /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/slave_i
add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/slave_o
add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dma_wb_o
add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dma_wb_i
......@@ -569,97 +569,565 @@ add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_wa
add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_rack
add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/reg_rdat_int
add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/rd_ack1_int
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dq
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_a
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ba
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ras_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_cas_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_we_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_odt
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_reset_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_cke
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dm
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udqs
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udqs_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_rzq
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udm
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_rst_i
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_calib_done
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_clk0
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_rst0
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dqs
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dqs_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ck
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ck_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_en
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_instr
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_bl
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_byte_addr
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_empty
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_full
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_en
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_mask
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_data
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_full
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_empty
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_count
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_underrun
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_error
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_en
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_data
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_full
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_empty
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_count
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_overflow
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_error
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_en
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_instr
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_bl
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_byte_addr
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_empty
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_full
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_en
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_mask
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_data
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_full
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_empty
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_count
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_underrun
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_error
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_en
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_data
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_full
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_empty
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_count
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_overflow
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_error
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk_p
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk_n
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_async_rst
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sysclk_2x
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sysclk_2x_180
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_ce_0
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_ce_90
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_lock
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_mcb_drp_clk
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_error
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_data_valid
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_modify_enable
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_error_status
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_data_mode_value
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_addr_mode_value
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_data
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_selfrefresh_enter
add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_selfrefresh_mode
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dq
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_a
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ba
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ras_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_cas_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_we_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_odt
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_reset_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_cke
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dm
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udqs
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udqs_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_rzq
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udm
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_rst_i
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_calib_done
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_clk0
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_rst0
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dqs
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dqs_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ck
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ck_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_en
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_instr
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_bl
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_byte_addr
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_empty
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_full
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_en
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_mask
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_data
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_full
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_empty
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_count
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_underrun
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_error
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_en
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_data
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_full
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_empty
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_count
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_overflow
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_error
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_en
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_instr
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_bl
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_byte_addr
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_empty
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_full
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_en
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_mask
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_data
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_full
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_empty
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_count
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_underrun
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_error
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_en
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_data
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_full
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_empty
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_count
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_overflow
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_error
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk_p
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk_n
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_async_rst
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sysclk_2x
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sysclk_2x_180
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_ce_0
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_ce_90
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_lock
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_mcb_drp_clk
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_error
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_data_valid
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_modify_enable
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_error_status
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_data_mode_value
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_addr_mode_value
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_data
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_selfrefresh_enter
add wave -noupdate -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_selfrefresh_mode
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/rst_n_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/clk_sys_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_adr_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_dat_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_dat_o
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_cyc_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_sel_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_stb_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_we_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_ack_o
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_err_o
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_rty_o
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_stall_o
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wb_int_o
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_fifo1_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_fifo2_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_fifo3_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_fifo4_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_fifo5_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_dma1_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_dma2_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_dma3_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_dma4_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_tdc_dma5_i
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_idr_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_idr_write_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_ier_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_ier_write_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_imr_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_isr_clear_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_isr_status_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_irq_ack_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/eic_isr_write_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/irq_inputs_vector_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/ack_sreg
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/rddata_reg
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wrdata_reg
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/bwsel_reg
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/rwaddr_reg
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/ack_in_progress
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/wr_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/rd_int
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/allones
add wave -noupdate -group EIC /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_enable_eic/cmp_tdc_eic/allzeros
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/clk_sys_i
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/rst_n_i
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/slave_i
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/slave_o
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/msi_master_i
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/msi_master_o
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/master_i
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/master_o
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/msi_slave_i
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/msi_slave_o
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/master_i_1
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/master_o_1
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/sdb_sel
add wave -noupdate -group xbar-mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_sdb_crossbar/c_layout
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/clk_sys_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/rst_n_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_adr_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_dat_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_dat_o
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_cyc_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_sel_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_stb_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_we_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_ack_o
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_stall_o
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/irqs_i
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/irq_master_o
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/irqs_i_reg
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ctl_pol
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ctl_pol_in
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ctl_wr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ctl_enable
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ctl_emu_edge
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ctl_emu_len
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_risr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ier
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ier_wr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_idr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_idr_wr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_imr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_var
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_eoir
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_eoir_wr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ivt_ram_addr_wb
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ivt_ram_data_towb
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ivt_ram_data_fromwb
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ivt_ram_data_int
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_ivt_ram_wr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_swir
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vic_swir_wr
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/swi_mask
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/current_irq
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/state
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_in
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/wb_out
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/timeout_count
add wave -noupdate -group Vic /main/DUT/inst_spec_base/gen_vic/inst_vic/U_Wrapped_VIC/vector_table
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/clk_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/rst_n_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_irq_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_carrier_addr_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_h_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_host_addr_l_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_len_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_l2p_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_p2l_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_next_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_byte_swap_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_abort_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_done_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_error_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_carrier_addr_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_host_addr_h_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_host_addr_l_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_len_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_next_l_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_next_h_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_attrib_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/next_item_valid_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_rst_n_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_clk_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_adr_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_dat_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_sel_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_cyc_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_stb_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_we_i
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/wb_ack_o
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_abort_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_wr_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_wack_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_byte_swap_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_byte_swap
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_start
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_abort
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_wr
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_cstart
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_hstartl
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_hstarth
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_len
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_nextl
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_nexth
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_attrib_chain
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_async_attrib_dir
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_irq_i_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_irq_o_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_status_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_wr_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_wack_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_rd_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_rack_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_irq_wr_wb
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_irq_wr
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_wr
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_cstart_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_hstartl_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_hstarth_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_len_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_nextl_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_nexth_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_attrib_chain_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_attrib_dir_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_byte_swap_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_ctrl_current_state
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_stat_reg
add wave -noupdate -group GennumDMA /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_dma_controller/dma_irq_reg
add wave -noupdate -group Top /main/DUT/button1_n_i
add wave -noupdate -group Top /main/DUT/clk_20m_vcxo_i
add wave -noupdate -group Top /main/DUT/clk_125m_pllref_p_i
add wave -noupdate -group Top /main/DUT/clk_125m_pllref_n_i
add wave -noupdate -group Top /main/DUT/clk_125m_gtp_n_i
add wave -noupdate -group Top /main/DUT/clk_125m_gtp_p_i
add wave -noupdate -group Top /main/DUT/pll25dac_cs_n_o
add wave -noupdate -group Top /main/DUT/pll20dac_cs_n_o
add wave -noupdate -group Top /main/DUT/plldac_din_o
add wave -noupdate -group Top /main/DUT/plldac_sclk_o
add wave -noupdate -group Top /main/DUT/sfp_txp_o
add wave -noupdate -group Top /main/DUT/sfp_txn_o
add wave -noupdate -group Top /main/DUT/sfp_rxp_i
add wave -noupdate -group Top /main/DUT/sfp_rxn_i
add wave -noupdate -group Top /main/DUT/sfp_mod_def0_i
add wave -noupdate -group Top /main/DUT/sfp_mod_def1_b
add wave -noupdate -group Top /main/DUT/sfp_mod_def2_b
add wave -noupdate -group Top /main/DUT/sfp_rate_select_o
add wave -noupdate -group Top /main/DUT/sfp_tx_fault_i
add wave -noupdate -group Top /main/DUT/sfp_tx_disable_o
add wave -noupdate -group Top /main/DUT/sfp_los_i
add wave -noupdate -group Top /main/DUT/onewire_b
add wave -noupdate -group Top /main/DUT/led_act_o
add wave -noupdate -group Top /main/DUT/led_link_o
add wave -noupdate -group Top /main/DUT/pcbrev_i
add wave -noupdate -group Top /main/DUT/uart_rxd_i
add wave -noupdate -group Top /main/DUT/uart_txd_o
add wave -noupdate -group Top /main/DUT/spi_sclk_o
add wave -noupdate -group Top /main/DUT/spi_ncs_o
add wave -noupdate -group Top /main/DUT/spi_mosi_o
add wave -noupdate -group Top /main/DUT/spi_miso_i
add wave -noupdate -group Top /main/DUT/ddr_a_o
add wave -noupdate -group Top /main/DUT/ddr_ba_o
add wave -noupdate -group Top /main/DUT/ddr_cas_n_o
add wave -noupdate -group Top /main/DUT/ddr_ck_n_o
add wave -noupdate -group Top /main/DUT/ddr_ck_p_o
add wave -noupdate -group Top /main/DUT/ddr_cke_o
add wave -noupdate -group Top /main/DUT/ddr_dq_b
add wave -noupdate -group Top /main/DUT/ddr_ldm_o
add wave -noupdate -group Top /main/DUT/ddr_ldqs_n_b
add wave -noupdate -group Top /main/DUT/ddr_ldqs_p_b
add wave -noupdate -group Top /main/DUT/ddr_odt_o
add wave -noupdate -group Top /main/DUT/ddr_ras_n_o
add wave -noupdate -group Top /main/DUT/ddr_reset_n_o
add wave -noupdate -group Top /main/DUT/ddr_rzq_b
add wave -noupdate -group Top /main/DUT/ddr_udm_o
add wave -noupdate -group Top /main/DUT/ddr_udqs_n_b
add wave -noupdate -group Top /main/DUT/ddr_udqs_p_b
add wave -noupdate -group Top /main/DUT/ddr_we_n_o
add wave -noupdate -group Top /main/DUT/gn_rst_n_i
add wave -noupdate -group Top /main/DUT/gn_gpio_b
add wave -noupdate -group Top /main/DUT/gn_p2l_rdy_o
add wave -noupdate -group Top /main/DUT/gn_p2l_clk_n_i
add wave -noupdate -group Top /main/DUT/gn_p2l_clk_p_i
add wave -noupdate -group Top /main/DUT/gn_p2l_data_i
add wave -noupdate -group Top /main/DUT/gn_p2l_dframe_i
add wave -noupdate -group Top /main/DUT/gn_p2l_valid_i
add wave -noupdate -group Top /main/DUT/gn_p_wr_req_i
add wave -noupdate -group Top /main/DUT/gn_p_wr_rdy_o
add wave -noupdate -group Top /main/DUT/gn_rx_error_o
add wave -noupdate -group Top /main/DUT/gn_l2p_data_o
add wave -noupdate -group Top /main/DUT/gn_l2p_dframe_o
add wave -noupdate -group Top /main/DUT/gn_l2p_valid_o
add wave -noupdate -group Top /main/DUT/gn_l2p_clk_n_o
add wave -noupdate -group Top /main/DUT/gn_l2p_clk_p_o
add wave -noupdate -group Top /main/DUT/gn_l2p_edb_o
add wave -noupdate -group Top /main/DUT/gn_l2p_rdy_i
add wave -noupdate -group Top /main/DUT/gn_l_wr_rdy_i
add wave -noupdate -group Top /main/DUT/gn_p_rd_d_rdy_i
add wave -noupdate -group Top /main/DUT/gn_tx_error_i
add wave -noupdate -group Top /main/DUT/gn_vc_rdy_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_pll_sclk_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_pll_sdi_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_pll_cs_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_pll_dac_sync_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_pll_sdo_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_pll_status_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_clk_125m_p_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_clk_125m_n_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_acam_refclk_p_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_acam_refclk_n_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_start_from_fpga_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_err_flag_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_int_flag_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_start_dis_o
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add wave -noupdate -group Top /main/DUT/fmc0_tdc_data_bus_io
add wave -noupdate -group Top /main/DUT/fmc0_tdc_address_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_cs_n_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_oe_n_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_rd_n_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_wr_n_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_ef1_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_ef2_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_enable_inputs_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_term_en_1_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_term_en_2_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_term_en_3_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_term_en_4_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_term_en_5_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_led_status_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_led_trig1_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_led_trig2_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_led_trig3_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_led_trig4_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_led_trig5_o
add wave -noupdate -group Top /main/DUT/fmc0_tdc_in_fpga_1_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_in_fpga_2_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_in_fpga_3_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_in_fpga_4_i
add wave -noupdate -group Top /main/DUT/fmc0_tdc_in_fpga_5_i
add wave -noupdate -group Top /main/DUT/fmc0_scl_b
add wave -noupdate -group Top /main/DUT/fmc0_sda_b
add wave -noupdate -group Top /main/DUT/fmc0_tdc_onewire_b
add wave -noupdate -group Top /main/DUT/fmc0_prsnt_m2c_n_i
add wave -noupdate -group Top /main/DUT/aux_leds_o
add wave -noupdate -group Top /main/DUT/sim_wb_i
add wave -noupdate -group Top /main/DUT/sim_wb_o
add wave -noupdate -group Top /main/DUT/sim_timestamp_i
add wave -noupdate -group Top /main/DUT/sim_timestamp_valid_i
add wave -noupdate -group Top /main/DUT/sim_timestamp_ready_o
add wave -noupdate -group Top /main/DUT/clk_sys_62m5
add wave -noupdate -group Top /main/DUT/rst_sys_62m5_n
add wave -noupdate -group Top /main/DUT/clk_ref_125m
add wave -noupdate -group Top /main/DUT/rst_ref_125m_n
add wave -noupdate -group Top /main/DUT/tdc0_clk_125m
add wave -noupdate -group Top /main/DUT/cnx_master_out
add wave -noupdate -group Top /main/DUT/cnx_master_in
add wave -noupdate -group Top /main/DUT/cnx_slave_out
add wave -noupdate -group Top /main/DUT/cnx_slave_in
add wave -noupdate -group Top /main/DUT/gn_wb_adr
add wave -noupdate -group Top /main/DUT/tm_link_up
add wave -noupdate -group Top /main/DUT/tm_time_valid
add wave -noupdate -group Top /main/DUT/tm_dac_wr_p
add wave -noupdate -group Top /main/DUT/tm_tai
add wave -noupdate -group Top /main/DUT/tm_cycles
add wave -noupdate -group Top /main/DUT/tm_dac_value
add wave -noupdate -group Top /main/DUT/tm_clk_aux_lock_en
add wave -noupdate -group Top /main/DUT/tm_clk_aux_locked
add wave -noupdate -group Top /main/DUT/wrabbit_en
add wave -noupdate -group Top /main/DUT/pps_led
add wave -noupdate -group Top /main/DUT/ddr_wr_fifo_empty
add wave -noupdate -group Top /main/DUT/fmc0_irq
add wave -noupdate -group Top /main/DUT/irq_vector
add wave -noupdate -group Top /main/DUT/gn4124_access
add wave -noupdate -group Top /main/DUT/tdc_scl_oen
add wave -noupdate -group Top /main/DUT/tdc_scl_in
add wave -noupdate -group Top /main/DUT/tdc_sda_oen
add wave -noupdate -group Top /main/DUT/tdc_sda_in
add wave -noupdate -group Top /main/DUT/tdc0_soft_rst_n
add wave -noupdate -group Top /main/DUT/ddr3_tdc_adr
add wave -noupdate -group Top /main/DUT/powerup_rst_cnt
add wave -noupdate -group Top /main/DUT/carrier_info_fmc_rst
add wave -noupdate -group Top /main/DUT/tdc_dma_out
add wave -noupdate -group Top /main/DUT/tdc_dma_in
add wave -noupdate -group Top /main/DUT/fmc0_wb_ddr_in
add wave -noupdate -group Top /main/DUT/fmc0_wb_ddr_out
add wave -noupdate -group Top /main/DUT/sim_ts_valid
add wave -noupdate -group Top /main/DUT/sim_ts_ready
add wave -noupdate -group Top /main/DUT/sim_ts
add wave -noupdate -group Top /main/DUT/ddr3_status
add wave -noupdate -group Top /main/DUT/dma_reg_adr
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_INT
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_REQ
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_ACK
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_CLOCK_EN
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_RD_DATA
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_RD_DATA_VALID
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RSTINn
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RSTOUT18n
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RSTOUT33n
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/LCLK
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/LCLKn
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_CLKp
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_CLKn
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_DATA
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_DFRAME
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_VALID
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_EDB
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L_WR_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_RD_D_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/TX_ERROR
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_CLKp
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_CLKn
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_DATA
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_DFRAME
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_VALID
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_WR_REQ
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_WR_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RX_ERROR
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/VC_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/GPIO
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/T_LCLKi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/T_P2L_CLK_DLYi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/PRIMARY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/SECONDARY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/GENERATE_X
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/EXPECT_ERROR
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/OUTBOUND_RD_OUTSTANDING
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RESPONSE_DELAY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/GPIOi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/GPIOo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/LCLKo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/LCLKno
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_CLKpi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_CLKni
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_CLKi_90
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_DATAi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_DFRAMEi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_VALIDi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_EDBi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L_WR_RDYo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_RD_D_RDYo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_RDYo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/TX_ERRORo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_CLKpo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_CLKno
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_DATAo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_DFRAMEo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_VALIDo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_RDYi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_WR_REQo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_WR_RDYi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RX_ERRORi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/VC_RDYo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/LCLKi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/LCLKni
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_CLKpo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_CLKno
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_DATAo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_DFRAMEo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_VALIDo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_EDBo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L_WR_RDYi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_RD_D_RDYi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/L2P_RDYi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/TX_ERRORi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_CLKpi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_CLKni
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_DATAi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_DFRAMEi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_VALIDi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P2L_RDYo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_WR_REQi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/P_WR_RDYo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RX_ERRORo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/VC_RDYi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/ICLK
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/LCLK_PERIOD
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CLK0o
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CLK90o
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CLK
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RSTOUTo
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/T_HOLD_OUTi
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/INBOUND_READ_REQUEST_ARRAY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/INBOUND_READ_REQUEST_CPL_STATE
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CURRENT_INBOUND_RD_IPR
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RD_BUFFER
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/OUTBOUND_READ_REQUEST_CPL_STATE
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CURRENT_OUTBOUND_RD_IPR
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RANDOM_NUMBER
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/BAR_ATTRIBUTE_ARRAY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/BFM_BAR_ATTRIBUTE_ARRAY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_REQ0
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_REQ1
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_WR0
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_WR1
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_ACK0
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_ACK1
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_ADDR0
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_ADDR1
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_WR_DATA0
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_WR_DATA1
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_RD_DATA0
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/RAM_RD_DATA1
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/IN_DATA
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/IN_DATA_LOW
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/IN_DFRAME
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/IN_VALID
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/Q_IN_DFRAME
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_RD_DATA_IN
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_RD_DATA_IN_VALID
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/Q_OUT_DATA
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/OUT_DATA
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/Q_OUT_DFRAME
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/OUT_DFRAME
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/Q_OUT_VALID
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/OUT_VALID
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/OUT_WR_REQ
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/OUT_WR_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/Q_OUT_WR_RDY
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_RD_DATA_OUT
add wave -noupdate -expand -group GennumBFM /main/Host/U_BFM/CMD_RD_DATA_OUT_VALID
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {135721 ps} 0}
WaveRestoreCursors {{Cursor 1} {199168064 ps} 0}
configure wave -namecolwidth 383
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -674,4 +1142,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {1625634 ps}
WaveRestoreZoom {0 ps} {416165888 ps}
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