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Created with Raphaël 2.2.02Oct23Sep24Jul16Oct15528Aug23Jul16Jun15117May30Apr2925242322724Mar28Feb8Oct742130Sep29282726324Jun24May16Oct1521Sep17121174331Aug301097627Jul232019Dec181124Nov8Mar17Jan22May19181229Apr1410974326Mar25201820Feb4Nov14Aug14Jul8725Jun23201817131254329May27261914925Apr2310Feb75431Jan302320171428Nov2220137614Oct109230Sep27119Aug526Jul1817125221Jun201422May151430Apr291Oct14Sep527Aug821Jun20141118May16Nov118124Oct2018116423Sep3Aug29Jul2118119MarUpdate .ohwr.yamlmastermasterUpdate .ohwr.yamlAdd .ohwr.yamltop/spec: disable fifo readout (spec driver uses DMA)feature/convent…feature/conventionrtl: fix handling of no fifo_readouttestbench/spec: adjust Manifest.pytop/spec: adjust constraints.syn/spec: adjust Manifest.pyhdl: remove unused declarations.updated submodules; added sourceid feature in metadatasubmodules update for new debugged DMAupdated submodulesupdated submodules and tweaks to meet timingspec syn optimizationsMerge branch 'tom-may08' into feature/conventiontestbench/spec: implement crude bus monitoringtom-may08tom-may08wr_spec_tdc: two fixes in DDR DMA connection:tdc_core_pkg: pad unused packed timestamp bits to 0swip svec with conventionhdl/testbench: demonstrate DMA to system RAM and continuous acquisition on the SPECtom-apr28tom-apr28testbench/include: fix TDC EIC register addresses. THEY ARE BADLY GENERATED by WBGEN, if the driver uses a wbgen-produced .h file cross-check agains the .vh file in this commit!hdl/tdc_dma_engine: use faster IRQ timeout tick period when running in simulation modehdl/tdc_core_pkg: fixed TDC EIC WB descriptor (not sure if necessary, see following commits)hdl: updated SPEC submoduletestbench/spec: Tom's work on DMAtom-apr24tom-apr24testbench: add register headers for the SPEC CSR & TDC DMA Bufferwr_spec_tdc: expose sim_timestamp interface to feed fake timestamps to the core without modelling the ACAM chipalways accept simulated (fake) timestamps...updated submodules (fixes for reset polarity of the DDR controller)rollback to version before dlamprid commit (split channel CSR from FIFO readout)wip testbench added infrastructure for dma testwip testbench speccosmeticscorrected bug on writing-to-FIFO; updated testbencheva-deveva-devadded missing reg_ctrl_pkgbugfix on fmc-id- correction of onewire sdb declaration for a reading of all the regsfile header cleanupwip cleanup of file headerswip cleanup