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FMC TDC 1ns 5cha - Gateware
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FMC TDC 1ns 5cha - Gateware
Commits
6b5e46a8
Commit
6b5e46a8
authored
7 years ago
by
Grzegorz Daniluk
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svec_tdc: add SPI Flash and 1-PPS out signals
parent
572973e6
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hdl/top/svec/wr_svec_tdc.ucf
+19
-1
19 additions, 1 deletion
hdl/top/svec/wr_svec_tdc.ucf
hdl/top/svec/wr_svec_tdc.vhd
+13
-1
13 additions, 1 deletion
hdl/top/svec/wr_svec_tdc.vhd
with
32 additions
and
2 deletions
hdl/top/svec/wr_svec_tdc.ucf
+
19
−
1
View file @
6b5e46a8
...
...
@@ -7,6 +7,12 @@ NET "tdc2_prsntm2c_n_i" LOC = AE29;
NET "tdc1_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
NET "tdc2_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
#----------------------------------------
#----------------------------------------
#
NET "pps_o" LOC = T28;
NET "pps_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC1/FMC2 I2C
#----------------------------------------
...
...
@@ -28,6 +34,18 @@ NET "tdc2_sda_b" IOSTANDARD = LVCMOS33;
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = LVCMOS33;
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AG27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" LOC = AG26;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" LOC = AH26;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" LOC = AH27;
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB version
#----------------------------------------
...
...
@@ -729,4 +747,4 @@ NET "tdc2_data_bus_io[0]" SLEW = FAST;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
\ No newline at end of file
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
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hdl/top/svec/wr_svec_tdc.vhd
+
13
−
1
View file @
6b5e46a8
...
...
@@ -171,6 +171,11 @@ entity wr_svec_tdc is
uart_txd_o
:
out
std_logic
;
-- 1-wire
carrier_onewire_b
:
inout
std_logic
;
-- SPI Flash
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
-- SVEC PCB version
pcb_ver_i
:
in
std_logic_vector
(
3
downto
0
);
-- Mezzanines presence
...
...
@@ -181,6 +186,8 @@ entity wr_svec_tdc is
fp_led_line_o
:
out
std_logic_vector
(
1
downto
0
);
fp_led_column_o
:
out
std_logic_vector
(
3
downto
0
);
pps_o
:
out
std_logic
;
-- VME interface
VME_AS_n_i
:
in
std_logic
;
VME_RST_n_i
:
in
std_logic
;
...
...
@@ -737,10 +744,15 @@ begin
tm_time_valid_o
=>
tm_time_valid
,
tm_tai_o
=>
tm_utc
,
tm_cycles_o
=>
tm_cycles
,
-- SPI Flash
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
-- not used
btn1_i
=>
'0'
,
btn2_i
=>
'0'
,
pps_p_o
=>
open
,
pps_p_o
=>
pps_o
,
-- aux reset
rst_aux_n_o
=>
open
);
...
...
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