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layout-v1.0
Milestone ID: 28
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27
- Consider making core between L6 and L7 thicker
- The P1V5 and VADJ planes stray unneccessarily
- The P1V5 plane gets way too thin at certain points
- The ERTEC IC is missing decoupling capacitors on its Vadj bank
- L10: expand Vadj plane at X:4962mil Y:4289mil
- remove acid traps at some pads
- [L7] create void opening in the Chassis polygon
- Flash.SchDoc both flash chips have the same enable signals and DQ0..15, this will not work
- Change test points to a different component with smaller footprint
- Unify traces thickness
- Not enough reference planes in the board stack-up
- Routing for memories
- [L10] X:5200mil Y:3900mil P3V3A polygon stretch can be removed as it does not connect to anything
- [L1] X:4653mil Y:4085mil very thin 4mil track to P3V3 decoupling cap
- external trigger
- FMC connector: Use separate via for each power pin
- Provide clean return path by providing each GND pin with its own via to GND plane
- Remove GND polygons from signal layers
- RJ45 connector wrong pinout
- Missing magnetics for RJ45 connectors
- Analog power rails should be decoupled against AGND
- Missing decoupling capacitors from ERTEC's (IC16) analog power supply pins
- Memories should be routed in a fly-by topology
- DC/DC layout issues
- [L1] X:4800mil, Y:4100mil mix of tracks and GND polygon create acid traps
- PCB: URL and OHL text missing
- Frontpanel: shows XXXXX