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Last edited by Vasco Guita

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Project description:

The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector. On the PCIe side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. In fact it uses a high-pin count one, but apart from a single clock signal and 4 Gigabit links only the low-pin count part is wired. Also some additional, non-standard power supplies are provided on the high-pin count part of the connector.

A big stress has been put in the versatility of the clocking resources, making this card an ideal component of a synchronous distributed system.

Other FMC projects and the FMC standard are described in FMC Projects.

This project is actually on hold. The simple PCIe FMC carrier is similar.


First prototype* "(large)":https://www.ohwr.org/project/fmc-pci-carrier/uploads/f05c58a883dedba54cb6f4d4cc71b3c1/0002.JPG

Main Features*

* 4-lane PCIe bus (Gennum GN4124)
* FMC slot
o 1 full LPC slot
o DP1 to DP4 gigabit links of HPC
o CLK2_BIDIR and CLK3_BIDIR only from carrier to mezzanine
o +5V, -2V, -5V2 and -12V optionally wired on HPC pins
* 1 Spartan6 FPGA, XC6SLX150T-2FGG676C
* Flexible clocking resources
o 2 Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO)
o 1 any rate I2C programmable crystal oscillator (Si570)
o 1 Direct Digital Synthesizer (DDS) (AD9910)
o 2 Phase Locked Loop (PLL) chips for clock cleaning and redistribution to the FPGAs and the pluggable modules (AD9516-4)
* On board memory
o 72Mbit QDR-II SRAM (CY7C1512KV18-250BZXC)
o A 2Gbit DDR3 (MT41J128M16HA-15E)
o 1 SPI 128Mbit flash proms for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data
* Front panel connectivity
o 1 Small Formfactor Pluggable (SFP) fibre-optic connector
* Internal connectors
o 2 e-SATA connected to 2 GTP blocks
o 1 e-SATA connected to 1 AD9516-4 LVDS output and 1 FPGA differential IO.
o 1 e-SATA connected to a AD9516-4 CLK_IN and to an FPGA GCLK, and 1 FPGA differential IO.
o 1 JTAG header
* FPGA configuration. The FPGA can optionally be programmed from:
o JTAG header
o GN4124 GPIO
o SPI EEPROM or GN4124 SPRIO interface (selected with optional 0Ohm resistors)
* 12-layer PCB
* White Rabbit will be supported by the FMC Standard Kit carriers.

Detailed project information

Reference design

Functional Specifications

Technical Specifications

Clocking guidelines

Planning

Configuration-Options

Debug tools and utilities

Status

Date Event
10-01-2010 Actual start of design (selection of components).
18-05-2010 Schematics finalised, transfered to PCB design office.
19-05-2010 Mechanics of front-panel designed, 3 prototypes will be built.
26-05-2010 Schematics review planned to be held on 2 June. Gennum engineer will also review. Schematics review files
28-05-2010 First placement of components on board. A full-sized PCIe card will be used.
03-06-2010 Review of schematics. Simplified power scheme and reduced number of different components.
Board will be shorter so that it can fit in more slots of the industrial PCs we use.
Suggestion came up to make a very simple PCIe FMC carrier having only the necessary
for standard cards (ADC, DAC, Fine delay, TDC etc.).
05-08-2010 PCB layout review held. review03082010
08-09-2010 PCB modifications ready. Waiting for a final check.
13-09-2010 PCB modifications before production. review13092010
15-09-2010 Received offers for PCIe front-panel with thick Aluminium plate with cutouts.
16-09-2010 Requested production of 4 PCBs of which 3 mounted.
23-09-2010 Front-panels with PMC cut-out ordered from two companies.
11-11-2010 Three assembled boards received. Board powered with 12V: 0.4 Amp. Start of debugging phase.
25-11-2010 Received PCIe front-panels. Issue with size of cutouts.
10-12-2010 PCIe communication to registers in Xilinx working.
03-02-2011 First DMA transfer to/from DDR3 memory.
04-05-2011 QDR memory access working with non-open core written by the company Eurotel.
Needs improvement as the qdr_a and qdr_d signals are placed at two different sides of the device.
04-05-2011 The project is actually on hold. The simple PCIe FMC carrier is similar.

Pablo Alvarez, Matthieu Cattin, Erik van der Bij - 22 June 2011

Files