Changes to run simulation with interfaces in EUDET mode.

Added Dummy_DUT.vhd - which clocks out trigger number

Added delay.vhd , dtype.vhd ( used by  DUTInterface_EUDET_rtl.vhd )

Edited comments in DUTInterface_EUDET_rtl.vhd

Wrote test bench which instantiates dummy EUDET DUTs ( fmc-tlu_v0-1_eudet_test-bench.vhd , based on fmc-tlu_v0-1_test-bench.vhd )

Created spread-sheet to keep track of verification tests on firmware.

Wrote script to put DUTs into AIDA mode ( test_aida_tlu_internal_triggers_eudet_v2.py , based on test_aida_tlu_internal_triggers_v2.py )