Checking in modified files before taking tag. single_pulse changes not tested but should be harmless.

Checking in changes to event formatter to get fine-grain timing information aligned with trigger and hence written to FIFO correctly

Changed number of registers in TriggerLogic to 16 - allows trigger hold-off word to be recorded and aux triggers. Also changed address map for PyChips and uHAL

replaced timestamp counter with high/low parts with single 48-bit counter. seems to eliminate bug with bit flipping high prematurely. also gives shorter and easier to read code

replaced timestamp counter with high/low parts with single 48-bit counter. seems to eliminate bug with bit flipping high prematurely. also gives shorter and easier to read code

fixed typo in miniTLU.xml (counter registers were write-only rather than read-only). Added print out of counters to startTLU

- changed IPBus read from FIFO in eventBuffer_rtl.vhd. Probably uncessary, but not going back now. In process changed FIFO to standard rather than fall-through and decreased size ( to try to help with timing closure )

- Put SHREG attribute in logic_clocks_rtl.vhd. Should also add to other places.

- Added pulse stretch to stretchPulse_rtl.vhd ( used to be just delay )

- Randomly hacked event formatter until it records which trigger fired.

- trigger logic hacked to provide only a single clock cycle trigger ( rather than staying high for however long the trigger combination was active.

- Trying to reduce timing errors by specifying which nets don't need timing closure ( using TIG ) in sp605_FMC_mTLU_v1a.ucf

- Uncommented re-generate IP in build_bitstream.tcl 

unable to understand Alvaro's code, so removed it ( will re-implement later ).
This involved editing
* eventFormatter to strip out Alvaro's code
* triggerLogic to connect stretched triggers not input triggers to trigger_o

Wrote script to set registers to that simulation works OK
( aida_tlu_enable_data_recording.py )

Added simple control - s = start running , q = quit. Writes to a ROOT file, but output not yet checked

Checking in scripts to read out data from TLU. v3 is functional. v4 is starting to transition to uHAL

Added Dummy_DUT.vhd - which clocks out trigger number

Added delay.vhd , dtype.vhd ( used by  DUTInterface_EUDET_rtl.vhd )

Edited comments in DUTInterface_EUDET_rtl.vhd

Wrote test bench which instantiates dummy EUDET DUTs ( fmc-tlu_v0-1_eudet_test-bench.vhd , based on fmc-tlu_v0-1_test-bench.vhd )

Created spread-sheet to keep track of verification tests on firmware.

Wrote script to put DUTs into AIDA mode ( test_aida_tlu_internal_triggers_eudet_v2.py , based on test_aida_tlu_internal_triggers_v2.py )

Write to "DUTInterfaceMode" register to choose between EUDET (0) and AIDA (1) modes

Will result in pseudo-LVDS for clock lines ( Boo.... ) put termination resistors in bodge boards.

Executes in simulation, produces internal triggers when test_aida_tlu_internal_triggers_v2.py run.

Edited setup_project.tcl so that new files are inserted into ISE project ( NOT TESTED)

Edited add_files.tcl so that new files are are inserted into Modelsim/Questa project ( NOT TESTED)

Removed unused trigger_counter_o port from EventFormatter. Connected up DUTInterface to TriggerLogic trigger_counter instead.

Factorized  hdl/common/DUTInterfaces_rtl.vhd to put hand-shake specific ( EUDET/AIDA ) code into hdl/common/DUTInterface_AIDA_rtl.vhd and hdl/common/DUTInterface_EUDET_rtl.vhd.

N.B. DUTInterface_EUDET_rtl.vhd not yet tested. DUTInterface_AIDA_rtl.vhd runs in simulation.

Improved Doxygen comments in coincidenceLogic_rtl.vhd , hdl/common/synchronizeRegisters_rtl.vhd ,  hdl/common/triggerLogic_rtl.vhd

Increased number of DUTs in simulation_src/fmc-tlu_v0-1_test-bench.vhd from 2 to 3.

Modified 

* Fixed bug in simulation by connecting up 40MHz clock from clock_sim module in IPBusInterface

* By-passed problem in test_aida_tlu_internal_triggers_v2.py by setting thresholds to -0.2V so that triggers not active

* Editing simulation test bench to remove ports no longer present ( simulation_src/fmc-tlu_v0-1_test-bench.vhd )

* Tidying up documentation ( in Doxygen / VHDL need to put @brief etc. near entity decl not at top of file ... )

T0_Shutter_Iface_rtl.vhd (which doesn't expect external shutter/T0 signals)

* Edited setup_project.tcl to reflect change from TPx3_iface_rtl.vhd --> T0_Shutter_Iface_rtl.vhd

* Edited sp605_FMC_mTLU_v1a.ucf  to reflect change from TPx3_iface_rtl.vhd --> T0_Shutter_Iface_rtl.vhd

* Edited fmc_tlu_chipscope.cdc  to change connections associated with  change from TPx3_iface_rtl.vhd --> T0_Shutter_Iface_rtl.vhd

to internal clock generation before merging back to trunk.

Made links from HDL source files to HDL designer directories to permit
HDL designer to work but make is easy to build firmware if HDL designer not
present

Added some more scripts.