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AIDA-2020 TLU
Commit ad3b0ac0 authored by Alvaro Dosil's avatar Alvaro Dosil
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synchronizing data

parent e86fd949
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Showing with 18 additions and 10 deletions
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ ad3b0ac0
......@@ -147,11 +147,13 @@ ARCHITECTURE rtl OF eventFormatter IS
signal s_coarse_timestamp : unsigned(c_COARSE_TIMESTAMP_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
-- signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- increment after each post-veto trigger.
signal s_word0 , s_word1, s_word2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal s_word0 , s_word1, s_word2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal s_word0_d1 , s_word1_d1, s_word2_d1 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal s_word0_d2 , s_word1_d2, s_word2_d2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal s_word0_d3 , s_word1_d3, s_word2_d3 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal trigger_inputs_fired_d1 : std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => '0');
signal trigger_times_d1 : t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => (others=>'0'));
signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
signal s_enable_record, s_enable_record_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (2 downto 0 => '1', others=>'0'); -- Enable data record
signal s_enable_trigger : std_logic := '1'; -- Enable trigger record
......@@ -219,7 +221,10 @@ BEGIN
s_event_strobe_d1 <= trigger_i and s_enable_trigger;
s_event_strobe_d2 <= s_event_strobe_d1;
s_event_strobe_d3 <= s_event_strobe_d2;
trigger_inputs_fired_d1 <= trigger_inputs_fired_i;
trigger_times_d1 <= trigger_times_i;
s_word0_d1 <= s_word0;
s_word1_d1 <= s_word1;
s_word1_d2 <= s_word1_d1;
......@@ -248,14 +253,14 @@ BEGIN
-------------------------------------------------------------------------------
-- Trigger event formater
-------------------------------------------------------------------------------
s_evttype(0) <= "0000" when unsigned(trigger_inputs_fired_i) = 0 and trigger_i = '1' else
s_evttype(0) <= "0000" when unsigned(trigger_inputs_fired_d1) = 0 and trigger_i = '1' else
"0001";
s_var(0) <= trigger_inputs_fired_i & std_logic_vector(to_unsigned(0,s_var(0)'length-g_NUM_TRIG_INPUTS));
s_var(0) <= trigger_inputs_fired_d1 & std_logic_vector(to_unsigned(0,s_var(0)'length-g_NUM_TRIG_INPUTS));
s_word0 <= s_evttype(0) & s_var(0) & std_logic_vector(s_coarse_timestamp);
s_word1 <= "000" & trigger_times_i(0) & "000" & trigger_times_i(1) &
"000" & trigger_times_i(2) & "000" & trigger_times_i(3) &
s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
"000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &
trigger_cnt_i;
-- Different number of trigger inputs require packing into s_word2 in
......@@ -311,7 +316,7 @@ BEGIN
--! Could also output data on trigger_i , but let's use the delayed signals. \n
--! The counters are one cycle delayed from the signal generation
s_FIFO_i(0) <= s_word0_d1 when (s_event_strobe_d1 = '1') else
s_word1_d1 when (s_event_strobe_d2 = '1') else
s_word1_d2 when (s_event_strobe_d2 = '1') else
s_word2_d3 when (s_event_strobe_d3_opt = '1') else
(others => '0');
......
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ ad3b0ac0
......@@ -2,8 +2,6 @@
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMaskW 0x00000020 0xffffffff 1 1
DUTMaskR 0x00000028 0xffffffff 1 1
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 1 1
......@@ -11,6 +9,11 @@ ThrCount0 0x00000041 0xffffffff 1 0
ThrCount1 0x00000042 0xffffffff 1 0
ThrCount2 0x00000043 0xffffffff 1 0
ThrCount3 0x00000044 0xffffffff 1 0
SerdesRstR 0x00000048 0xffffffff 1 1
ThrCount0R 0x00000049 0xffffffff 1 0
ThrCount1R 0x0000004a 0xffffffff 1 0
ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
*
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
......
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