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AIDA-2020 TLU
Commit e86fd949 authored by Alvaro Dosil's avatar Alvaro Dosil
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updates from CERN meeting on 09/04/2014. Trigger counter, DUT mask and bug fixing

parent a3ba6405
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firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ e86fd949
......@@ -35,7 +35,7 @@
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! @todo <next thing to do> Indicate if the DUT works under AIDA/EUDET style\n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
......@@ -47,6 +47,7 @@ USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
......@@ -91,53 +92,104 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1 : std_logic;
signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
constant c_N_CTRL : positive := 1;
constant c_N_STAT : positive := 1;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- IPBus. Dummy for now.
-----------------------------------------------------------------------------
ipbus_o.ipb_err <= '0';
ipbus_o.ipb_ack <= ipbus_i.ipb_strobe;
ipbus_o.ipb_rdata <= ( others => '1');
-- -----------------------------------------------------------------------------
-- -- IPBus. Dummy for now.
-- -----------------------------------------------------------------------------
-- ipbus_o.ipb_err <= '0';
-- ipbus_o.ipb_ack <= ipbus_i.ipb_strobe;
-- ipbus_o.ipb_rdata <= ( others => '1');
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
duts: for dut in 1 to g_NUM_DUTS generate
-- busy_IBUFDS_inst : IBUFDS
-- generic map (
-- DIFF_TERM => TRUE, -- Differential Termination
-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "LVDS_25")
-- port map (
-- O => s_busy_from_dut(dut-1), -- Buffer output
-- I => busy_from_dut_p_i(dut-1), -- Diff_p buffer input (connect directly to top-level port)
-- IB => busy_from_dut_n_i(dut-1) -- Diff_n buffer input (connect directly to top-level port)
-- );
busy_IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => s_busy_from_dut(dut-1), -- Buffer output
I => busy_from_dut_p_i(dut-1), -- Diff_p buffer input (connect directly to top-level port)
IB => busy_from_dut_n_i(dut-1) -- Diff_n buffer input (connect directly to top-level port)
);
trig_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => trigger_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => trigger_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_trigger_to_dut(dut-1) -- Buffer input
O => trigger_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => trigger_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_trigger_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
);
clk_rst_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => reset_or_clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => reset_or_clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_reset_or_clk_to_dut(dut-1) -- Buffer input
O => reset_or_clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => reset_or_clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_reset_or_clk_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
s_busy_from_dut(dut-1);
(s_busy_from_dut(dut-1) and
s_DUT_mask(dut-1));
end generate duts;
......
firmware/hdl/common/arrivalTimeLUT_rtl.vhd
View file @ e86fd949
......@@ -190,7 +190,7 @@ BEGIN
PORT MAP (
clock_i => clk_4x_logic_i,
enable_i => '1',
reset_i => strobe_4x_logic_i, --'0',
reset_i => strobe_4x_logic_i, -- Synchronous reset, so the counter will present result_o="11" when reset_i='1'
result_o => s_coarse_bits
);
......
firmware/hdl/common/eventBuffer_rtl.vhd
View file @ e86fd949
......@@ -173,7 +173,7 @@ BEGIN
---- multiply s_wr_data_count by 2 before subraction
--! wr_data_count and rd_data_count provide exactly the same information but in different clock domains
---- s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
--s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
s_fifo_fill_level <= unsigned(s_rd_data_count);
END ARCHITECTURE rtl;
......
firmware/hdl/common/triggerInputs_rtl.vhd
View file @ e86fd949
......@@ -283,6 +283,7 @@ BEGIN
data_o => s_deserialized_CFD_data(triggerInput),
status_o => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
);
--s_deserialized_CFD_data(triggerInput) <= (others=>'0');
s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
CFDLUT : entity work.arrivalTimeLUT
......
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @ e86fd949
......@@ -368,7 +368,8 @@ BEGIN
logic_clocks_reset <= '0';
-- ModuleWare code(v1.12) for instance 'I10' of 'gnd'
trigger_cnt_i <= (OTHERS => '0');
--trigger_cnt_i <= (OTHERS => '0');
trigger_cnt_i <= event_number_o;
-- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
spill_i <= '0';
......
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ e86fd949
......@@ -2,6 +2,8 @@
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMaskW 0x00000020 0xffffffff 1 1
DUTMaskR 0x00000028 0xffffffff 1 1
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 1 1
......
firmware/scripts/aida_mini_tlu_addr_map.txt~
View file @ e86fd949
......@@ -2,6 +2,7 @@
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMask 0x00000020 0xffffffff 1 1
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 1 1
......@@ -10,7 +11,7 @@ ThrCount1 0x00000042 0xffffffff 1 0
ThrCount2 0x00000043 0xffffffff 1 0
ThrCount3 0x00000044 0xffffffff 1 0
*
* trigger logic = 0x060 **Note Read and write directions separated
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
TriggerMaskW 0x00000063 0xffffffff 1 1
TriggerVetoW 0x00000064 0xffffffff 1 1
......
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