Checking in changes before requesting move to Git. Adding fmc_tlu_hdmi_passive_adaptor files

circuit_board/Cadence/worklib/fmc_tlu_hdmi_passive_adaptor/physical/README

+
+fmc_tlu_hdmi_passive_adaptor
+
+These file describes PCB fabrication and assembly details of a 
+HDMI <--> RJ45 passive converter for EUDET/AIDA/AIDA-2020 TLU<-->DUT
+connections.
+
+contact:	David.Cussans@bristol.ac.uk
+		tel: 0117 95 46879
+		     0117 33 17199
+		fax: 0117 925 5624
+
+Files produced by Cadence Allegro PE17.2
+
+Version: B
+Date: 22/June/2018
+
+Artwork:
+--------
+
+Format: Gerber RS-274X , parameters described in art_param.txt. 
+All layers viewed from top
+
+Build:
+------
+
+Two Layers as follows:
+
+fmc_tlu_hdmi_rj45_L1.art
+fmc_tlu_hdmi_rj45_L2.art
+
+FR4 or similar laminate
+
+35um copper ( after plating )
+
+Solder Masks
+------------
+
+fmc_tlu_hdmi_rj45_SM1.art
+fmc_tlu_hdmi_rj45_SM2.art
+
+Colour not critical, suggest green. Photo-imagable.
+
+Solderpaste masks
+-----------------
+
+There there are no solder-paste masks - there are only through hole components
+
+Silk screen
+-----------
+
+(there is no silk screen on the top surface )
+fmc_tlu_hdmi_rj45_SS2.art
+
+
+Colour not critical, suggest white.
+
+Assembly Diagram
+-----------------
+
+fmc_tlu_hdmi_rj45_AST.art
+( no components on bottom surface )
+
+
+Board outline: (Gerber RS-274X)
+-------------------------------
+
+fmc_tlu_hdmi_rj45_OUTLINE.art
+
+
+Drill figure: ( illustration of hole sizes and position )
+-------------
+
+fmc_tlu_hdmi_rj45_DD.art
+
+
+
+Drill information ( Excellon format, described in nc_param.txt )
+-----------------
+Plated and unplated holes in same file.
+
+fmc_tlu_hdmi_passive_adaptor_07-1-2.drl
+
+
+Router Information 
+-------------------
+
+fmc_tlu_hdmi_passive_adaptor_07-1-2.rou
+
+
+Bill of Materials
+-----------------
+
+fmc_tlu_hdmi_passive_adaptor.xlsx
+
+ODB++ format:
+-------------
+
+Fabrication and assembly information in
+fmc_tlu_hdmi_passive_adaptor_07.tgz
+

circuit_board/Cadence/worklib/fmc_tlu_hdmi_passive_adaptor/physical/fmc_tlu_hdmi_passive_adaptor_07-1-2.drl

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+;LEADER: 12 
+;HEADER: 
+;CODE  : ASCII 
+;FILE  : fmc_tlu_hdmi_passive_adaptor_07-1-2.drl for  ... layers TOP and BOTTOM
+;DESIGN: fmc_tlu_hdmi_passive_adaptor_07.brd
+;T01 Holesize 1. = 0.410000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 4
+;T02 Holesize 2. = 0.550000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 19
+;T03 Holesize 3. = 0.810000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 12
+;T04 Holesize 4. = 0.910000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 8
+;T05 Holesize 5. = 1.600000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
+;T06 Holesize 6. = 3.200000 Tolerance = +0.000000/-0.000000 PLATED MM Quantity = 2
+;T07 Holesize 7. = 1.700000 Tolerance = +0.000000/-0.000000 NON_PLATED MM Quantity = 2
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circuit_board/Cadence/worklib/fmc_tlu_hdmi_passive_adaptor/physical/fmc_tlu_hdmi_passive_adaptor_07.rou

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+;HEADER: 
+;CODE  : ASCII 
+;FILE  : /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_hdmi_passive_adaptor/physical/fmc_tlu_hdmi_passive_adaptor_07.rou for board /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_hdmi_passive_adaptor/physical/#Taaaaaw00858.tmp
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