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Commit 80534e21 authored by Paolo Baesso's avatar Paolo Baesso
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EUDET files now used shared libraries from the packages folder

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......@@ -11,6 +11,7 @@
## Backup files
*.py~
*.md~
*.sh~
## Core latex/pdflatex auxiliary files:
*.aux
......
EUDETdummy/scripts/AD5665R.py deleted 100644 → 0
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# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class AD5665R:
#Class to configure the DAC modules
def __init__(self, i2c, slaveaddr=0x1F):
self.i2c = i2c
self.slaveaddr = slaveaddr
def setIntRef(self, intRef=False, verbose=False):
mystop=True
if intRef:
cmdDAC= [0x38,0x00,0x01]
else:
cmdDAC= [0x38,0x00,0x00]
self.i2c.write( self.slaveaddr, cmdDAC, mystop)
if verbose:
print "DAC int ref:", intRef
def writeDAC(self, dacCode, channel, verbose=False):
#Vtarget is the required voltage, channel is the DAC channel to target
#intRef indicates whether to use the external voltage reference (True)
#or the internal one (False).
print "\tDAC value:" , hex(dacCode)
if channel<0 or channel>7:
print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
return -1
if dacCode<0:
print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
dacCode=0
elif dacCode>0xFFFF :
print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
dacCode=0xFFFF
sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
print "\tWriting DAC string:", sequence
mystop= False
self.i2c.write( self.slaveaddr, sequence, mystop)
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# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class AD5665R:
#Class to configure the DAC modules
def __init__(self, i2c, slaveaddr=0xC):
self.i2c = i2c
self.slaveaddr = slaveaddr
def setIntRef(self, intRef=False, verbose=False):
mystop=True
if intRef:
cmdDAC= [0x38,0x00,0x01]
else:
cmdDAC= [0x38,0x00,0x00]
self.i2c.write( self.slaveaddr, cmdDAC, mystop)
if verbose:
print "DAC int ref:", intRef
def writeDAC(self, dacCode, channel, verbose=False):
#Vtarget is the required voltage, channel is the DAC channel to target
#intRef indicates whether to use the external voltage reference (True)
#or the internal one (False).
print "\t DAC value:" , dacCode
if channel<0 or channel>7:
print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
##return -1
if dacCode<0:
print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
dacCode=0
elif dacCode>0xFFFF :
print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
dacCode=0xFFFF
sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
print "\t Writing DAC string:", sequence
mystop= False
self.i2c.write( self.slaveaddr, sequence, mystop)
EUDETdummy/scripts/AIDA_testScript.py~ deleted 100644 → 0
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# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
# #######################################
#
# time.sleep(0.1)
# #Read the EPROM
# mystop=False
# nwords=6
# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
# myaddr= [0xfa]#0xfa
# master_I2C.write( myslave, myaddr, mystop)
# #res= master_I2C.read( 0x50, 6)
# res= master_I2C.read( myslave, nwords)
# print " PCB EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
# #######################################
#Second I2C core
#print ("Instantiating SFP I2C core:")
#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
#clock_I2C.state()
# #Third I2C core
# print ("Instantiating clock I2C core:")
# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
# clock_I2C.state()
# #time.sleep(0.01)
# #Read the EPROM
# mystop=False
# nwords=2
# myslave= 0x68 #DUNE CLOCK CHIP 0x68
# myaddr= [0x02 ]#0xfa
# clock_I2C.write( myslave, myaddr, mystop)
# #time.sleep(0.1)
# res= clock_I2C.read( myslave, nwords)
# print " CLOCK EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
#
#CLOCK CONFIGURATION BEGIN
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0B]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL: 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS: 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(0, 0xFF)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(1, 0xFF)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0xFF)# 0= normal
IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(0, 0xFF)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x0F)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# #Reset counters
#cmd = int("0x0", 16) #write 0x2 to reset
#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
#hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
## #Read trigger inputs
#myreg= [-1, -1, -1, -1, -1, -1]
#for inputN in range(0, 6):
# regString= "triggerInputs.ThrCount%dR" % inputN
# myreg[inputN]= hw.getNode(regString).read()
# hw.dispatch()
# print regString, myreg[inputN]
## Read ev formatter
#cmd = int("0x0", 16) #
##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
#hw.dispatch()
#print "Event Formatter Record: 0x%X" % efstatus
EUDETdummy/scripts/E24AA025E48T.py deleted 100644 → 0
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# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class E24AA025E48T:
#Class to configure the EEPROM
def __init__(self, i2c, slaveaddr=0x50):
self.i2c = i2c
self.slaveaddr = slaveaddr
def readEEPROM(self, startadd, nBytes):
#Read EEPROM memory locations
mystop= False
myaddr= [startadd]#0xfa
self.i2c.write( self.slaveaddr, [startadd], mystop)
res= self.i2c.read( self.slaveaddr, nBytes)
return res
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EUDETdummy/scripts/EUDETdummy.pyc
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EUDETdummy/scripts/FmcTluI2c.py deleted 100644 → 0
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import time
#from PyChipsUser import *
from I2cBusProperties import *
from RawI2cAccess import *
class FmcTluI2c:
############################
### configure i2c connection
############################
def __init__(self,board):
self.board = board
i2cClockPrescale = 0x30
self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
return
##########################
### scan all i2c addresses
##########################
def i2c_scan(self):
list=[]
for islave in range(128):
i2cscan = RawI2cAccess(self.i2cBusProps, islave)
try:
i2cscan.write([0x00])
device="slave address "+hex(islave)+" "
if islave==0x1f:
device+="(DAC)"
elif islave==0x50:
device+="(serial number PROM)"
elif islave>=0x54 and islave<=0x57:
device+="(sp601 onboard EEPROM)"
else:
device+="(???)"
pass
list.append(device)
pass
except:
pass
pass
return list
###################
### write to EEPROM
###################
def eeprom_write(self,address,value):
if address<0 or address>127:
print "eeprom_write ERROR: address",address,"not in range 0-127"
return
if value<0 or value>255:
print "eeprom_write ERROR: value",value,"not in range 0-255"
return
i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
prom.write([address,value])
time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
return
####################
### read from EEPROM
####################
def eeprom_read(self,address):
if address<0 or address>255:
print "eeprom_write ERROR: address",address,"not in range 0-127"
return
i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
prom.write([address])
return prom.read(1)[0]
######################
### read serial number
######################
def get_serial_number(self):
result=""
for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
result+="%02x "%(self.eeprom_read(iaddr))
pass
return result
#################
### set DAC value
#################
def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
if channel<0 or channel>7:
print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
return -1
if value<0 or value>0xFFFF:
print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
return -1
# AD5665R chip with A0,A1 tied to ground
#i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
# if we want to enable internal voltage reference:
if vrefOn:
# enter vref-on mode:
print "Turning internal reference ON"
dac.write([0x38,0x00,0x01])
else:
print "Turning internal reference OFF"
dac.write([0x38,0x00,0x00])
# now set the actual value
sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
print sequence
dac.write(sequence)
##################################################
### convert required threshold voltage to DAC code
##################################################
def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
Vdaq = ( desiredVoltage + Vref ) / 2
dacCode = 0xFFFF * Vdaq / Vref
return int(dacCode)
##################################################
### calculate the DAC code required and set DAC
##################################################
def set_threshold_voltage(self, channel , voltage ):
dacCode = self.convert_voltage_to_dac(voltage)
print " requested voltage, calculated DAC code = " , voltage , dacCode
self.set_dac(channel , dacCode)
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EUDETdummy/scripts/I2CuHal.py deleted 100644 → 0
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# -*- coding: utf-8 -*-
"""
"""
import time
import uhal
verbose = True
################################################################################
# /*
# I2C CORE
# */
################################################################################
class I2CCore:
"""I2C communication block."""
# Define bits in cmd_stat register
startcmd = 0x1 << 7
stopcmd = 0x1 << 6
readcmd = 0x1 << 5
writecmd = 0x1 << 4
ack = 0x1 << 3
intack = 0x1
recvdack = 0x1 << 7
busy = 0x1 << 6
arblost = 0x1 << 5
inprogress = 0x1 << 1
interrupt = 0x1
def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
self.target = target
self.name = name
self.delay = delay
self.prescale_low = self.target.getNode("%s.i2c_pre_lo" % name)
self.prescale_high = self.target.getNode("%s.i2c_pre_hi" % name)
self.ctrl = self.target.getNode("%s.i2c_ctrl" % name)
self.data = self.target.getNode("%s.i2c_rxtx" % name)
self.cmd_stat = self.target.getNode("%s.i2c_cmdstatus" % name)
self.wishboneclock = wclk
self.i2cclock = i2cclk
self.config()
def state(self):
status = {}
status["ps_low"] = self.prescale_low.read()
status["ps_hi"] = self.prescale_high.read()
status["ctrl"] = self.ctrl.read()
status["data"] = self.data.read()
status["cmd_stat"] = self.cmd_stat.read()
self.target.dispatch()
status["prescale"] = status["ps_hi"] << 8
status["prescale"] |= status["ps_low"]
for reg in status:
val = status[reg]
bval = bin(int(val))
if verbose:
print "\treg %s = %d, 0x%x, %s" % (reg, val, val, bval)
def clearint(self):
self.ctrl.write(0x1)
self.target.dispatch()
def config(self):
#INITIALIZATION OF THE I2S MASTER CORE
#Disable core
self.ctrl.write(0x0 << 7)
self.target.dispatch()
#Write pre-scale register
#prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
#prescale = 0x2710 #FOR NOW HARDWIRED, TO BE MODIFIED
self.prescale_low.write(prescale & 0xff)
self.prescale_high.write((prescale & 0xff00) >> 8)
#Enable core
self.ctrl.write(0x1 << 7)
self.target.dispatch()
def checkack(self):
inprogress = True
ack = False
while inprogress:
cmd_stat = self.cmd_stat.read()
self.target.dispatch()
inprogress = (cmd_stat & I2CCore.inprogress) > 0
ack = (cmd_stat & I2CCore.recvdack) == 0
return ack
def delayorcheckack(self):
ack = True
if self.delay is None:
ack = self.checkack()
else:
time.sleep(self.delay)
ack = self.checkack()#Remove this?
return ack
################################################################################
# /*
# I2C WRITE
# */
################################################################################
def write(self, addr, data, stop=True):
"""Write data to the device with the given address."""
# Start transfer with 7 bit address and write bit (0)
nwritten = -1
addr &= 0x7f
addr = addr << 1
startcmd = 0x1 << 7
stopcmd = 0x1 << 6
writecmd = 0x1 << 4
#Set transmit register (write operation, LSB=0)
self.data.write(addr)
#Set Command Register to 0x90 (write, start)
self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
nwritten += 1
for val in data:
val &= 0xff
#Write slave memory address
self.data.write(val)
#Set Command Register to 0x10 (write)
self.cmd_stat.write(I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
nwritten += 1
if stop:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return nwritten
################################################################################
# /*
# I2C READ
# */
################################################################################
def read(self, addr, n):
"""Read n bytes of data from the device with the given address."""
# Start transfer with 7 bit address and read bit (1)
data = []
addr &= 0x7f
addr = addr << 1
addr |= 0x1 # read bit
self.data.write(addr)
self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
self.target.dispatch()
ack = self.delayorcheckack()
if not ack:
self.cmd_stat.write(I2CCore.stopcmd)
self.target.dispatch()
return data
for i in range(n):
if i < (n-1):
self.cmd_stat.write(I2CCore.readcmd) # <---
else:
self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
self.target.dispatch()
ack = self.delayorcheckack()
val = self.data.read()
self.target.dispatch()
data.append(val & 0xff)
#self.cmd_stat.write(I2CCore.stopcmd)
#self.target.dispatch()
return data
################################################################################
# /*
# I2C WRITE-READ
# */
################################################################################
# def writeread(self, addr, data, n):
# """Write data to device, then read n bytes back from it."""
# nwritten = self.write(addr, data, stop=False)
# readdata = []
# if nwritten == len(data):
# readdata = self.read(addr, n)
# return nwritten, readdata
"""
SPI core XML:
<node description="SPI master controller" fwinfo="endpoint;width=3">
<node id="d0" address="0x0" description="Data reg 0"/>
<node id="d1" address="0x1" description="Data reg 1"/>
<node id="d2" address="0x2" description="Data reg 2"/>
<node id="d3" address="0x3" description="Data reg 3"/>
<node id="ctrl" address="0x4" description="Control reg"/>
<node id="divider" address="0x5" description="Clock divider reg"/>
<node id="ss" address="0x6" description="Slave select reg"/>
</node>
"""
class SPICore:
go_busy = 0x1 << 8
rising = 1
falling = 0
def __init__(self, target, wclk, spiclk, basename="io.spi"):
self.target = target
# Only a single data register is required since all transfers are
# 16 bit long
self.data = target.getNode("%s.d0" % basename)
self.control = target.getNode("%s.ctrl" % basename)
self.control_val = 0b0
self.divider = target.getNode("%s.divider" % basename)
self.slaveselect = target.getNode("%s.ss" % basename)
self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
self.divider_val = 0x7f
self.configured = False
def config(self):
"Configure SPI interace for communicating with ADCs."
self.divider_val = int(self.divider_val) % 0xffff
if verbose:
print "Configuring SPI core, divider = 0x%x" % self.divider_val
self.divider.write(self.divider_val)
self.target.dispatch()
self.control_val = 0x0
self.control_val |= 0x0 << 13 # Automatic slave select
self.control_val |= 0x0 << 12 # No interrupt
self.control_val |= 0x0 << 11 # MSB first
# ADC samples data on rising edge of SCK
self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
# ADC changes output shortly after falling edge of SCK
self.control_val |= 0x0 << 9 # read input on rising edge
self.control_val |= 0x10 # 16 bit transfers
if verbose:
print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
self.configured = True
def transmit(self, chip, value):
if not self.configured:
self.config()
assert chip >= 0 and chip < 8
value &= 0xffff
self.data.write(value)
checkdata = self.data.read()
self.target.dispatch()
assert checkdata == value
self.control.write(self.control_val)
self.slaveselect.write(0xff ^ (0x1 << chip))
self.target.dispatch()
self.control.write(self.control_val | SPICore.go_busy)
self.target.dispatch()
busy = True
while busy:
status = self.control.read()
self.target.dispatch()
busy = status & SPICore.go_busy > 0
self.slaveselect.write(0xff)
data = self.data.read()
ss = self.slaveselect.read()
status = self.control.read()
self.target.dispatch()
#print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
return data
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EUDETdummy/scripts/I2cBusProperties.py deleted 100644 → 0
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##########################################################
# I2cBusProperties - simple encapsulation of all items
# required to control an I2C bus.
#
# Carl Jeske, July 2010
# Refactored by Robert Frazier, May 2011
##########################################################
class I2cBusProperties(object):
"""Encapsulates details of an I2C bus master in the form of a host device, a clock prescale value, and seven I2C master registers
Provide the ChipsBus instance to the device hosting your I2C core, a 16-bit clock prescaling
value for the Serial Clock Line (see I2C core docs for details), and the names of the seven
registers that define/control the bus (assuming these names are not the defaults specified
in the constructor below). The seven registers consist of the two clock pre-scaling
registers (PRElo, PREhi), and five bus master registers (CONTROL, TRANSMIT, RECEIVE,
COMMAND and STATUS).
Usage: You'll need to create an instance of this class to give to a concrete I2C bus instance, such
as OpenCoresI2cBus. This I2cBusProperties class is simply a container to hold the properties
that define the bus; a class such as OpenCoresI2cBus will make use of these properties.
Access the items stored by this class via these (deliberately compact) variable names:
chipsBus -- the ChipsBus device hosting the I2C core
preHiVal -- the top byte of the clock prescale value
preLoVal -- the bottom byte of the clock prescale value
preHiReg -- the register the top byte of the clk prescale value (preHiVal) gets written to
preLoReg -- the register the bottom byte of the clk prescale value (preLoVal) gets written to
ctrlReg -- the I2C Control register
txReg -- the I2C Transmit register
rxReg -- the I2C Receive register
cmdReg -- the I2C Command register
statusReg -- the I2C Status register
Compatibility Notes: The seven register names are the registers typically required to operate an
OpenCores or similar I2C Master (Lattice Semiconductor's I2C bus master works
the same way as the OpenCores one). This software is not compatible with your
I2C bus master if it doesn't use this register interface.
"""
def __init__(self,
chipsBusDevice,
clkPrescaleU16,
clkPrescaleLoByteReg = "i2c_pre_lo",
clkPrescaleHiByteReg = "i2c_pre_hi",
controlReg = "i2c_ctrl",
transmitReg = "i2c_tx",
receiveReg = "i2c_rx",
commandReg = "i2c_cmd",
statusReg = "i2c_status"):
"""Provide a host ChipsBus device that is controlling the I2C bus, and the names of five I2C control registers.
chipsBusDevice: Provide a ChipsBus instance to the device where the I2C bus is being
controlled. The address table for this device must contain the five registers
that control the bus, as declared next...
clkPrescaleU16: A 16-bit value used to prescale the Serial Clock Line based on the host
master-clock. This value gets split into two 8-bit values and ultimately will
get written to the two I2C clock-prescale registers as declared below. See
the OpenCores or Lattice Semiconductor I2C documentation for more details.
clkPrescaleLoByteReg: The register where the lower byte of the clock prescale value is set. The default
name for this register is "i2c_pre_lo".
clkPrescaleHiByteReg: The register where the higher byte of the clock prescale value is set. The default
name for this register is "i2c_pre_hi"
controlReg: The CONTROL register, used for enabling/disabling the I2C core, etc. This register is
usually read and write accessible. The default name for this register is "i2c_ctrl".
transmitReg: The TRANSMIT register, used for holding the data to be transmitted via I2C, etc. This
typically shares the same address as the RECEIVE register, but has write-only access. The default
name for this register is "i2c_tx".
receiveReg: The RECEIVE register - allows access to the byte received over the I2C bus. This
typically shares the same address as the TRANSMIT register, but has read-only access. The
default name for this register is "i2c_rx".
commandReg: The COMMAND register - stores the command for the next I2C operation. This typically
shares the same address as the STATUS register, but has write-only access. The default name for
this register is "i2c_cmd".
statusReg: The STATUS register - allows monitoring of the I2C operations. This typically shares
the same address as the COMMAND register, but has read-only access. The default name for this
register is "i2c_status".
"""
object.__init__(self)
self.chipsBus = chipsBusDevice
self.preHiVal = ((clkPrescaleU16 & 0xff00) >> 8)
self.preLoVal = (clkPrescaleU16 & 0xff)
# Check to see all the registers are in the address table
registers = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, receiveReg, commandReg, statusReg]
for reg in registers:
if not self.chipsBus.addrTable.checkItem(reg):
raise ChipsException("I2cBusProperties error: register '" + reg + "' is not present in the address table of the device hosting the I2C bus master!")
# Check that the registers we'll need to write to are indeed writable
writableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, commandReg]
for wReg in writableRegisters:
if not self.chipsBus.addrTable.getItem(wReg).getWriteFlag():
raise ChipsException("I2cBusProperties error: register '" + wReg + "' does not have the necessary write permission!")
# Check that the registers we'll need to read from are indeed readable
readableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, receiveReg, statusReg]
for rReg in readableRegisters:
if not self.chipsBus.addrTable.getItem(rReg).getReadFlag():
raise ChipsException("I2cBusProperties error: register '" + rReg + "' does not have the necessary read permission!")
# Store the various register name strings
self.preHiReg = clkPrescaleHiByteReg
self.preLoReg = clkPrescaleLoByteReg
self.ctrlReg = controlReg
self.txReg = transmitReg
self.rxReg = receiveReg
self.cmdReg = commandReg
self.statusReg = statusReg
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# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class PCA9539PW:
#Class to configure the expander modules
def __init__(self, i2c, slaveaddr=0x74):
self.i2c = i2c
self.slaveaddr = slaveaddr
def writeReg(self, regN, regContent, verbose=False):
#Basic functionality to write to register.
if (regN < 0) | (regN > 7):
print "PCA9539PW - ERROR: register number should be in range [0:7]"
return
regContent= regContent & 0xFF
mystop=True
cmd= [regN, regContent]
self.i2c.write( self.slaveaddr, cmd, mystop)
def readReg(self, regN, nwords, verbose=False):
#Basic functionality to read from register.
if (regN < 0) | (regN > 7):
print "PCA9539PW - ERROR: register number should be in range [0:7]"
return
mystop=False
self.i2c.write( self.slaveaddr, [regN], mystop)
res= self.i2c.read( self.slaveaddr, nwords)
return res
def setInvertReg(self, regN, polarity= 0x00):
#Set the content of register 4 or 5 which determine the polarity of the
#ports (0= normal, 1= inverted).
if (regN < 0) | (regN > 1):
print "PCA9539PW - ERROR: regN should be 0 or 1"
return
polarity = polarity & 0xFF
self.writeReg(regN+4, polarity)
def getInvertReg(self, regN):
#Read the content of register 4 or 5 which determine the polarity of the
#ports (0= normal, 1= inverted).
if (regN < 0) | (regN > 1):
print "PCA9539PW - ERROR: regN should be 0 or 1"
return
res= self.readReg(regN+4, 1)
return res
def setIOReg(self, regN, direction= 0xFF):
#Set the content of register 6 or 7 which determine the direction of the
#ports (0= output, 1= input).
if (regN < 0) | (regN > 1):
print "PCA9539PW - ERROR: regN should be 0 or 1"
return
direction = direction & 0xFF
self.writeReg(regN+6, direction)
def getIOReg(self, regN):
#Read the content of register 6 or 7 which determine the polarity of the
#ports (0= normal, 1= inverted).
if (regN < 0) | (regN > 1):
print "PCA9539PW - ERROR: regN should be 0 or 1"
return
res= self.readReg(regN+6, 1)
return res
def getInputs(self, bank):
#Read the incoming values of the pins for one of the two 8-bit banks.
if (bank < 0) | (bank > 1):
print "PCA9539PW - ERROR: bank should be 0 or 1"
return
res= self.readReg(bank, 1)
return res
def setOutputs(self, bank, values= 0x00):
#Set the content of the output flip-flops.
if (bank < 0) | (bank > 1):
print "PCA9539PW - ERROR: bank should be 0 or 1"
return
values = values & 0xFF
self.writeReg(bank+2, values)
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# Created on Sep 10, 2012
# @author: Kristian Harder, based on code by Carl Jeske
from I2cBusProperties import I2cBusProperties
from ChipsBus import ChipsBus
from ChipsLog import chipsLog
from ChipsException import ChipsException
class RawI2cAccess:
def __init__(self, i2cBusProps, slaveAddr):
# For performing read/writes over an OpenCores-compatible I2C bus master
#
# An instance of this class is required to communicate with each
# I2C slave on the I2C bus.
#
# i2cBusProps: an instance of the class I2cBusProperties that contains
# the relevant ChipsBus host and the I2C bus-master registers (if
# they differ from the defaults specified by the I2cBusProperties
# class).
#
#slaveAddr: The address of the I2C slave you wish to communicate with.
#
self._i2cProps = i2cBusProps # The I2C Bus Properties
self._slaveAddr = 0x7f & slaveAddr # 7-bit slave address
def resetI2cBus(self):
# Resets the I2C bus
#
# This function does the following:
# 1) Disables the I2C core
# 2) Sets the clock prescale registers
# 3) Enables the I2C core
# 4) Sets all writable bus-master registers to default values
try:
self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x00)
#self._chipsBus().getNode(self._i2cProps.ctrlReg).write(0)
self._chipsBus().queueWrite(self._i2cProps.preHiReg,
self._i2cProps.preHiVal)
self._chipsBus().queueWrite(self._i2cProps.preLoReg,
self._i2cProps.preLoVal)
self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x80)
self._chipsBus().queueWrite(self._i2cProps.txReg, 0x00)
self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x00)
self._chipsBus().queueRun()
except ChipsException, err:
raise ChipsException("I2C reset error:\n\t" + str(err))
def read(self, numBytes):
# Performs an I2C read. Returns the 8-bit read result(s).
#
# numBytes: number of bytes expected as response
#
try:
result = self._privateRead(numBytes)
except ChipsException, err:
raise ChipsException("I2C read error:\n\t" + str(err))
return result
def write(self, listDataU8):
# Performs an 8-bit I2C write.
#
# listDataU8: The 8-bit data values to be written.
#
try:
self._privateWrite(listDataU8)
except ChipsException, err:
raise ChipsException("I2C write error:\n\t" + str(err))
return
def _chipsBus(self):
# Returns the instance of the ChipsBus device that's hosting
# the I2C bus master
return self._i2cProps.chipsBus
def _privateRead(self, numBytes):
# I2C read implementation.
#
# Fast I2C read implementation,
# i.e. done with the fewest packets possible.
# transmit reg definitions
# bits 7-1: 7-bit slave address during address transfer
# or first 7 bits of byte during data transfer
# bit 0: RW flag during address transfer or LSB during data transfer.
# '1' = reading from slave
# '0' = writing to slave
# command reg definitions
# bit 7: Generate start condition
# bit 6: Generate stop condition
# bit 5: Read from slave
# bit 4: Write to slave
# bit 3: 0 when acknowledgement is received
# bit 2:1: Reserved
# bit 0: Interrupt acknowledge. When set, clears a pending interrupt
# Reset bus before beginning
self.resetI2cBus()
# Set slave address in bits 7:1, and set bit 0 to zero
# (i.e. we're writing an address to the bus)
self._chipsBus().queueWrite(self._i2cProps.txReg,
(self._slaveAddr << 1) | 0x01)
# Set start and write bit in command reg
self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
# Run the queue
self._chipsBus().queueRun()
# Wait for transaction to finish.
self._i2cWaitUntilFinished()
result=[]
for ibyte in range(numBytes):
if ibyte==numBytes-1:
stop_bit=0x40
ack_bit=0x08
else:
stop_bit=0
ack_bit=0
pass
# Set read bit, acknowledge and stop bit in command reg
self._chipsBus().write(self._i2cProps.cmdReg, 0x20+ack_bit+stop_bit)
# Wait for transaction to finish.
# Don't expect an ACK, do expect bus free at finish.
if stop_bit:
self._i2cWaitUntilFinished(requireAcknowledgement = False,
requireBusIdleAtEnd = True)
else:
self._i2cWaitUntilFinished(requireAcknowledgement = False,
requireBusIdleAtEnd = False)
pass
result.append(self._chipsBus().read(self._i2cProps.rxReg))
return result
def _privateWrite(self, listDataU8):
# I2C write implementation.
#
# Fast I2C write implementation,
# i.e. done with the fewest packets possible.
# transmit reg definitions
# bits 7-1: 7-bit slave address during address transfer
# or first 7 bits of byte during data transfer
# bit 0: RW flag during address transfer or LSB during data transfer.
# '1' = reading from slave
# '0' = writing to slave
# command reg definitions
# bit 7: Generate start condition
# bit 6: Generate stop condition
# bit 5: Read from slave
# bit 4: Write to slave
# bit 3: 0 when acknowledgement is received
# bit 2:1: Reserved
# bit 0: Interrupt acknowledge. When set, clears a pending interrupt
# Reset bus before beginning
self.resetI2cBus()
# Set slave address in bits 7:1, and set bit 0 to zero (i.e. "write mode")
self._chipsBus().queueWrite(self._i2cProps.txReg,
(self._slaveAddr << 1) & 0xfe)
# Set start and write bit in command reg
self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
# Run the queue
self._chipsBus().queueRun()
# Wait for transaction to finish.
self._i2cWaitUntilFinished()
for ibyte in range(len(listDataU8)):
dataU8 = listDataU8[ibyte]
if ibyte==len(listDataU8)-1:
stop_bit=0x40
else:
stop_bit=0x00
pass
# Set data to be written in transmit reg
self._chipsBus().queueWrite(self._i2cProps.txReg, (dataU8 & 0xff))
# Set write and stop bit in command reg
self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x10+stop_bit)
# Run the queue
self._chipsBus().queueRun()
# Wait for transaction to finish.
# Do expect an ACK and do expect bus to be free at finish
if stop_bit:
self._i2cWaitUntilFinished(requireAcknowledgement = True,
requireBusIdleAtEnd = True)
else:
self._i2cWaitUntilFinished(requireAcknowledgement = True,
requireBusIdleAtEnd = False)
pass
pass
return
def _i2cWaitUntilFinished(self, requireAcknowledgement = True,
requireBusIdleAtEnd = False):
# Ensures the current bus transaction has finished successfully
# before allowing further I2C bus transactions
# This method monitors the status register
# and will not allow execution to continue until the
# I2C bus has completed properly. It will throw an exception
# if it picks up bus problems or a bus timeout occurs.
maxRetry = 20
attempt = 1
while attempt <= maxRetry:
# Get the status
i2c_status = self._chipsBus().read(self._i2cProps.statusReg)
receivedAcknowledge = not bool(i2c_status & 0x80)
busy = bool(i2c_status & 0x40)
arbitrationLost = bool(i2c_status & 0x20)
transferInProgress = bool(i2c_status & 0x02)
interruptFlag = bool(i2c_status & 0x01)
if arbitrationLost: # This is an instant error at any time
raise ChipsException("I2C error: Arbitration lost!")
if not transferInProgress:
break # The transfer looks to have completed successfully, pending further checks
attempt += 1
# At this point, we've either had too many retries, or the
# Transfer in Progress (TIP) bit went low. If the TIP bit
# did go low, then we do a couple of other checks to see if
# the bus operated as expected:
if attempt > maxRetry:
raise ChipsException("I2C error: Transaction timeout - the 'Transfer in Progress' bit remained high for too long!")
if requireAcknowledgement and not receivedAcknowledge:
raise ChipsException("I2C error: No acknowledge received!")
if requireBusIdleAtEnd and busy:
raise ChipsException("I2C error: Transfer finished but bus still busy!")
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*RegName RegAddr RegMask R W
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
*
* DUT interfaces base = 0x020
DUTMaskW 0x00000020 0xffffffff 0 1
IgnoreDUTBusyW 0x00000021 0xffffffff 0 1
IgnoreShutterVetoW 0x00000022 0xffffffff 0 1
DUTInterfaceModeW 0x00000023 0xffffffff 0 1
DUTInterfaceModeModifierW 0x00000024 0xffffffff 0 1
DUTMaskR 0x00000028 0xffffffff 1 0
IgnoreDUTBusyR 0x00000029 0xffffffff 1 0
IgnoreShutterVetoR 0x0000002A 0xffffffff 1 0
DUTInterfaceModeR 0x0000002B 0xffffffff 1 0
DUTInterfaceModeModifierR 0x0000002C 0xffffffff 1 0
*
* trigger inputs = 0x040
SerdesRstW 0x00000040 0xffffffff 0 1
SerdesRstR 0x00000048 0xffffffff 1 0
ThrCount0R 0x00000049 0xffffffff 1 0
ThrCount1R 0x0000004a 0xffffffff 1 0
ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
*
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 0 1
TriggerPatternW 0x00000063 0xffffffff 0 1
TriggerVetoW 0x00000064 0xffffffff 0 1
PulseStretchW 0x00000066 0xffffffff 0 1
PulseDelayW 0x00000067 0xffffffff 0 1
TriggerHoldOffW 0x00000068 0xffffffff 0 1
PostVetoTriggersR 0x00000070 0xffffffff 1 0
PreVetoTriggersR 0x00000071 0xffffffff 1 0
InternalTriggerIntervalR 0x00000072 0xffffffff 1 0
TriggerPatternR 0x00000073 0xffffffff 1 0
TriggerVetoR 0x00000074 0xffffffff 1 0
ExternalTriggerVetoR 0x00000075 0xffffffff 1 0
PulseStretchR 0x00000076 0xffffffff 1 0
PulseDelayR 0x00000077 0xffffffff 1 0
TriggerHoldOffR 0x00000078 0xffffffff 1 0
AuxTriggerCountR 0x00000079 0xffffffff 1 0
*
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
EventFifoFillLevel 0x00000081 0xffffffff 1 0
EventFifoCSR 0x00000082 0xffffffff 1 1
EventFifoFillLevelFlags 0x00000083 0xffffffff 1 0
*
* logic clocks = 0x0A0
LogicClocksCSR 0x000000A0 0xffffffff 1 1
LogicRst 0x000000A1 0xffffffff 0 1
*
* I2C = 0x0C0
i2c_pre_lo 0x000000C0 0x000000ff 1 1
i2c_pre_hi 0x000000C1 0x000000ff 1 1
i2c_ctrl 0x000000C2 0x000000ff 1 1
i2c_tx 0x000000C3 0x000000ff 0 1
i2c_rx 0x000000C3 0x000000ff 1 0
i2c_cmd 0x000000C4 0x000000ff 0 1
i2c_status 0x000000C4 0x000000ff 1 0
*
* Event formatter = 0x140
Enable_Record_Data 0x00000140 0xffffffff 1 1
ResetTimestampW 0x00000141 0xffffffff 0 1
CurrentTimestampLR 0x00000142 0xffffffff 1 0
CurrentTimestampHR 0x00000143 0xffffffff 1 0
*
* Shutter/T0 control = 0x160
ShutterStateW 0x00000160 0xffffffff 0 1
PulseT0 0x00000161 0xffffffff 0 1
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