Backing out changes to T0/Sync generator going back to generating T0 pulse

components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd

@@ -81,7 +81,7 @@ ARCHITECTURE rtl OF T0_Shutter_Iface IS
   signal s_enable_sequence : std_logic ; --! take high to enable sequence
   signal s_enable_internal_cycle : std_logic ; --! take high to enable internal sequence
   signal s_T0_ipbus : std_logic; --! T0 synchronization signal on IPBus clock domain.
-  signal s_run_active : std_logic; --! Take active to issue T0 pulse and enable shutters
+--  signal s_run_active : std_logic; --! Take active to issue T0 pulse and enable shutters
   constant c_NUM_CTRL_REGS  : integer := 9;
   constant c_NUM_STAT_REGS  : integer := 1;
   signal s_ipbus_statusregs:   ipb_reg_v(c_NUM_STAT_REGS - 1 downto 0) := (others => (others => '0'));
@@ -131,8 +131,9 @@ begin
       rstb => open
       );
 
-  s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active ) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
-  s_run_active <= s_ipbus_controlregs(8)(0); --! Set to 1 to issue T0 and start shutter 
+--  s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active ) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
+  s_enable_sequence <=  s_ipbus_controlregs(0)(0)  when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
+--  s_run_active <= s_ipbus_controlregs(8)(0); --! Set to 1 to issue T0 and start shutter 
   
   s_enable_internal_cycle <= s_ipbus_controlregs(0)(1);
   s_trigger_source_select <= s_ipbus_controlregs(1);
@@ -147,25 +148,26 @@ begin
   -- A bodge. I can't figure out which standard IPBus register generates a
   -- pulse, so put this logic in parallel.
   --------------------
- -- ipbus_generateT0: process (ipbus_clk_i)
- -- begin  -- process ipbus_clk_i
- -- if rising_edge(ipbus_clk_i) then
---
---      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
---        s_T0_ipbus <= '1'; -- set T0 signal high
---      else
---        s_T0_ipbus <= '0';
---      end if;
+  ipbus_generateT0: process (ipbus_clk_i)
+  begin  -- process ipbus_clk_i
+  if rising_edge(ipbus_clk_i) then
+
+      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
+        s_T0_ipbus <= '1'; -- set T0 signal high
+      else
+        s_T0_ipbus <= '0';
+      end if;
 
---    end if;
---  end process ipbus_generateT0;
+    end if;
+  end process ipbus_generateT0;
 
   --! Retime T0 generated by IPBus onto clk_4x and align with strobe
   cmp_T0_retime: entity work.stretchPulse4x
     port map (
       clk_4x_i      => clk_4x_i,
       clk_4x_strobe_i => clk_4x_strobe_i,
-      pulse_i       => s_run_active,
+--      pulse_i       => s_run_active,
+      pulse_i       => s_T0_ipbus 
       pulse_o       => T0_o);
 
 END rtl;